Texas Instruments SN74AHC123ADBR, SN74AHC123ADGVR, SN74AHC123AN, SN74AHC123APWR, SNJ54AHC123AFK Datasheet
SN54AHC123A, SN74AHC123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS352E – JULY 1997 – REVISED JANUAR Y 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
D
Schmitt-Trigger Circuitry On A, B, and CLR
CC
Inputs for Slow Input Transition Rates
D
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D
Retriggerable for Very Long Output Pulses
D
Overriding Clear Terminates Output Pulse
D
Glitch-Free Power-Up Reset On Outputs
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
SN54AHC123A ...J OR W PACKAGE
SN74AHC123A . . . D, DB, DGV, N, OR PW PACKAGE
1CLR
2R
ext/Cext
SN54AHC123A . . . FK PACKAGE
1CLR
1Q
NC
2Q
2C
ext
(TOP VIEW)
1A
1B
1Q
2Q
2C
ext
GND
1B1ANC
3212019
4
5
6
7
8
910111213
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
(TOP VIEW)
CC
V
V
CC
1R
ext/Cext
1C
ext
1Q
2Q
2CLR
2B
2A
ext
/C
ext
1R
18
17
16
15
14
1C
ext
1Q
NC
2Q
2CLR
description
NC
2A
2B
ext
/C
The ’AHC123A devices are dual retriggerable
monostable multivibrators designed for 2-V to
5.5-V VCC operation.
These edge-triggered multivibrators feature
NC – No internal connection
GND
ext
2R
output pulse-duration control by three methods. In
the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and
the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes
high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between C
between R
R
ext/Cext
ext/Cext
and VCC. The output pulse duration also can be reduced by taking CLR low.
and VCC. T o obtain variable pulse durations, connect an external variable resistance between
ext
and R
ext/Cext
(positive) and an external resistor connected
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override
A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early
clearing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, T exas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54AHC123A, SN74AHC123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS352E – JULY 1997 – REVISED JANUAR Y 2000
description (continued)
The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’AHC123A is shown in Figure 10. V ariations in output pulse
duration versus supply voltage and temperature are shown in Figure 6.
During power up, Q outputs are in the high state, and Q outputs are in the low state. The outputs are glitch free
without applying a reset pulse.
The SN54AHC123A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC123A is characterized for operation from –40°C to 85°C.
For additional application information on multivibrators, see the application report
SN74AHC123A and SN74AHCT123A
logic symbol
‡
1CLR
1C
1R
ext/Cext
2CLR
2C
2R
ext/Cext
1A
1B
ext
2A
2B
ext
, literature number SCLA014.
FUNCTION TABLE
(each multivibrator)
INPUTS
CLR
†
These outputs are based on the
assumption that the indicated steady-state
conditions at the A and B inputs have been
set up long enough to complete any pulse
started before the setup.
1
2
3
14
15
9
10
11
6
7
A B Q Q
L X X L H
X HXL†H
X XLL†H
H L ↑
H
#
↑ L H
&
R
CX
RX/CX
&
R
CX
RX/CX
OUTPUTS
H
†
†
13
1Q
4
1Q
5
2Q
12
2Q
Designing With The
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
logic diagram, each multivibrator (positive logic)
A
SN54AHC123A, SN74AHC123A
SCLS352E – JULY 1997 – REVISED JANUAR Y 2000
R
ext/Cext
C
ext
CLR
input/output timing diagram
A
B
CLR
R
ext/Cext
Q
B
R
Q
Q
t
rr
Q
t
w
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
w
tw + t
rr
3
SN54AHC123A, SN74AHC123A
UNIT
mA
mA
R
External timing resistance
Ω
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS352E – JULY 1997 – REVISED JANUAR Y 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range in high or low state, V
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . .
O
†
Output voltage range in power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to the network ground terminal.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54AHC123A SN74AHC123A
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
ext
∆t/∆V
T
A
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
High-level input voltage
Low-level input voltage
Input voltage 0 5.5 0 5.5 V
Output voltage 0 V
High-level output current
Low-level output current
Power-up ramp rate 1 1 ms/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VCC = 3 V
VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8 8
VCC = 2 V 5k 5k
VCC > 3 V 1k 1k
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
4
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