Texas Instruments SN74ACT7808-30PM, SN74ACT7808-40FN, SN74ACT7808-40PAG, SN74ACT7808-40PM, SN74ACT7808-20FN Datasheet
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SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
D
Load Clocks and Unload Clocks Can Be
Asynchronous or Coincident
D
2048 Words by 9 Bits
D
Low-Power Advanced CMOS Technology
D
Fast Access Times of 15 ns With a 50-pF
Load
D
Programmable Almost-Full/Almost-Empty
Flag
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7808 is a 2048-word by 9-bit FIFO designed for high speed and fast access times.
It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.
Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a
low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked
in exceeds the number of words clocked out by 2048. When the memory is full, LDCK signals have no effect
on the data residing in memory. When the memory is empty, UNCK signals have no effect.
D
Expansion Logic for Depth Cascading
D
Empty, Full, and Half-Full Flags
D
Fall-Through Time of 20 ns Typical
D
Data Rates up to 50 MHz
D
3-State Outputs
D
Package Options Include 44-Pin Plastic
Leaded Chip Carrier (FN), 64-Pin Thin Quad
Flat (PM), and Reduced-Height 64-Pin Quad
Flat (PAG) Packages
Status of the FIFO memory is monitored by the full (FULL
almost-full/almost-empty (AF/AE) flags. The FULL
memory is not full. The EMPTY
output is high when the FIFO contains 1024 or more words and is low when it contains 1023 or fewer words.
The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset
can be used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable
(PEN
) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (2048 – Y) or more words.
The AF/AE flag is low when the FIFO contains between (X + 1) and (2047 – Y) words.
A low level on the reset (RESET
low, and EMPTY
The first word loaded into empty memory causes EMPTY
It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect
to the data inputs and are in the high-impedance state when the output-enable (OE) input is low. OE does not
affect the output flags.
Cascading is easily accomplished in the word-width and word-depth directions. When not using the FIFO in
depth expansion, cascade enable (CASEN
The FIFO must be reset upon power up.
The SN74ACT7808 is characterized for operation from 0°C to 70°C.
low. The Q outputs are not reset to any specific logic level.
output is low when the memory is empty and high when it is not empty . The HF
) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
) must be tied high.
output is low when the memory is full and high when the
to go high and the data to appear on the Q outputs.
), empty (EMPTY), half-full (HF), and
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
FN PACKAGE
(TOP VIEW)
NC
Q0
GND
GND
OE
XO
V
CC
V
CC
RESET
PEN
GND
GND
AF/AE
HF
V
CC
V
CC
CC
HF
AF/AE
GND
D0
D1
D2
GND
D3
D4
D5
V
CC
D6
D7
D8
V
6 5 4 3 2 1 44 43 42 41 40
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
XI
DP9
GND
LDCK
PAG OR PM PACKAGE
(TOP VIEW)
CCVCC
V
Q1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 19 20 21 22 23 24 25 26 27 2817 29 30 31 32
Q2
GND
GNDQ3Q4
PEN
RESET
FULL
EMPTY
V
VCCV
CC
FL
XOOEGND
UNCK
CASEN
CC
Q5
Q6
Q0
39
38
37
36
35
34
33
32
31
30
29
Q8
GND
GND
Q7
Q1
V
CC
Q2
Q3
GND
Q4
V
CC
Q5
Q6
GND
Q7
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
Q8
V
CC
V
CC
UNCK
CASEN
NC
FL
EMPTY
FULL
XI
DP9
LDCK
GND
GND
NC
D1
NC
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GND
D2
D0
GND
D3
D4
NC
D5
V
CC
D8
D6
D7
CC
V
NC
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
logic symbol
†
RESET
LDCK
UNCK
CASEN CASCADE ENABLE
1
19
26
42
OE
2
PEN PROGRAM ENABLE
24
FL FIRST LOAD
25
21
XI
20
DP9
7
D0
8
D1
9
D2
11
D3
12
D4
13
D5
15
D6
16
D7
17
D8
RESET
LDCK
UNCK
EN1
EXPANSION IN
DATA PIN 9
0
8
Φ
FIFO 2048 × 9
SN74ACT7808
ALMOST FULL/EMPTY
EXPANSION OUT
Data
HALF FULL
Data
FULL
EMPTY
1
22
FULL
5
HF
4
AF/AE
23
EMPTY
43
XO
40
0
8
39
37
36
34
32
31
29
28
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
functional block diagram
OE
D0–D8
UNCK
Read
Pointer
Location 1
Location 2
2048 × 9 RAM
LDCK
DP9
RESET
PEN
FL
CASEN
Write
Pointer
Reset
Logic
Expansion
and
Status-Flag
Logic
XI
Location 2047
Location 2048
Q0–Q8
EMPTY
FULL
HF
AF/AE
XO
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
of one device must be connected to the XI of the next device in the chain. The XO of the last device in the chain is
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
AF/AE O
CASEN
D0–D8 I Nine-bit data input port
DP9 I DP9 is used as the most significant bit when programming the AF/AE offset values.
EMPTY O Empty flag. EMPTY is low when the FIFO memory is empty. A FIFO reset also causes EMPTY to go low.
†
FL
FULL O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF O Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.
LDCK I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE I Output enable. When OE is low, D0–D8 are in the high-impedance state.
PEN I
Q0–Q8 O Nine-bit data output port
RESET I Reset. A low level on RESET resets the FIFO and drives FULL and AF/AE high and HF and EMPTY low.
UNCK I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
†
XI
†
XO
†
See Figures 6 and 7 for application information on FIFO word-width and word-depth expansions, respectively.
I/O DESCRIPTION
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE or the default value of 256 can be
used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer
words or (2048 – Y) or more words. AF/AE is high after reset.
†
Cascade enable. When multiple SN74ACT7808 devices are depth cascaded, every device must have CASEN tied low.
I
CASEN
must be tied high when a device is not used in depth expansion.
First load. When multiple SN74ACT7808 devices are depth cascaded, the first device in the chain must have its FL
I
input tied low and all other devices must have their FL inputs tied high.
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D8 and DP9 is
latched as an AF/AE offset value when PEN
Expansion input (XI) and expansion output (XO). When multiple SN74ACT7808 devices are depth cascaded, the XO
I
O
connected to the XI of the first device in the chain.
is low and LDCK is high.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ACT7808
ÎÎ
ÎÎ
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the
offsets are not programmed, the default values of X = Y = 256 are used. The AF/AE flag is high when the FIFO
contains X or fewer words or (2048 – Y) or more words.
T o program the offset values, program enable (PEN
) can be brought low after reset only when LDCK is low. On
the following low-to-high transition of LDCK, the binary value on D0–D8 and DP9 is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PEN
low for another low-to-high transition of LDCK
reprograms Y to the binary value on D0–D8 and DP9 at the time of the second LDCK low-to-high transition.
Writes to the FIFO memory are disabled while the offsets are programmed. A maximum value of 1023 can be
programmed for either X or Y (see Figure 1). To use the default values of X = Y = 256, PEN
RESET
LDCK
PEN
D0–D8
Don’t Care
X and Y Y
Don’t Care
must be held high.
DP9
EMPTY
Don’t Care
X and Y MSB Y MSB
Figure 1. Programming X and Y Separately
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
RESET
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PEN
CASEN
LDCK
D0–D8
UNCK
OE
Q0–Q8
EMPTY
AF/AE
W1 W2
(X+1)
1
0
1
0
W
W1024
W
(2048–Y)
W2048
Don’t Care
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
W
W1
W2 W1025 W1026
(Y+1)
(Y+2)
W
W
W
(2048–X)
(2049–x)
W2047
W2048
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
7
Figure 2
HF
FULL
Define the AF/AE Flag Using
the Default Value or X and Y
SN74ACT7808
Figure 2. Read
SN74ACT7808
UNIT
VIHHigh-level input voltage
V
IOLLow-level output current
mA
V
V
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1): FN package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
PAG package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PM package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
’ACT7808-20 ’ACT7808-25 ’ACT7808-30 ’ACT7808-40
MIN MAX MIN MAX MIN MAX MIN MAX
V
V
I
OH
T
Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
CC
p
Low-level input voltage 0.8 0.8 0.8 0.8 V
IL
High-level output current –8 –8 –8 –8 mA
p
Operating free-air temperature 0 70 0 70 0 70 0 70 °C
A
XI 3.85 3.85 3.85 3.85
Other inputs 2 2 2 2
Q outputs 16 16 16 16
Flags 8 8 8 8
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
OH
Flags VCC = 4.5 V, IOL = 8 mA 0.5
OL
Q outputs VCC = 4.5 V, IOL = 16 mA 0.5
I
I
I
OZ
I
CC
§
∆I
CC
C
i
C
o
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
This is the increase in supply current for each input, excluding XI, that is at one of the specified TTL voltage levels rather 0 V or VCC.
VCC = 4.5 V, IOH = –8 mA 2.4 V
VCC = 5.5 V, VI =VCC or 0 ±5 µA
VCC = 5.5 V, VO =VCC or 0 ±5 µA
VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1 mA
VI = 0, f = 1 MHz 4 pF
VO = 0, f = 1 MHz 8 pF
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
twPulse duration
ns
h
PARAMETER
UNIT
t
A
Q
EMPTY
PHL
t
FULL
ns
t
AF/AE
ns
t
ns
t
HF
ns
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figures 1 through 3)
’ACT7808-20 ’ACT7808-25 ’ACT7808-30 ’ACT7808-40
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
t
su
t
h
Clock frequency 50 40 33.3 25 MHz
LDCK high or low 8 9 11 13
UNCK high or low 8 9 11 13
PEN low 9 9 11 13
RESET low 10 13 16 19
D0–D8, DP9 before LDCK↑ 5 5 5 5
Setup time
Hold time
LDCK inactive
before RESET
PEN before LDCK↑ 5 5 5 5
D0–D8, DP9 after LDCK↑ 0 0 0 0
LDCK inactive
after RESET
PEN low after LDCK↑ 4 4 4 4
PEN high after LDCK low 0 0 0 0
high
high
5 5 5 5
5 5 5 5
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
f
max
pd
‡
t
pd
t
PLH
t
PHL
PLH
pd
PLH
PHL
t
PLH
t
PHL
t
en
t
dis
t
en
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This parameter is measured with CL = 30 pF (see Figure 4).
= 50 pF (unless otherwise noted) (see Figure 3)
L
FROM TO
(INPUT) (OUTPUT)
LDCK or UNCK 50 40 33.3 25 MHz
LDCK↑
UNCK↑
UNCK↑
LDCK↑
UNCK↑
RESET low
LDCK↑
UNCK↑
RESET low
LDCK↑
UNCK↑
RESET low AF/AE 0 10 0 12 0 14 0 16
LDCK↑ HF 2 19 2 21 2 23 2 25
UNCK↑
RESET low
UNCK↑ XO 2 11 2 13 2 15 2 17 ns
LDCK↑ XO 2 11 2 13 2 15 2 17 ns
OE Any Q 1 10 1 12 1 14 1 16 ns
OE Any Q 1 9 1 11 1 13 1 15 ns
XI high Any Q 3 13 3 15 3 17 3 19 ns
XO high Any Q 4 4 4 4 ns
ny
Any Q 10 ns
EMPTY
FULL
’ACT7808-20 ’ACT7808-25 ’ACT7808-30 ’ACT7808-40
MIN TYP†MAX MIN MAX MIN MAX MIN MAX
5 20 5 22 5 25 5 28
4.5 11 15 4.5 18 4.5 20 4.5 22
4 15 4 17 4 19 4 21 ns
2 15 2 17 2 19 2 21
2 16 2 18 2 20 2 22
4 15 4 17 4 19 4 21
4 14 4 16 4 18 4 20
2 18 2 20 2 22 2 24
2 16 2 18 2 20 2 22
2 16 2 18 2 20 2 22
2 16 2 18 2 20 2 22
2 12 2 14 2 16 2 18
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 91 pF
pd
PARAMETER MEASUREMENT INFORMATION
7 V
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
h
Test
Point
500 Ω
3 V
0 V
3 V
0 V
Input
Output
Control
PARAMETER S1
t
t
t
t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
t
PZL
PZH
en
t
PZL
t
PHZ
dis
t
PLZ
t
PLH
pd
t
PHL
PULSE DURATION
t
PLZ
t
w
Open
Closed
Open
Closed
Open
Open
1.5 V1.5 V
3 V
0 V
3 V
0 V
Input
t
PLH
Output
NOTE A: CL includes probe and jig capacitance.
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELA Y TIMES
Figure 3. Load Circuit and Voltage Waveforms
10
3 V
0 V
t
PHL
V
OH
V
OL
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Output
Waveform 1
S1 at 7 V
Output
Waveform 2
S1 at Open
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PHZ
1.5 V
VOL + 0.3 V
VOH – 0.3 V
≈ 3.5 V
V
OL
V
OH
≈ 0 V
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
typ + 8
typ + 6
typ + 4
typ + 2
– Propagation Delay Time – ns
pd
t
typ – 2
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
VCC = 5 V
RL = 500 Ω
TA = 25°C
typ
0 50 100 150 200 250 300
CL – Load Capacitance – pF
Figure 4
SUPPLY CURRENT
CLOCK FREQUENCY
160
TA = 75°C
CL = 0 pF
140
VCC = 5 V
120
100
80
60
– Supply Current – mA
CC(f)
40
I
20
0
01020304050
f
– Clock Frequency – MHz
clock
Figure 5
vs
VCC = 5.5 V
VCC = 4.5 V
60 70 80
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
APPLICATION INFORMATION
LDCK UNCK
FULL
D9–D17
D0–D8
LDCK
FULL
D0–D8
LDCK
FULL
D0–D8
SN74ACT7808
CASEN
H
SN74ACT7808
CASEN
H
UNCK
EMPTY
OE
Q0–Q8
UNCK
EMPTY
OE
Q0–Q8
EMPTY
OE
Q9–Q17
Q0–Q8
Figure 6. Word-Width Expansion: 2048 × 18 Bits
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
APPLICATION INFORMATION
depth cascading (see Figure 7)
The SN74ACT7808 provides expansion logic necessary for cascading an unlimited number of the FIFOs in
depth. CASEN
chain; all others must have FL
expansion-in (XI) input of the next FIFO in the chain. The XO output of the last FIFO is tied to the XI input of
the first FIFO to complete the loop. Data buses are common to each FIFO in the chain. A composite EMPTY
and FULL signal must be generated to indicate boundary conditions.
RESET
must be low on all FIFOs used in depth expansion. FL must be tied low on the first FIFO in the
tied high. The expansion-out (XO) output of a FIFO must be tied to the
OE
D0–D8
LDCK
FULL
LL
CASEN
FL
SN74ACT7808
XI XO
RESET
D0–D8
LDCK
9 9 9
FULL EMPTY
9
OE
Q0–Q8
UNCK
FL
SN74ACT7808
XI XO
RESET
D0–D8 D0–D8
LDCK
FULL EMPTY
LH
CASEN
OE
Q0–Q8
9 9
UNCK
9 9
LH
CASEN
FL
SN74ACT7808
XI XO
RESET
LDCK
FULL EMPTY
OE
Q0–Q8
UNCK
Q0–Q8
UNCK
EMPTY
Figure 7. Depth Cascading to Form a 6K × 9 FIFO
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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