Texas Instruments SN74ACT7807-15PAG, SN74ACT7807-15PM, SN74ACT7807-20FN, SN74ACT7807-20PAG, SN74ACT7807-25FN Datasheet
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SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D
Read and Write Operations Synchronized
to Independent System Clocks
D
Input-Ready Flag Synchronized to Write
Clock
D
Output-Ready Flag Synchronized to Read
Clock
D
2048 Words by 9 Bits
D
Low-Power Advanced CMOS Technology
D
Programmable Almost-Full/Almost-Empty
Flag
D
Input-Ready, Output-Ready, and Half-Full
Flags
D
Cascadable in Word Width and/or Word
Depth
D
Fast Access Times of 12 ns With a 50-pF
Load
D
Data Rates up to 67 MHz
D
3-State Outputs
D
Package Options Include 44-Pin Plastic
Leaded Chip Carrier (FN) and 64-Pin Thin
Quad Flat (PAG, PM) Packages
description
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at
rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect
to the data inputs. Expansion is easily accomplished in both word width and word depth.
The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous
or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9,
WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising
edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the
output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer
regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the
output buffer.
The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET
must be asserted while at least four
WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the
IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset
upon power up.
The SN74ACT7807 is characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q1
V
CC
Q2
Q3
GND
Q4
V
CC
Q5
Q6
GND
Q7
39
38
37
36
35
34
33
32
31
30
29
18 19
7
8
9
10
11
12
13
14
15
16
17
D0
D1
D2
GND
D3
D4
D5
V
CC
D6
D7
D8
20 21 22 23
FN PACKAGE
(TOP VIEW)
NCOEGND
Q0
54321644
HF
AF/AE
GND
PEN
RESET
RDEN1
RDCLK
Q8
GND
WRTCLK
WRTEN1/DP9
WRTEN2
IR
OR
RDEN2
42 41 4043
24 25 26 27 28
V
CC
V
CC
V
CC
Q2
GND
GNDQ3Q4
Q5
Q6
GND
Q7
GND
NC
D1
D2
GND
GND
D4
D8
NC
NC
D0
D3
NC
D5
VCCV
CC
VCCV
CC
VCCV
CC
17 18 19 20 21 22 25 26 27 28 29 30 31 322423
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
D6
D7
Q1
PAG OR PM PACKAGE
(TOP VIEW)
NC
Q0
GND
GND
OE
NC
V
CC
V
CC
RESET
PEN
GND
GND
AF/AE
HF
V
CC
V
CC
NC
Q8
V
CC
V
CC
RDCLK
RDEN1
NC
RDEN2
OR
IR
WRTEN2
WRTEN1/DP9
WRTCLK
GND
GND
NC
NC – No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
WRTEN
&
RDEN
&
0
7
D0
8
D1
9
D2
11
D3
12
D4
13
D5
15
D6
16
D7
8
17
D8
Q0
40
0
Q1
39
Q2
37
Q3
36
Q4
34
IR
22
IN RDY
HF
5
HALF FULL
AF/AE
4
ALMOST FULL/EMPTY
OR
23
OUT RDY
Q5
32
Q6
31
Q7
29
Q8
28
8
Data
1
RESET
25
RDEN1
EN1
42
OE
PEN
RESET
1
19
WRTCLK
WRTCLK
20
WRTEN1/DP9
21
WRTEN2
2
26
RDCLK
RDCLK
PROGRAM ENABLE
24
RDEN2
Data
Φ
FIFO 2048 × 9
SN74ACT7807
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Q0 – Q8
OR
IR
AF/AE
HF
Register
2048 × 9 RAM
OE
D0–D8
RDCLK
RDEN1
RDEN2
WRTCLK
WRTEN1/DP9
WRTEN2
RESET
PEN
Synchronous
Read
Control
Synchronous
Write
Control
Reset
Logic
Write
Pointer
Status-
Flag
Logic
Location 1
Location 2
Location 2047
Location 2048
Read
Pointer
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O DESCRIPTION
AF/AE O
Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE or the default value of 256 can
be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains
X or fewer words or (2048 – Y) or more words. AF/AE is high after reset.
D0–D8 I Nine-bit data input port
HF O Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.
IR O
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low , the FIFO is full and
writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after
reset.
OE I
Output enable. When OE, RDEN1, RDEN2 and OR are high, data is read from the FIFO on a low-to-high transition
of RDCLK. When OE is low, reads are disabled and the data outputs are in the high-impedance state.
OR O
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty
and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low during reset and goes high
on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
PEN
I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D8 and DP9
is latched as an AF/AE offset value when PEN
is low and WRTCLK is high.
Q0–Q8 O
Nine-bit data output port. After the first valid write to empty memory , the first word is output on Q0–Q8 on the third
rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When OR is low, the last word
read from the FIFO is present on Q0–Q8.
RDCLK I
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high
transition of RDCLK reads data from memory when RDEN1, RDEN2, OE, and OR are high. OR is synchronous
to the low-to-high transition of RDCLK.
RDEN1
RDEN2
I
Read enables. When RDEN1, RDEN2, OE, and OR are high, data is read from the FIFO on the low-to-high
transition of RDCLK.
RESET
I
Reset. T o reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must
occur while RESET
is low. This sets HF, IR, and OR low and AF/AE high.
WRTCLK I
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high
transition of WRTCLK writes data to memory when WRTEN1/DP9, WR TEN2, and IR are high. IR is synchronous
to the low-to-high transition of WRTCLK.
WRTEN1/DP9 I
Write enable/data pin 9. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a
low-to-high transition of WRTCLK. When programming an AF/AE offset value, WRTEN1/DP9 is used as the
most-significant data bit.
WRTEN2 I
Write enable. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-to-high
transition of WRTCLK.
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the
offsets are not programmed, the default values of X = Y = 256 are used. The AF/AE flag is high when the FIFO
contains X or fewer words or (2048 – Y) or more words.
Program enable (PEN
) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTCLK is low . On the following low-to-high transition of WRTCLK, the binary value on D0–D8 and
WRTEN1/DP9 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN
low for another low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D8 and
WRTEN1/DP9 at the time of the second WRTCLK low-to-high transition. While the offsets are programmed,
data is not written to the FIFO memory , regardless of the state of the write enables (WRTEN1/DP9, WRTEN2).
A maximum value of 1023 can be programmed for either X or Y (see Figure 1). To use the default values of
X = Y = 256, PEN
must be held high.
X and Y
MSB
34
RESET
ООООООООООО
PEN
D0–D8
WRTCLK
WRTEN1/DP9
WRTEN2
IR
X and Y Y
YMSB
ПППППППППППППППППП
ПППППППППППППППППП
Word 1
Figure 1. Programming X and Y Separately
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
123412
Don’t Care
Don’t Care
Don’t Care
1234
Don’t Care
Don’t Care
Invalid
Don’t Care
Don’t Care
Don’t Care
Don’t Care
RESET
WRTCLK
PEN
WRTEN1/DP9
WRTEN2
D0–D8
RDCLK
RDEN1
OE
RDEN2
Q0–Q8
OR
AF/AE
HF
IR
Define the AF/AE Flag Using the
Default Value of X = Y = 256
1
0
1
0
Figure 2. Reset Cycle
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
123
Invalid
RESET
WRTCLK
PEN
WRTEN1/DP9
WRTEN2
D0–D8
RDCLK
RDEN1
OE
RDEN2
Q0–Q8
OR
AF/AE
HF
IR
1
0
1
0
1
0
W1 W2 W3 W4 W(X+2) W1025 W(2049–Y) W2049
1
0
1
0
W1
Figure 3. Write Cycle
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W1026
RESET
WRTCLK
PEN
WRTEN1/
DP9
WRTEN2
D0–D8
RDCLK
RDEN1
OE
RDEN2
Q0–Q8
OR
AF/AE
HF
IR
1
0
1
0
W2049
1
2
W1 W2 W3 W(Y+1) W(Y+2) W1025 W(2048–X) W(2049–X) W2048 W2049
1
0
Figure 4. Read Cycle
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 1): FN package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAG package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PM package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
’ACT7807-15 ’ACT7807-20 ’ACT7807-25 ’ACT7807-40
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 2 2 V
V
IL
Low-level input voltage 0.8 0.8 0.8 0.8 V
I
OH
High-level output current Q outputs, flags –8 –8 –8 –8 mA
p
Q outputs 16 16 16 16
IOLLow-level output current
Flags 8 8 8 8
mA
T
A
Operating free-air temperature 0 70 0 70 0 70 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
OH
VCC = 4.5 V, IOH = –8 mA 2.4 V
Flags VCC = 4.5 V, IOL = 8 mA 0.5
V
OL
Q outputs VCC = 4.5 V, IOL = 16 mA 0.5
V
I
I
VCC = 5.5 V, VI = VCC or 0 ±5 µA
I
OZ
VCC = 5.5 V, VO = VCC or 0 ±5 µA
I
CC
VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA
WRTEN1/DP9
p
p
2
∆I
CC
§
Other inputs
V
CC
=
5.5 V
,
One input at 3.4 V
,
Other inputs at V
CC
or GND
1
mA
C
i
VI = 0, f = 1 MHz 4 pF
C
o
VO = 0, f = 1 MHz 8 pF
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
This is the supply current for each input that is at one of the specified TTL voltage levels rather 0 V or VCC.
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 5)
’ACT7807-15 ’ACT7807-20 ’ACT7807-25 ’ACT7807-40
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 67 50 40 25 MHz
WRTCLK high or low 6 8 9 13
t
w
Pulse duration
RDCLK high or low
6 8 9 13
ns
PEN low 6 9 9 13
D0–D8 before WRTCLK↑ 4 5 5 5
WRTEN1, WRTEN2
before WRTCLK↑
4 5 5 5
t
su
Setup time
OE, RDEN1, RDEN2
before RDCLK↑
5 6 6 6.5
ns
Reset: RESET low before
first WRTCLK↑ and RDCLK↑
†
7 8 8 8
PEN before WRTCLK↑ 4 5 5 5
D0–D8 after WRTCLK↑ 0 0 0 0
WRTEN1, WRTEN2
after WRTCLK↑
0 0 0 0
t
h
Hold time
OE, RDEN1, RDEN2
after RDCLK↑
0 0 0 0
ns
h
Reset: RESET low after
fourth WRTCLK↑ and RDCLK↑
†
5 5 5 5
PEN high after WRTCLK↓ 0 0 0 0
PEN low after WRTCLK↑ 3 3 3 3
†
To permit the clock pulse to be utilized for reset purposes
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 5)
FROM TO
’ACT7807-15 ’ACT7807-20 ’ACT7807-25 ’ACT7807-40
PARAMETER
(INPUT) (OUTPUT)
MIN TYP‡MAX MIN MAX MIN MAX MIN MAX
UNIT
f
max
WRTCLK or
RDCLK
67 50 40 25 MHz
t
pd
RDCLK↑ Any Q 3 9 12 3 13 3 18 3 25 ns
t
pd
§
RDCLK↑ Any Q 8 ns
WRTCLK↑ IR 1 9 1 12 1 14 1 16
RDCLK↑ OR 1 9 2 12 2 14 2 16
t
pd
WRTCLK↑
2 16 2 20 2 25 2 30
ns
RDCLK↑
AF/AE
2 17 2 20 2 25 2 30
t
PLH
WRTCLK↑ HF 2 19 2 21 2 23 2 25 ns
t
PHL
RDCLK↑ HF 2 16 2 18 2 20 2 22 ns
t
PLH
RESET low
AF/AE 1 12 1 18 1 22 1 24 ns
t
PHL
RESET low
HF 2 12 2 18 2 22 2 24 ns
t
en
OE Any Q 2 10 2 13 2 15 2 18 ns
t
dis
OE Any Q 1 11 1 13 1 15 1 18 ns
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
This parameter is measured with CL = 30 pF (see Figure 6).
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 91 pF
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
t
h
t
PLH
t
PHL
Output
Control
Output
Waveform 1
S1 at 7 V
Output
Waveform 2
S1 at Open
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
1.5 V
3 V
0 V
1.5 V 1.5 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
Input
3 V
3 V
≈ 3.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
S1
500 Ω
LOAD CIRCUIT
500 Ω
7 V
From Output
Under Test
Test
Point
NOTE A: CL includes probe and jig capacitance.
CL = 50 pF
(see Note A)
t
su
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
Open
Closed
Open
Closed
Open
Open
PARAMETER S1
t
en
t
dis
t
pd
Figure 5. Load Circuit and Voltage Waveforms
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
0 50 100 150 200 250 300
CL – Load Capacitance – pF
VCC = 5 V
RL = 500 Ω
TA = 25°C
pd
t – Propagation Delay Time – ns
typ + 8
typ + 6
typ + 4
typ + 2
typ
typ – 2
Figure 7
– Active I
CC(f)
I
CC
– mA
100
80
40
20
0
60
0102030405060
120
70
ACTIVE I
CC
vs
FREQUENCY
f – Frequency – MHz
140
160
180
200
TA = 25°C
VCC = 5 V
VCC = 4.5 V
VCC = 5.5 V
5
4
2
1
0
3
0102030405060
6
f – Frequency – MHz
70
Slope = 0.07
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
TA = 25°
– Idle I
CC(I)
I
CC
– mA
Figure 8. SN74ACT7807 Idle ICC With WRTCLK Switching,
Other Inputs at 0 or V
CC
– 0.2 V and Outputs Disconnected
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
WRTCLK
WRTEN1/DP9WRTEN1
WRTEN2WRTEN2
IRIR
WRTCLK
D0–D8
RDCLK
OR
RDEN1
RDEN2
OE
RDCLK
WRTEN1/DP9
WRTEN2
IR
RDEN1RDEN1
OROR
OEOE
Q0–Q8
5 V
RDEN2RDEN2
CLOCK
D0–D8 Q0–Q8D0–D8 Q0–Q8
SN74ACT7807
SN74ACT7807
WRTCLK
RDCLK
Figure 9. Word-Depth Expansion: 4096 × 9 Bits
WRTEN1/DP9
WRTEN2
IR
OE
RDEN1
RDEN2
OR
WRTEN1/DP9
WRTEN2
IR
D0–D8
OE
RDEN1
RDEN2
OR
WRTCLK
WRTEN
D9–D17
IR
D0–D8
RDCLK
RDEN
Q9–Q17
OR
OE
D0–D8
Q0–Q8
Q0–Q8
Q0–Q8
SN74ACT7807
SN74ACT7807
WRTCLK
RDCLK
WRTCLK
RDCLK
Figure 10. Word-Width Expansion: 2048 × 18 Bits
IMPORTANT NOTICE
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