Texas Instruments SN74ACT7807-15PAG, SN74ACT7807-15PM, SN74ACT7807-20FN, SN74ACT7807-20PAG, SN74ACT7807-25FN Datasheet
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SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D
Read and Write Operations Synchronized
to Independent System Clocks
D
Input-Ready Flag Synchronized to Write
Clock
D
Output-Ready Flag Synchronized to Read
Clock
D
2048 Words by 9 Bits
D
Low-Power Advanced CMOS Technology
D
Programmable Almost-Full/Almost-Empty
Flag
D
Input-Ready, Output-Ready, and Half-Full
Flags
D
Cascadable in Word Width and/or Word
Depth
D
Fast Access Times of 12 ns With a 50-pF
Load
D
Data Rates up to 67 MHz
D
3-State Outputs
D
Package Options Include 44-Pin Plastic
Leaded Chip Carrier (FN) and 64-Pin Thin
Quad Flat (PAG, PM) Packages
description
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at
rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect
to the data inputs. Expansion is easily accomplished in both word width and word depth.
The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous
or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9,
WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising
edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the
output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer
regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the
output buffer.
The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET
must be asserted while at least four
WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the
IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset
upon power up.
The SN74ACT7807 is characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q1
V
CC
Q2
Q3
GND
Q4
V
CC
Q5
Q6
GND
Q7
39
38
37
36
35
34
33
32
31
30
29
18 19
7
8
9
10
11
12
13
14
15
16
17
D0
D1
D2
GND
D3
D4
D5
V
CC
D6
D7
D8
20 21 22 23
FN PACKAGE
(TOP VIEW)
NCOEGND
Q0
54321644
HF
AF/AE
GND
PEN
RESET
RDEN1
RDCLK
Q8
GND
WRTCLK
WRTEN1/DP9
WRTEN2
IR
OR
RDEN2
42 41 4043
24 25 26 27 28
V
CC
V
CC
V
CC
Q2
GND
GNDQ3Q4
Q5
Q6
GND
Q7
GND
NC
D1
D2
GND
GND
D4
D8
NC
NC
D0
D3
NC
D5
VCCV
CC
VCCV
CC
VCCV
CC
17 18 19 20 21 22 25 26 27 28 29 30 31 322423
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
D6
D7
Q1
PAG OR PM PACKAGE
(TOP VIEW)
NC
Q0
GND
GND
OE
NC
V
CC
V
CC
RESET
PEN
GND
GND
AF/AE
HF
V
CC
V
CC
NC
Q8
V
CC
V
CC
RDCLK
RDEN1
NC
RDEN2
OR
IR
WRTEN2
WRTEN1/DP9
WRTCLK
GND
GND
NC
NC – No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
WRTEN
&
RDEN
&
0
7
D0
8
D1
9
D2
11
D3
12
D4
13
D5
15
D6
16
D7
8
17
D8
Q0
40
0
Q1
39
Q2
37
Q3
36
Q4
34
IR
22
IN RDY
HF
5
HALF FULL
AF/AE
4
ALMOST FULL/EMPTY
OR
23
OUT RDY
Q5
32
Q6
31
Q7
29
Q8
28
8
Data
1
RESET
25
RDEN1
EN1
42
OE
PEN
RESET
1
19
WRTCLK
WRTCLK
20
WRTEN1/DP9
21
WRTEN2
2
26
RDCLK
RDCLK
PROGRAM ENABLE
24
RDEN2
Data
Φ
FIFO 2048 × 9
SN74ACT7807
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Q0 – Q8
OR
IR
AF/AE
HF
Register
2048 × 9 RAM
OE
D0–D8
RDCLK
RDEN1
RDEN2
WRTCLK
WRTEN1/DP9
WRTEN2
RESET
PEN
Synchronous
Read
Control
Synchronous
Write
Control
Reset
Logic
Write
Pointer
Status-
Flag
Logic
Location 1
Location 2
Location 2047
Location 2048
Read
Pointer
SN74ACT7807
2048 × 9
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS200D – JANUARY 1991 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O DESCRIPTION
AF/AE O
Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE or the default value of 256 can
be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains
X or fewer words or (2048 – Y) or more words. AF/AE is high after reset.
D0–D8 I Nine-bit data input port
HF O Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.
IR O
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low , the FIFO is full and
writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after
reset.
OE I
Output enable. When OE, RDEN1, RDEN2 and OR are high, data is read from the FIFO on a low-to-high transition
of RDCLK. When OE is low, reads are disabled and the data outputs are in the high-impedance state.
OR O
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty
and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low during reset and goes high
on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
PEN
I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D8 and DP9
is latched as an AF/AE offset value when PEN
is low and WRTCLK is high.
Q0–Q8 O
Nine-bit data output port. After the first valid write to empty memory , the first word is output on Q0–Q8 on the third
rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When OR is low, the last word
read from the FIFO is present on Q0–Q8.
RDCLK I
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high
transition of RDCLK reads data from memory when RDEN1, RDEN2, OE, and OR are high. OR is synchronous
to the low-to-high transition of RDCLK.
RDEN1
RDEN2
I
Read enables. When RDEN1, RDEN2, OE, and OR are high, data is read from the FIFO on the low-to-high
transition of RDCLK.
RESET
I
Reset. T o reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must
occur while RESET
is low. This sets HF, IR, and OR low and AF/AE high.
WRTCLK I
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high
transition of WRTCLK writes data to memory when WRTEN1/DP9, WR TEN2, and IR are high. IR is synchronous
to the low-to-high transition of WRTCLK.
WRTEN1/DP9 I
Write enable/data pin 9. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a
low-to-high transition of WRTCLK. When programming an AF/AE offset value, WRTEN1/DP9 is used as the
most-significant data bit.
WRTEN2 I
Write enable. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-to-high
transition of WRTCLK.
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