Texas Instruments SN74AC573DBLE, SN74AC573DBR, SN74AC573DW, SN74AC573DWR, SN74AC573N Datasheet
...
SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
D
3-State Outputs Drive Bus Lines Directly
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D Inputs.
A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the high-impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
) input can be used
SN54AC573 ...J OR W PACKAGE
SN74AC573 . . . DB, DW, N, OR PW PACKAGE
SN54AC573 . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
8D
9
GND
10
(TOP VIEW)
2D1DOE
3 2 1 20 19
4
5
6
7
8
910111213
8D
LE
20
19
18
17
16
15
14
13
12
11
V
8Q
CC
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1Q
18
17
16
15
14
7Q
CC
2Q
3Q
4Q
5Q
6Q
GND
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC573 is characterized for operation over the full military temperature range of –55_C to 125_C.
The SN74AC573 is characterized for operation from –40_C to 85_C.
FUNCTION TABLE
(each latch)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
1
SN54AC573, SN74AC573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS542B - OCTOBER 1995 – REVISED NOVEMBER 1996
logic symbol
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
logic diagram (positive logic)
1
OE
11
LE
C1
1D
2
To Seven Other Channels
1D
19
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to + 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to V
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or V
Output clamp current, IOK (VO < 0 or V
Continuous output current, I
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through, V
Maximum power dissipation at T
> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
= 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . . . .
A
DW package 1.6 W. . . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1Q
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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