Texas Instruments SN74AC533DBLE, SN74AC533DBR, SN74AC533DW, SN74AC533DWR, SN74AC533N Datasheet
...
SN54AC533, SN74AC533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS555A – NOVEMBER 1995 – REVISED MA Y 1996
D
3-State Inverting Outputs Drive Bus Lines
Directly
D
Full Parallel Access for Loading
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AC533 are octal transparent D-type latches
with 3-state outputs. When the latch-enable (LE)
input is high, the Q outputs follow the
complements of the data (D) inputs. When LE is
taken low, the Q
logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or a highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
outputs are latched at the inverse
SN54AC533 ...J OR W PACKAGE
SN74AC533 . . . DB, DW, N, OR PW P ACKAGE
SN54AC533 ...FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
(TOP VIEW)
1D1QOE
3212019
4
5
6
7
8
9
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
10 11 12 13
LE
4Q
CC
5Q
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
8Q
18
17
16
15
14
5D
CC
8D
7D
7Q
6Q
6D
GND
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC533 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC533 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
INPUTS
OE LE D
L H H L
L HL H
L LX Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AC533, SN74AC533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS555A – NOVEMBER 1995 – REVISED MA Y 1996
1
11
3
4
7
8
13
14
17
18
†
EN
C1
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
1D
1
logic diagram (positive logic)
1
OE
11
LE
C1
1D
3
To Seven Other Channels
1D
2
1Q
logic symbol
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DW package 1.6 W. . . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
I
mA
V
V
I
mA
SN54AC533, SN74AC533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS555A – NOVEMBER 1995 – REVISED MA Y 1996
recommended operating conditions (see Note 3)
SN54AC533 SN74AC533
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
High-level input voltage
Low-level input voltage
Input voltage 0 V
Output voltage 0 V
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
VCC = 4.5 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VCC = 4.5 V
VCC = 5.5 V 1.65 1.65
VCC = 3 V –12 –12
VCC = 4.5 V
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
VCC = 4.5 V
VCC = 5.5 V 24 24
3.15 3.15
1.35 1.35
CC
CC
–24 –24
24 24
0 V
0 V
CC
CC
V
V
V
V
mA
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54AC533 SN74AC533
MIN TYP MAX MIN MAX MIN MAX
I
I
I
C
OH
OL
OZ
I
CC
i
CC
3 V 2.9 2.9 2.9
IOH = –50 µA
IOH = –12 mA 3 V 2.56 2.4 2.46
= –24
OH
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.5 0.44
= 24
OL
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
VI = VCC or GND 5 V 4.5 pF
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AC533, SN74AC533
UNIT
UNIT
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS555A – NOVEMBER 1995 – REVISED MA Y 1996
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC533 SN74AC533
MIN MAX MIN MAX MIN MAX
t
Pulse duration, LE high 6 8 6.5 ns
w
t
Setup time, data before LE↓ 5.5 7.5 6 ns
su
t
Hold time, data after LE↓ 1.5 2.5 1 ns
h
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC533 SN74AC533
MIN MAX MIN MAX MIN MAX
t
Pulse duration, LE high 4.5 6.5 5 ns
w
t
Setup time, data before LE↓ 4 6 4.5 ns
su
t
Hold time, data after LE↓ 1.5 2.5 1 ns
h
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C SN54AC533 SN74AC533
MIN MAX MIN MAX MIN MAX
2 14 1 17.5 1.5 16
2 13 1 16 1.5 14.5
2 14.5 1 18 1.5 16.5
2 13 1 16 1.5 14.5
2 12.5 1 15.5 1.5 14
2 12.5 1 15.5 1.5 14
2 13 1 16 1.5 14.5
2 13 1 16 1.5 14.5
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C SN54AC533 SN74AC533
MIN MAX MIN MAX MIN MAX
2 10 1 12.5 1.5 11
2 9.5 1 12 1.5 10.5
2 10.5 1 13 1.5 11.5
2 10 1 13 1.5 11
2 9.5 1 12 1.5 10.5
2 9.5 1 12 1.5 10.5
2 10 1 12.5 1.5 11
2 10 1 12.5 1.5 11
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
Input
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
LOAD CIRCUIT
t
w
50% V
CC
VOLTAGE WAVEFORMS
S1
50% V
CC
2 × V
V
CC
0 V
CC
Open
SN54AC533, SN74AC533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS555A – NOVEMBER 1995 – REVISED MA Y 1996
TEST S1
Timing Input
Data Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
50% V
VOLTAGE WAVEFORMS
50% V
CC
Open
2 × V
Open
CC
CC
t
h
50% V
CC
V
0 V
V
0 V
CC
CC
50% V
Input
t
PLH
In-Phase
Output
t
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
PHL
VOLTAGE WAVEFORMS
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
CC
50% V
50% V
50% V
CC
CC
Figure 1. Load Circuit and Voltage Waveforms
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
CC
t
PZL
t
50% V
50% V
PZH
50% V
VOLTAGE WAVEFORMS
CC
t
PLZ
t
PHZ
CC
CC
50% V
CC
VOL + 0.3 V
VOH – 0.3 V
V
0 V
[
V
V
[
CC
V
OL
OH
0 V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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