Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AC245 octal bus transceivers are designed
for asynchronous two-way communication
between data buses. The control-function
implementation minimizes external timing
requirements.
When the output-enable (OE
passes noninverted data from the A bus to the B
bus or from the B bus to the A bus, depending on
the logic level at the direction control (DIR) input.
A high on OE disables the device so that the buses
are effectively isolated.
The SN54AC245 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AC245 is characterized for
operation from –40°C to 85°C.
) is low, the device
SN54AC245 ...J OR W PACKAGE
SN74AC245 . . . DB, DW, N, OR PW PACKAGE
SN54AC245 . . . FK PACKAGE
A3
A4
A5
A6
A7
(TOP VIEW)
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
(TOP VIEW)
A2A1DIR
3 2 1 20 19
4
5
6
7
8
9 10 11 12 13
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
18
17
16
15
14
V
OE
B1
B2
B3
B4
B5
B6
B7
B8
CC
B1
B2
B3
B4
B5
B7
B8
B6OE
A8
GND
FUNCTION TABLE
INPUTS
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIR
L
L
H
L
H
X
B data to A bus
A data to B bus
Isolation
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
SN54AC245, SN74AC245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS461D – FEBRUARY 1995 – REVISED DECEMBER 1996
logic symbol
19
OE
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
G3
3EN1[BA]
3EN2[AB]
1
18
2
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
logic diagram (positive logic)
1
DIR
2
A1
To Seven Other Channels
19
18
OE
B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, VI (see Note 1)–0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1)–0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
switching characteristics over recommended operating free-air temperature range,
= 5 V " 5 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°CSN54AC245SN74AC245
MINTYPMAXMINMAXMINMAX
1.53.56.518.517
1.53.5617.517
1.558.511019
1.55.59110.519.5
1.55.59110.5110
1.55.59110.5110
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROMTO
(INPUT)(OUTPUT)
operating characteristics, V
PARAMETERTEST CONDITIONSTYPUNIT
Cpd Power dissipation capacitance per transceiverCL = 50 pF, f = 1 MHz45pF
= 5 V, T
CC
= 25°C
A
PARAMETER MEASUREMENT INFORMATION
2 × V
From Output
Under Test
CL = 50 pF
(see Note A)
Input
In-Phase
Output
Out-of-Phase
Output
50%50%
t
PLH
t
PHL
VOLTAGE WAVEFORMS
500 Ω
500 Ω
LOAD CIRCUIT
50% V
CC
50% V
CC
t
PHL
50% V
t
PLH
50% V
V
0 V
V
CC
V
V
CC
V
S1
CC
OH
OL
OH
OL
CC
Open
S1 at 2 × V
Output
Control
(low-level
enabling)
Output
Waveform 1
(see Note B)
Waveform 2
S1 at Open
(see Note B)
CC
Output
t
PZL
t
PZH
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
50% V
t
PLZ
50% V
t
PHZ
50% V
VOLTAGE WAVEFORMS
CC
Open
2 × V
Open
50% V
CC
CC
CC
CC
VOL + 0.3 V
VOH – 0.3 V
V
0 V
[
V
V
[
CC
V
OL
OH
0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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