Texas Instruments SN74ABT541BDBLE, SN74ABT541BDBR, SN74ABT541BDW, SN74ABT541BDWR, SN74ABT541BN Datasheet

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SN54ABT541, SN74ABT541B
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
D
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
D
T ypical V at V
D
High-Impedance State During Power Up
= 5 V, TA = 25°C
CC
(Output Ground Bounce) < 1 V
OLP
and Power Down
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (N) and Ceramic (J) DIPs
description
The SN54ABT541 and SN74ABT541B octal buffers and line drivers are ideal for driving bus lines or buffering memory address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 outputs are in the high-impedance state.
or OE2) input is high, all eight
SN54ABT541 ...J OR W PACKAGE
SN74ABT541B . . . DB, DW, N, OR PW PACKAGE
SN54ABT541 . . . FK PACKAGE
A3 A4 A5 A6 A7
(TOP VIEW)
OE1
A1 A2 A3 A4 A5 A6 A7 A8
GND
(TOP VIEW)
3 2 1 20 19
4 5 6 7 8
910111213
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
A2A1OE1
A8
V
Y8
GND
CC
Y7
V
CC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
18 17 16 15 14
Y6 OE2
Y1 Y2 Y3 Y4 Y5
When V However, to ensure the high-impedance state above 2.1 V, OE
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT541B is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
OE1 OE2 A
L L L L
L LH H HXX Z XHX Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
INPUTS
OUTPUT
Y
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
SN54ABT541, SN74ABT541B
UNIT
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
1
19
2 3 4 5 6 7 8 9
&
EN
1
18 17 16 15 14 13 12 11
logic symbol
OE1
OE2
A1 A2 A3 A4 A5 A6 A7 A8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE1 OE2
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
1 19
218
A1
Y1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high or power-off state, V Current into any output in the low state, I
Input clamp current, I Output clamp current, I Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABT541 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
SN74ABT541B 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT541 SN74ABT541B
MIN MAX MIN MAX
V V V I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
2
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
High-level output current –24 –32 mA Low-level output current 48 64 mA Operating free-air temperature –55 125 –40 85 ° C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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