Texas Instruments SN74ABT162827ADGGR, SN74ABT162827ADGVR, SN74ABT162827ADL, SN74ABT162827ADLR Datasheet
SN54ABT162827A, SN74ABT162827A
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS248E – JULY 1993 – REVISED MAY 1997
D
Members of the Texas Instruments
Widebus
D
Output Ports Have Equivalent 25-Ω Series
Family
Resistors, So No External Resistors Are
Required
D
High-Impedance State During Power Up
and Power Down
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Typical V
< 1 V at V
D
High-Impedance State During Power Up
(Output Ground Bounce)
OLP
= 5 V, TA = 25°C
CC
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ABT162827A are noninverting 20-bit buffers
composed of two 10-bit buffers with separate
output-enable signals. For either 10-bit buffer , the
two output-enable (1OE1
2OE2) inputs must both be low for the
corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
10-bit buffer are in the high-impedance state.
and 1OE2, or 2OE1 and
SN54ABT162827A ...WD PACKAGE
SN74ABT162827A . . . DGG, DGV, OR DL PACKAGE
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
V
CC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
2A10
2OE2
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to
reduce overshoot and undershoot.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT162827A is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABT162827A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT162827A, SN74ABT162827A
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS248E – JULY 1993 – REVISED MAY 1997
OE1 OE2 A
FUNCTION TABLE
(each 10-bit buffer)
INPUTS
L L L L
L LH H
H XX Z
X H X Z
OUTPUT
Y
logic symbol
†
1OE1
1OE2
2OE1
2OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
&
&
11
12
EN1
EN2
10
12
13
14
15
16
17
19
20
21
23
24
26
27
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
1Y5
9
1Y6
1Y7
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
2Y9
2Y10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
logic diagram (positive logic)
SN54ABT162827A, SN74ABT162827A
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS248E – JULY 1993 – REVISED MAY 1997
1OE1
1OE2
1A1
1
56
55
2
1Y1
To Nine Other Channels To Nine Other Channels
2OE1
2OE2
2A1
28
29
42
15
2Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 3)
SN54ABT162827A SN74ABT162827A
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆V Input transition rise or fall rate 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –12 –12 mA
Low-level output current 12 12 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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