SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JUL Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
D
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
D
3-State Outputs Drive Bus Lines or
Buffer-Memory Address Registers
D
ESD Protection Exceeds 2000 V
Per MIL-STD-883 Method 3015
D
High-Impedance State During Power Up
and Power Down
D
Package Options Include Plastic
Small-Outline (D) and Standard Plastic
300-mil DIPs (N)
description
The SN64BCT126A bus buffer features independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
The SN64BCT126A is characterized for operation from – 40°C to 85°C and 0°C to 70°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
Y
H H H
H LL
LXZ
logic symbol
†
EN
1
1OE
2
1A
1Y
3
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
2Y
6
3Y
8
4Y
11
1
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
4
56
2A 2Y
2OE
1
23
1A
1Y
1OE
10
98
3A
3Y
3OE
13
12 11
4A 4Y
4OE
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JUL Y 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
–0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative voltage rating may be exceeded if the input clamp current rating is observed.
2. The package thermal impedance is calculated in acordane with JESD 51, except for through-hole packages, which use a trace length
of zero.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –15 mA
I
OL
Low-level output current 64 mA
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JUL Y 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
IOH = –3 mA 2.4 3.3
V
OH
V
CC
=
4.5 V
IOH = –15 mA 2 3.1
V
V
OL
VCC = 4.5 V, IOH = 64 mA 0.42 0.55 V
I
OZH
VCC = 5.5 V, VO = 2.7 V 50 µA
I
OZL
VCC = 5.5 V, VO = 0.5 V –50 µA
VCC = 0 to 1.3 V (power up)
"
50
I
OZ
VCC = 1.3 V to 0 (power down)
V
O
= 2.7 V or 0.5 V,
OE at 2 V
"
50
µ
A
I
I
VCC = 0, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 25 µA
I
IL
VCC = 5.5 V, VI = 0.5 V –20 µA
I
OS
‡
VCC = 5.5 V, VO = 0 –100 –225 mA
I
CCL
VCC = 5.5 V 35 51 mA
I
CCH
VCC = 5.5 V 21 33 mA
I
CCZ
VCC = 5.5 V 5 10 mA
C
i
VCC = 5 V, VI = 2.5 V or 0.5 V 4 pF
C
o
VCC = 5 V, VO = 2.5 V or 0.5 V 9 pF
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
switching characteristics (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
CL = 50 pF,
R1 = 500 Ω,
VCC = 4.5 V to 5.5 V
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω
UNIT
PARAMETER
(INPUT) (OUTPUT)
R2
=
500 Ω
,
TA = 25°C
TA = –40°C
to 85°C
TA = 0°C
to 70°C
UNIT
MIN TYP MAX MIN MAX MIN MAX
t
PLH
1.5 3.6 4.9 1.5 6.3 1.5 6.3
t
PHL
A
Y
2.7 5.3 6.9 2.7 7.7 2.7 7.4
ns
t
PZH
2.6 4.8 6.4 2.6 7.9 2.6 7.9
t
PZL
OE
Y
3.7 6.4 8.3 3.7 10.5 3.7 10
ns
t
PHZ
3.2 6.6 8.2 3.2 10 3.2 10
t
PLZ
OE
Y
3.4 6.5 8 3.4 12.3 3.4 10.7
ns
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JUL Y 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
R1
C
L
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
R1
S1
7 V (t
PZL
, t
PLZ
, O.C.)
Open
(all others)
From Output
Under Test
Test
Point
R2
C
L
(see Note A)
RL = R1 = R2
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
(see Note B)
Data Input
(see Note B)
1.5 V
1.5 V
3 V
3 V
0 V
0 V
High-Level
Pulse
(see Note B)
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
t
PHL
t
PLH
t
PLH
t
PHL
Input
(see Note B)
Out-of-Phase
Output
(see Note D)
1.5 V 1.5 V
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
t
PHZ
t
PLZ
0.3 V
t
PZL
t
PZH
1.5 V1.5 V
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level enable)
Waveform 1
(see Notes C and D)
Waveform 2
(see Notes C and D)
0 V
V
OH
V
OL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 1. Load Circuits and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...