Texas Instruments SN64BCT126ADR, SN64BCT126AN, SN64BCT126AD Datasheet
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JUL Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
D
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
D
3-State Outputs Drive Bus Lines or
Buffer-Memory Address Registers
D
ESD Protection Exceeds 2000 V
Per MIL-STD-883 Method 3015
D
High-Impedance State During Power Up
and Power Down
D
Package Options Include Plastic
Small-Outline (D) and Standard Plastic
300-mil DIPs (N)
description
The SN64BCT126A bus buffer features independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
The SN64BCT126A is characterized for operation from – 40°C to 85°C and 0°C to 70°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
Y
H H H
H LL
LXZ
logic symbol
†
EN
1
1OE
2
1A
1Y
3
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
2Y
6
3Y
8
4Y
11
1
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
4
56
2A 2Y
2OE
1
23
1A
1Y
1OE
10
98
3A
3Y
3OE
13
12 11
4A 4Y
4OE
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JUL Y 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
–0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative voltage rating may be exceeded if the input clamp current rating is observed.
2. The package thermal impedance is calculated in acordane with JESD 51, except for through-hole packages, which use a trace length
of zero.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –15 mA
I
OL
Low-level output current 64 mA
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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