SN54ALS251, SN74ALS251
1-OF-8 DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SDAS215A – APRIL 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State Version of the ′ALS151
• 3-State Outputs Interface Directly With
System Bus
• Perform Parallel-to-Serial Conversion
• Complementary Outputs Provide True and
Inverted Data
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These data selectors/multiplexers contain full
binary decoding to select one-of-eight data
sources and feature controlled complementary
3-state outputs.
The 3-state outputs can interface with and drive
data lines of bus-organized systems. With all but
one of the common outputs disabled (at the
high-impedance state), the low impedance of the
signal-enabled output drives the bus line to a high
or low logic level. Both outputs are controlled by
the output-enable (OE
) input. The outputs are
disabled when OE
is high.
The SN54ALS251 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS251 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
Y W
X X X H Z Z
L LLLD0 D0
L LHLD1 D1
L HLLD2 D2
L HHLD3 D3
H LLLD4 D4
H LHLD5 D5
H HLLD6 D6
H H H L D7 D7
D0, D1, . . . D7 = the level of the respective D input
SN54ALS251 ...J PACKAGE
SN74ALS251 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
D5
D6
NC
D7
A
D1
D0
NC
Y
W
SN54ALS251 . . . FK PACKAGE
(TOP VIEW)
D2D3NC
C
B
D4
OE
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3
D2
D1
D0
Y
W
OE
GND
V
CC
D4
D5
D6
D7
A
B
C
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS251, SN74ALS251
1-OF-8 DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SDAS215A – APRIL 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
MUX
EN
7
0
11
A
10
B
2
9
C
0
4
D0
1
3
D1
2
2
D2
3
1
D3
4
15
D4
5
14
D5
6
13
D6
7
12
D7
0
7
G
W
6
Y
5
OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
7
4
3
2
1
15
14
13
12
11
10
9
5
6
OE
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
Y
W
Data
Inputs
Data
Select
(binary)
Pin numbers shown are for the D, J, and N packages.