Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These octal buffers and line drivers are designed
specifically to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. With the ′ALS240A, ′ALS241C,
′AS240A, and ′AS241A, these devices provide the
choice of selected combinations of inverting
outputs, symmetrical active-low output-enable
(OE
) inputs, and complementary OE and OE
inputs.
The -1 version of SN74ALS244C is identical to the
standard version, except that the recommended
maximum I
no -1 version of the SN54ALS244C.
The SN54ALS244C and SN54AS244A are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS244C and SN74AS244A are
characterized for operation from 0°C to 70°C.
for the -1 version is 48 mA. There is
OL
SN54ALS244C, SN54AS244A ...J PACKAGE
SN74ALS244C, SN74AS244A . . . DW OR N PACKAGE
SN54ALS244C, SN54AS244A . . . FK PACKAGE
1A2
2Y3
1A3
2Y2
1A4
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
9
2Y1
GND
10
(TOP VIEW)
2Y4
3 2 1 20 19
4
5
6
7
8
910111213
2Y1
1A1
GND
20
19
18
17
16
15
14
13
12
11
V
1OE
2A1
CC
1Y4
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
18
17
16
15
14
2A22OE
1Y1
2A4
1Y2
2A3
1Y3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each buffer)
INPUTS
OEA
LHH
LLL
HXZ
OUTPUT
Y
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS142C – JULY 1987 – REVISED AUGUST 1995
1
2
4
6
8
19
11
13
15
17
†
EN
EN
logic symbol
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
18
16
14
12
logic diagram (positive logic)
1
1OE
2
1Y1
1Y2
1Y3
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
1A1
1A2
1A3
1A4
2OE
2A1
2A2
4
6
8
19
11
13
18
16
14
12
1Y1
1Y2
1Y3
1Y4
9
2Y1
7
2Y2
2A3
2A4
15
17
5
2Y3
3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PLZ
FROM
(INPUT)
TO
(OUTPUT)
R1 = 500 Ω
R2 = 500 Ω,
TA = MIN to MAX
SN54AS244A SN74AS244A
MINMAXMINMAX
2926.2
1716.2
11019
2827.5
16.516
110.519
,
§
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS142C – JULY 1987 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
R
L
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
C
(see Note A)
Test
Point
L
From Output
Under Test
(see Note A)
7 V
RL = R1 = R2
S1
R1
C
L
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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