Texas Instruments SN54ALS139J, SN74ALS139D, SN74ALS139DR, SN74ALS139N, SN74ALS139N3 Datasheet
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SN54ALS139, SN74ALS139
OUTPUTS
ENABLE
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
• Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
• Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ′ALS139 are dual 2-line to 4-line
decoders/demultiplexers designed for use in
high-performance memory-decoding or datarouting applications requiring very short
propagation delay times. In high-performance
memory systems, these devices can minimize the
effects of system decoding. When employed with
high-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the
enable time of the memory are usually less than
the typical access time of the memory . Therefore,
the effective system delay introduced by the
Schottky-clamped system decoder is negligible.
SN54ALS139 ...J PACKAGE
SN74ALS139 ...D OR N PACKAGE
SN54ALS139 . . . FK PACKAGE
1B
1Y0
NC
1Y1
1Y2
(TOP VIEW)
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
GND
(TOP VIEW)
3 2 1 20 19
4
5
6
7
8
910111213
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
1A1GNC
V
CC
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
9
CC
2G
V
2A
18
17
2B
16
NC
15
2Y0
14
2Y1
The ′ALS139 comprise two individual 2-line to
4-line decoders in a single package. The
active-low enable (G
) input can be used as a data
NC – No internal connection
1Y3
GND
NC
2Y3
2Y2
line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its
driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and
simplify system design.
The SN54ALS139 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS139 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
ENABLE
G
H X X H H H H
L L LLHHH
L LHHLHH
L HLHHLH
L HHHHHL
SELECT
B A Y0 Y1 Y2 Y3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
X/Y
†
4
12
11
10
1Y0
5
1Y1
6
1Y2
7
1Y3
2Y0
2Y1
2Y2
9
2Y3
0
1
2
3
1A
1B
1G
2A
2B
2G
2
3
1
14
13
15
logic symbols (alternatives)
2
1A
3
1B
1
1G
14
2A
13
2B
15
2G
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
1
EN
logic diagram (positive logic)
1A
1B
1
2
3
15
Enable 1G
Select
Inputs
Enable 2G
DMUX
0
G
1
7
12
11
0
0
3
1
2
3
4
1Y0
5
1Y1
6
1Y2
1Y3
2Y0
2Y1
Data
Outputs
12
11
10
4
1Y0
5
1Y1
6
1Y2
7
1Y3
2Y0
2Y1
2Y2
9
2Y3
14
Select
Inputs
Pin numbers shown are for the D, J, and N packages.
2
2A
2B
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
2Y2
9
2Y3
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