Texas Instruments SN54ALS1245AJ, SN74ALS1245ADW, SN74ALS1245ADWR, SN74ALS1245AN, SNJ54ALS1245AFK Datasheet

SN54ALS1245A, SN74ALS1245A

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SDAS245A – DECEMBER 1982 – REVISED JANUARY 1995

Copyright  1995, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Bidirectional Bus Transceivers in

High-Density 20-Pin Packages

• Low-Power Versions of ′ALS245 Series

• ′ALS1245 Series Is Identical to ′ALS1645

Series

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs

description

These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. These devices transmit data from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction­control (DIR) input. The output-enable (OE

) input
can be used to disable the device so the buses are
effectively isolated.

The SN54ALS1245A is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74ALS1245A is
characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OE DIR

OPERATION

L L B data to A bus
L H A data to B bus
H X Isolation

3212019

910111213

4
5
6
7
8

18
17
16
15
14

B1
B2
B3
B4
B5

A3
A4
A5
A6
A7

A2A1DIR

B7

B6

OE

A8

GND

B8

V

CC

SN54ALS1245A . . . FK PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

DIR

A1
A2
A3
A4
A5
A6
A7
A8

GND

V

CC

OE
B1
B2
B3
B4
B5
B6
B7
B8

SN54ALS1245A ...J PACKAGE

SN74ALS1245A . . . DW OR N PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54ALS1245A, SN74ALS1245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SDAS245A – DECEMBER 1982 – REVISED JANUAR Y 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

logic diagram (positive logic)

B2

17

B3

16

B4

15

A5

6

A6

7

A7

8

A8

9

A2

3

A3

4

A4

5

OE

A1

2

G3

19

3EN2 [AB]

B5

14

B6

13

B7

12

B8

11

B1

18

3EN1 [BA]

1

DIR

DIR

A1 B1

19

218

To Seven Other Transceivers

1

2

1

OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

: All inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: SN54ALS1245A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALS1245A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS1245A SN74ALS1245A

MIN NOM MAX MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.7 0.8 V

I

OH

High-level output current –12 –15 mA

I

OL

Low-level output current 8 16 mA

T

A

Operating free-air temperature –55 125 0 70 °C

SN54ALS1245A, SN74ALS1245A

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SDAS245A – DECEMBER 1982 – REVISED JANUAR Y 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54ALS1245A SN74ALS1245A

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2

IOH = –3 mA 2.4 3.2 2.4 3.2

V

OH

VCC = 4.5 V

IOH = –12 mA 2

V

IOH = –15 mA 2
IOL= 8 mA 0.25 0.4 0.25 0.4

VOLV

CC

=

4.5 V

IOL = 16 mA

0.35 0.5

V

Control inputs

VI = 7 V 0.1 0.1

I

I

A or B ports

V

CC

= 5.5

V

VI = 5.5 V 0.1 0.1

mA

Control inputs

20 20

I

IH

A or B ports

‡

V

CC

= 5.5 V,

V

I

= 2.7

V

20 20

µ

A

Control inputs

–0.1 –0.1

I

IL

A or B ports

‡

V

CC

=

5.5 V

,

V

I

=

0.4 V

–0.1 –0.1

mA

I

O

§

VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA

Outputs high 21 33 21 30

I

CC

VCC = 5.5 V

Outputs low 23 36 23 33

mA

Outputs disabled 25 40 25 36

†

All typical values are VCC = 5 V, TA = 25°C.

‡

For I/O ports, the parameters IIH and IIL include the off-state output current.

§

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX

¶

UNIT

SN54ALS1245A SN74ALS1245A

MIN MAX MIN MAX

t

PLH

2 19 2 13

t

PHL

A or B

B or A

2 15 2 13

ns

t

PZH

8 30 8 25

t

PZL

OE

A or B

8 29 8 25

ns

t

PHZ

2 14 2 12

t

PLZ

OE

A or B

3 30 3 18

ns

¶

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN54ALS1245A, SN74ALS1245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SDAS245A – DECEMBER 1982 – REVISED JANUAR Y 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

t

PHZ

t

PLZ

t

PHL

t

PLH

0.3 V

t

PZL

t

PZH

t

PLH

t

PHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

From Output

Under Test

Test
Point

R1

S1

C

L

(see Note A)

7 V

1.3 V

1.3 V1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V 1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

t

w

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note C)

1.3 V 1.3 V

1.3 V1.3 V

1.3 V 1.3 V

1.3 V1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

V

OL

V

OH

V

OH

V

OL

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

[

0 V

V

OH

V

OL

[

3.5 V

In-Phase

Output

0.3 V

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2

V

CC

R

L

Test
Point

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

From Output

Under Test

Test
Point

C

L

(see Note A)

R

L

RL = R1 = R2

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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Copyright  1998, Texas Instruments Incorporated