Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain six independent hex
inverters. They perform the Boolean function
Y = A
.
The SN54ALS04B and SN54AS04 are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS04B and SN74AS04 are characterized
for operation from 0°C to 70°C.
FUNCTION TABLE
(each inverter)
INPUT
OUTPUT
A
HL
LH
Y
SN54ALS04B, SN54AS04 ...J PACKAGE
SN74ALS04B, SN74AS04 ...D OR N PACKAGE
SN54ALS04B, SN54AS04 . . . FK PACKAGE
2A
NC
2Y
NC
3A
NC – No internal connection
1A
1Y
2A
2Y
3A
3Y
GND
3 2 1 20 19
4
5
6
7
8
9 10 11 12 13
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
7
(TOP VIEW)
1Y1ANC
3Y
NC
GND
V
CC
6A
6Y
5A
5Y
4A
9
4Y
8
CC
V
6A
18
6Y
17
NC
16
5A
15
NC
14
5Y
4Y
4A
1
3
5
9
11
13
†
1
logic symbol
1A
2A
3A
4A
5A
6A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
10
12
logic diagram (positive logic)
2
1Y
4
2Y
6
3Y
8
4Y
5Y
6Y
12
3
2A2Y
5
3A3Y
9
4A4Y
11
5A5Y
13
6A6Y
1Y1A
4
6
8
10
12
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04
UNIT
VILLow-level input voltage
V
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
HEX INVERTERS
SDAS063B – APRIL 1982 – REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
TO
OUTPUT
RL = 500 Ω,
TA = MIN to MAX
SN54AS04SN74AS04
MINMAXMINMAX
1615
14.514
†
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54ALS04B, SN54AS04, SN74ALS04B, SN74AS04
HEX INVERTERS
SDAS063B – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
R
L
Test
Point
C
L
R
L
From Output
Under Test
C
(see Note A)
Test
Point
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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