TEXAS INSTRUMENTS SN54AHCT373 Technical data
SOIC
DW
AHCT373
40°C to 85°C
TSSOP
PW
HB373
查询5962-9686701Q2A供应商
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN74AHCT373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
SN54AHCT373 ...J OR W PACKAGE
(TOP VIEW)
20
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
19
18
17
16
15
14
13
12
11
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
CC
description/ordering information
SN54AHCT373, SN74AHCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS239M – OCTOBER 1995 – REVISED JUL Y 2003
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHCT373 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
1D1QOE
3 2 1 20 19
4
5
6
7
8
9 10 11 12 13
LE
4Q
GND
V
CC
5Q
8Q
18
17
16
15
14
5D
8D
7D
7Q
6Q
6D
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to V
through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMA TION
T
A
PDIP – N Tube SN74AHCT373N SN74AHCT373N
°
–
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SOP – NS Tape and reel SN74AHCT373NSR AHCT373
°
SSOP – DB Tape and reel SN74AHCT373DBR HB373
TVSOP – DGV Tape and reel SN74AHCT373DGVR HB373
CDIP – J Tube SNJ54AHCT373J SNJ54AHCT373J
CFP – W Tube SNJ54AHCT373W SNJ54AHCT373W
LCCC – FK Tube SNJ54AHCT373FK SNJ54AHCT373FK
PACKAGE
–
–
†
Tube SN74AHCT373DW
Tape and reel SN74AHCT373DWR
Tube SN74AHCT373PW
Tape and reel SN74AHCT373PWR
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54AHCT373, SN74AHCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS239M – OCTOBER 1995 – REVISED JULY 2003
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
logic diagram (positive logic)
1
OE
11
LE
(each latch)
OUTPUT
Q
0
1D
3
To Seven Other Channels
C1
1D
2
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
UNIT
SN54AHCT373, SN74AHCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS239M – OCTOBER 1995 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54AHCT373 SN74AHCT373
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
TA = 25°C SN54AHCT373 SN74AHCT373
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
I
I
I
∆I
C
C
OH
OL
OZ
I
CC
i
o
CC
CC
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,
†
Other inputs at VCC or GND
VI = VCC or GND 5 V 4 10 10 pF
VO = VCC or GND 5 V 9 pF
5.5 V 1.35 1.5 1.5 mA
CC
0 V
CC
V
m
A
m
A
m
A
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHCT373 SN74AHCT373
MIN MAX MIN MAX MIN MAX
t
w
t
su
t
h
Pulse duration, LE high 6.5 6.5 6.5 ns
Setup time, data before LE↓
Hold time, data after LE↓ 3.5 3.5 3.5 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1.5 1.5 1.5 ns
= 5 V ± 0.5 V
CC
3
SN54AHCT373, SN74AHCT373
PARAMETER
UNIT
DQC
15 pF
ns
LEQC
15 pF
ns
OE
Q
C
15 pF
ns
OE
Q
C
15 pF
ns
DQC
50 pF
ns
LEQC
50 pF
ns
OE
Q
C
50 pF
ns
OE
Q
C
50 pF
ns
PARAMETER
UNIT
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS239M – OCTOBER 1995 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 50 pF 1** 1 ns
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
TA = 25°C SN54AHCT373 SN74AHCT373
MIN TYP MAX MIN MAX MIN MAX
5.1* 8.5* 1* 9.5* 1 9.5
5.1* 8.5* 1* 9.5* 1 9.5
7.7* 12.3* 1* 13.5* 1 13.5
7.7* 12.3* 1* 13.5* 1 13.5
6.3* 10.9* 1* 12.5* 1 12.5
6.3* 10.9* 1* 12.5* 1 12.5
6* 10.2* 1* 11* 1 11
6* 10.2* 1* 11* 1 11
5.9 9.5 1 10.5 1 10.5
5.9 9.5 1 10.5 1 10.5
8.5 13.3 1 14.5 1 14.5
8.5 13.3 1 14.5 1 14.5
7.1 11.9 1 13.5 1 13.5
7.1 11.9 1 13.5 1 13.5
6.8 11.2 1 12 1 12
6.8 11.2 1 12 1 12
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 17 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL
OL
OH
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
SN74AHCT373
MIN TYP MAX
0.8 1.2 V
–0.8 –1.2 V
4.1 V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHCT373, SN74AHCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS239M – OCTOBER 1995 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
3 V
0 V
3 V
0 V
t
PHL
V
t
PLH
CC
CC
OH
V
OL
V
OH
V
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V
t
CC
CC
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Loading...