Schmitt-Trigger Circuitry On A, B, and CLR
Inputs for Slow Input Transition Rates
D
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D
Retriggerable for Very Long Output Pulses
D
Overriding Clear Terminates Output Pulse
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A
goes high. In the second method, the B input is
high, and the A
the A
input is low, the B input is high, and the clear
(CLR
) input goes high.
input goes low. In the third method,
The output pulse duration is programmed by
selecting external resistance and capacitance
values. The external timing capacitor must be
connected between C
and an external resistor connected between
R
ext/Cext
and VCC. To obtain variable pulse
durations, connect an external variable resistance
between R
ext/Cext
duration also can be reduced by taking CLR
input is low, and the B input
and R
ext
ext/Cext
and VCC. The output pulse
(positive)
low.
SN54AHCT123A ...J OR W PACKAGE
SN74AHCT123A . . . D, DB, DGV, N, OR PW PACKAGE
1CLR
2R
ext/Cext
SN54AHCT123A . . . FK PACKAGE
2C
GND
1A
1B
1Q
2Q
ext
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
(TOP VIEW)
V
CC
1R
ext/Cext
1C
ext
1Q
2Q
2CLR
2B
2A
ext
/C
ext
GND
NC
CC
V
2A
1R
18
17
16
15
14
2B
1C
ext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2C
ext
1B1ANC
3212019
4
5
6
7
8
910111213
ext
/C
ext
2R
NC – No internal connection
T
A
PDIP – NTubeSN74AHCT123ANSN74AHCT123AN
–
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SSOP – DBTape and reelSN74AHCT123ADBRHB123A
TSSOP – PWTape and reelSN74AHCT123APWRHB123A
TVSOP – DGVTape and reelSN74AHCT123ADGVRHB123A
CDIP – JTubeSNJ54AHCT123AJSNJ54AHCT123AJ
CFP – WTubeSNJ54AHCT123AWSNJ54AHCT123AW
LCCC – FKTubeSNJ54AHCT123AFKSNJ54AHCT123AFK
ORDERING INFORMA TION
PACKAGE
–
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
†
TubeSN74AHCT123AD
Tape and reelSN74AHCT123ADR
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A
rates with jitter-free triggering at the outputs.
, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A
high-level-active (B) input. Pulse duration can be reduced by taking CLR
A
or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early
low. CLR input can be used to override
) or
clearing.
The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’AHCT123A is shown in Figure 10. V ariations in output pulse
duration versus supply voltage and temperature are shown in Figure 6.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
For additional application information on multivibrators, see the application report, Designing With theSN74AHC123A and SN74AHCT123A, literature number SCLA014.
FUNCTION TABLE
(each multivibrator)
INPUTS
CLRABQQ
LXXLH
XHXL†H
XXLL†H
HL↑
H
↑LH
†
These outputs are based on the
assumption that the indicated
steady-state conditions at the A
B inputs have been set up long enough to
complete any pulse started before the
setup.
#
OUTPUTS
†
†
H
and
logic diagram, each multivibrator (positive logic)
A
B
CLR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
R
ext/Cext
C
ext
Q
R
Q
input/output timing diagram
A
B
CLR
R
ext/Cext
Q
SN54AHCT123A, SN74AHCT123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS420G – JUNE 1998 – REVISED APRIL 2003
t
rr
Q
t
w
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to the network ground terminal.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
B. All input pulses are supplied by generators having the following characteristics: ZO = 50 Ω, tr +3 ns, tf + 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
C
LOAD CIRCUIT
1.5 V
1.5 V
DELA Y TIMES
L
50% V
50% V
Test
Point
CC
CC
3 V
0 V
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Inputs
Outputs
Input CLR
(see Note B)
In-Phase
Output
Out-of-Phase
Output
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V1.5 V
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
DELA Y TIMES
CC
CC
1.5 V1.5 V
50% V
50% V
50% V
t
PHL
t
PLH
CC
3 V
0 V
V
CC
V
V
CC
V
3 V
0 V
V
V
OH
OL
OH
OL
OH
OL
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT123A, SN74AHCT123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS420G – JUNE 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
caution in use
To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep
the wiring between the external components and C
power-down considerations
ext
and R
ext/Cext
terminals as short as possible.
Large values of C
may cause problems when powering down the ’AHCT123A devices because of the amount
ext
of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may
discharge from V
must be limited to 30 mA; therefore, the turn-off time of the V
t = V
CC
× C
ext
through the protection diodes at pin 2 or pin 14. Current through the input protection diodes
CC
/30 mA. For example, if VCC = 5 V and C
= 15 pF , the VCC supply must turn off no faster than
ext
power supply must not be faster than
CC
t = (5 V) ×(15 pF)/30mA = 2.5 ns. Usually , this is not a problem because power supplies are heavily filtered and
cannot discharge at this rate. When a more rapid decrease of V
to zero occurs, the ’AHCT123A devices may
CC
sustain damage. To avoid this possibility, use external clamping diodes.
output pulse duration
The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing
resistance (R
). The timing components are connected as shown in Figure 2.
T
V
CC
R
T
C
T
To R
Terminal
ext/Cext
To C
ext
Terminal
Figure 2. Timing-Component Connections
The pulse duration is given by:
+K
t
w
RT
C
T
(1)
if CT is ≥ 1000 pF, K = 1.0 or
if C
is < 1000 pF, K can be determined from Figure 5
T
where:
= pulse duration in ns
t
w
R
= external timing resistance in kΩ
T
C
= external capacitance in pF
T
K= multiplier factor
Equation 1 and Figure 3 can be used to determine values for pulse duration, external resistance, and external
capacitance.
The minimum input retriggering time (t
the input. After t
, the device retriggers the output. Experimentally , it also can be shown that to retrigger the
MIR
output pulse, the two adjacent input signals should be t
duration is calculated as shown in Figure 3.
t
MIR
) is the minimum time required after the initial signal before retriggering
MIR
apart, where t
MIR
= 0.30 × tw. The retrigger pulse
MIR
Input
Output
t
PLH
t
RT
t
w
tRT = tw + t
Where:
t
= Minimum Input Retriggering Time
MIR
t
= Propagation Delay
PLH
tRT= Retrigger Time
tw= Output Pulse Duration Before Retriggering
= (K × RT × CT) + t
PLH
PLH
Figure 3. Retrigger Pulse Duration
The minimum value from the end of the input pulse to the beginning of the retriggered output should be
approximately 15 ns to ensure a retriggered output (see Figure 4).
Input
t
MRT
Output
t
= Minimum Time Between the End of the Second Input Pulse and the Beginning of the Retriggered Output
MRT
t
= 15 ns
MRT
Figure 4. Input/Output Requirements
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT123A, SN74AHCT123A
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SCLS420G – JUNE 1998 – REVISED APRIL 2003
Output Pulse Duration – ns
–
w
t
1.00E+09
1.00E+08
1.00E+07
1.00E+06
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
APPLICATION INFORMATION
VCC = 5 V
TA = 25°C
RT = 150k Ω
RT = 80k Ω
RT = 1k Ω
11010210
CT – External Timing Capacitance – pF
RT = 200k Ω
RT = 5k Ω
3
10
†
RT = 10k Ω
4
10
5
10
6
10
7
Figure 5. Output Pulse Duration vs External Timing Capacitance
14%
tw = 866 ns at:
12%
VCC = 5 V,
RT = 10 kΩ
10%
CT = 50 pF
TA = 25°C
8%
6%
4%
2%
0%
–2%
Variation in Output Pulse Duration
–4%
–6%
–60–40–20020406080100120140160
Temperature – °C
VCC = 2.5 V
VCC = 3 V
VCC = 3.5 V
VCC = 4 V
VCC = 5 V
VCC = 6 V
VCC = 7 V
Figure 6. Variations in Output Pulse Duration vs Temperature
180
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-NC-NC-NC
CU NIPDAULevel-NC-NC-NC
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
26-Sep-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
20
22
23
24
25
19
21
1282627
12
131415161817
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
(10,31)
(12,58)
(12,58)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
0.495
0.495
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
24
112
A
0,23
0,13
13
0,07
4,50
4,30
M
6,60
6,20
0,16 NOM
Gage Plane
0,25
0°–8°
0,75
0,50
1,20 MAX
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
0,15
0,05
14
3,70
3,50
Seating Plane
3,50
20
5,10
4,90
0,08
5,103,70
4,90
382416
7,90
7,70
48
9,80
9,60
56
11,40
11,20
4073251/E 08/00
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
6,60
6,20
14
0,10
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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Mailing Address:Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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