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SN54AHCT00, SN74AHCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS229H – OCTOBER 1995 – REVISED JANUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
description
The ’AHCT00 devices perform the Boolean
function Y = A • B or Y = A + B in positive logic.
The SN54AHCT00 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AHCT00 is characterized for
operation from –40°C to 85°C.
SN74AHCT00 . .. D, DB, DGV, N, OR PW PACKAGE
FUNCTION TABLE
(each gate)
INPUTS
A B
H H L
L XH
X L H
OUTPUT
Y
SN54AHCT00 ...J OR W PACKAGE
(TOP VIEW)
NC
14
13
12
11
10
9
8
CC
V
3Y
V
4B
4A
4Y
3B
3A
3Y
4B
18
17
16
15
14
3A
CC
4A
NC
4Y
NC
3B
1A
1
1B
2
1Y
3
2A
4
2B
5
6
2Y
GND
SN54AHCT00 . . . FK PACKAGE
7
(TOP VIEW)
1B1ANC
1Y
NC
2A
NC
2B
3212019
4
5
6
7
8
910111213
2Y
GND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54AHCT00, SN74AHCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS229H – OCTOBER 1995 – REVISED JANUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, DB, DGV, J, N, PW, and W packages.
†
1
1A
1B
2A
2B
3A
3B
4A
4B
2
4
5
9
10
12
13
&
3
1Y
6
2Y
8
3Y
11
4Y
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
PARAMETER
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
pF
ns
SN54AHCT00, SN74AHCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS229H – OCTOBER 1995 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHCT00 SN74AHCT00
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 2 20 20
One input at 3.4 V ,
†
Other inputs at VCC or GND
VI = VCC or GND 5 V 2 10 10 pF
I
I
∆I
C
OH
OL
I
CC
CC
i
, literature number SCBA004.
CC
5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT00 SN74AHCT00
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
CC
0 V
CC
V
m
A
m
A
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
=
L
= 50
L
p
p
TA = 25°C SN54AHCT00 SN74AHCT00
MIN TYP MAX MIN MAX MIN MAX
5** 6.9** 1** 8** 1 8
5** 6.9** 1** 8** 1 8
5.5 7.9 1 9 1 9
5.5 7.9 1 9 1 9
3
SN54AHCT00, SN74AHCT00
PARAMETER
UNIT
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS229H – OCTOBER 1995 – REVISED JANUARY 2000
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 10.5 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL
OL
OH
= 5 V, T
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 25°C
A
SN74AHCT00
MIN TYP MAX
0.4 0.8 V
–0.4 –0.8 V
4.5 V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHCT00, SN74AHCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS229H – OCTOBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3-STATE AND OPEN-DRAIN OUTPUTS
CC
CC
LOAD CIRCUIT FOR
3 V
0 V
3 V
0 V
t
PHL
V
t
PLH
CC
CC
OH
V
OL
V
OH
V
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V
t
CC
CC
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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