Texas Instruments SN54ACT7811GB Datasheet
SN54ACT7811
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996
D
Member of the Texas Instruments
Widebus
D
Independent Asynchronous Inputs and
Family
Outputs
D
1024 Words × 18 Bits
D
Read and Write Operations Can Be
Synchronized to Independent System
Clocks
D
Programmable Almost-Full/Almost-Empty
Flag
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN54ACT781 1 is a 1024 × 18-bit FIFO for high speed and fast access times. It processes data
at rates up to 28.5 MHz and access times of 20 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is easily accomplished in both word width and word depth.
The SN54ACT781 1 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent read and write (interrupts, requests) to their respective system
clock.
D
Input-Ready, Output-Ready, and Half-Full
Flags
D
Cascadable in Word Width and/or Word
Depth
D
Fast Access Times of 20 ns With a 50-pF
Load
D
High Output Drive for Direct Bus Interface
D
Package Options Include 68-Pin Ceramic
PGA (GB) or Space-Saving 68-Pin Ceramic
Quad Flatpack (HV)
†
1024 × 18
The SN54ACT7811 is characterized for operation from –55°C to 125°C.
GB PACKAGE
(TOP VIEW)
123456789
A
B
C
D
E
F
G
H
J
†
The SN54ACT781 1 HV is not production released.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996
GB-Package Terminal Assignments
TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME
A1 Q15 B7 Q5 F2 D17 H8 D0
A2 Q13 B8 Q4 F8 WRTEN2 H9 DAF
A3 Q12 B9 Q1 F9 AF/AE J1 D11
A4 Q11 C1 RESET G1 D16 J2 D10
A5 Q10 C2 Q16 G2 D15 J3 D8
A6 Q8 C8 Q2 G8 WRTCLK J4 NC
A7 Q7 C9 Q0 G9 WRTEN1 J5 D7
A8 Q6 D1 OE H1 D14 J6 D6
A9 Q3 D9 HF H2 D13 J7 D5
B1 OR E1 RDEN1 H3 D12 J8 D3
B2 Q17 E2 RDEN2 H4 D9 J9 D2
B3 Q14 E9 IR H6 D4
B5 Q9 F1 RDCLK H7 D1
VCC = B4, C6, C7, D2, D7, E8, G3, G4, G6 GND = B6, C3, C4, D3, D8, F3, F7, G7, H5
NC = No internal connection
D14
D13
D12
D1 1
D10
D9
V
CC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HV PACKAGE
(TOP VIEW)
D17
GND
RDCLK
RDEN1
D15
D16
87 65493
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
31 32 33 34
30
RDEN2OERESET
†
CC
V
GND
OR
168672
35 36 37 38 39
66 65
CC
Q17
Q16
V
64 63 62 61
40 41 42 43
GND
Q15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
Q14
Q13
GND
Q12
Q11
V
CC
Q10
Q9
GND
Q8
Q7
V
CC
Q6
Q5
GND
Q4
IR
HF
Q0
Q1
Q2
CC
V
WRTEN1
WRTEN2
CC
V
GND
AF/AE
DAF
GND
WRTCLK
†
The SN54ACT781 1 HV is not production released.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GND
Q3
CC
V
SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996
logic symbol
†
WRTCLK
WRTEN1
WRTEN2
RESET
RDCLK
RDEN1
OE
RDEN2
DAF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
C1
G8
G9
F8
F1
E1
D1
E2
H9
H8
H7
J9
J8
H6
J7
J6
J5
J3
H4
J2
J1
H3
H2
H1
G2
G1
F2
FIFO 1024 × 18
RESET
WRTCLK
&
WRTEN
RDCLK
&
EN1
DEF ALMOST FULL
0
17
ALMOST FULL/EMPTY
RDEN
Data
Φ
HALF FULL
Data
IN RDY
OUT RDY
1
17
E9
IR
D9
HF
F9
AF/AE
B1
OR
C9
0
B9
C8
A9
B8
B7
A8
A7
A6
B5
A5
A4
A3
A2
B3
A1
C2
B2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the GB package.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996
functional block diagram
OE
D0 – D17
RDCLK
RDEN1
RDEN2
WRTCLK
WRTEN1
WRTEN2
RESET
DAF
Synchronous
Read
Control
Synchronous
Write
Control
Reset
Logic
Read
Pointer
Write
Pointer
Status-
Flag
Logic
Location 1
Location 2
1024 × 18 RAM
Location 1023
Location 1024
Register
Q0 – Q17
OR
IR
HF
AF/AE
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
AF/AE
F9
O
TERMINAL
NAME NO.
DAF H9 I
D0–D17
HF D9 O
IR E9 O
OE D1 I
OR B1 O
Q0–Q17
RDCLK F1 I
RDEN1,
RDEN2
RESET C1 I
†
Terminals listed are for the GB package.
†
F2, G1, G2,
H1–H4, H6–H8,
J1–J3, J5–J9
A1–A9, B2, B3,
B5, B7–B9, C2,
C8, C9
E1
E2
SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996
Terminal Functions
AF/AE boundary is defined by the AF/AE offset value (X). This value can be programmed during
reset, or the default value of 256 can be used. The AF/AE flag is high when the FIFO contains (X + 1)
or fewer words or (1025 – X) or more words. The AF/AE flag is low when the FIFO contains between
(X + 2) and (1024 - X) words.
Programming procedure for AF/AE – The AF/AE flag is programmed during each reset cycle. The
AF/AE offset value (X) is either a user-defined value or the default of X = 256. Instructions to program
AF/AE using both methods are as follows:
User-defined X
Step 1:
Step 2:
Step 3:
Step 4:
Default X
T o redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset
cycle.
Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the
AF/AE offset value (X). With DAF
flag using X.
Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0–D8 also carry the AF/AE
I
offset value (X) on a high-to-low transition of the DAF
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512
or fewer words.
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
is driven low on the rising edge of the second write clock (WRTCLK) pulse. IR is then driven high on
the rising edge of the second WRTCLK pulse after RESET
is driven low, IR is driven high on the second WRTCLK pulse after the first valid read.
Output enable. The data-out (Q0–Q17) outputs are in the high-impedance state when OE is low. OE
must be high before the rising edge of read clock (RDCLK) to read a word from memory.
Output ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR
is set low on the rising edge of the third read clock (RDCLK) pulse. OR is set high on the rising edge
of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the
rising edge of the first RDCLK pulse after the last word is read.
Data outputs. The first data word to be loaded into the FIFO is moved to the data-out (Q0–Q17)
register on the rising edge of the third read clock (RDCLK) pulse to occur after the first valid write.
O
The read-enable (RDEN1, RDEN2) inputs do not affect this operation. The following data is unloaded
on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high.
Read clock. Data is read out of memory on a low-to-high transition at RDCLK if the OR output and
the OE, RDEN1, and RDEN2 control inputs are high. RDCLK is a free-running clock and functions
as the synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.
Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
I
of memory. The read enables are not used to read the first word stored in memory.
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
and IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF
level, a low pulse on RESET
previously stored. With DAF
default value of X = 256.
Take DAF
If the reset (RESET) input is not already low, take RESET low.
With DAF held low, take RESET high. This defines the AF/AE flag using X.
To retain the current offset for the next reset, keep DAF low.
from high to low.
held low, a low pulse on the reset (RESET) input defines the AF/AE
input.
goes high. After the FIFO is filled and IR
input at a low
defines AF/AE using the AF/AE offset value (X), where X is the value
at a high level, a low-level pulse on RESET defines AF/AE using the
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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