Texas Instruments SN54ACT3641HFP, SNJ54ACT3641HFP Datasheet

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SN54ACT3641

1024 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

Clocked FIFO Buffering Data From Port A to Port B

Memory Size: 1024 × 36

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Programmable Almost-Full and Almost-Empty Flags

Microprocessor Interface Control Logic

Input-Ready and Almost-Full Flags Synchronized by CLKA

Output-Ready and Almost-Empty Flags Synchronized by CLKB

Low-Power 0.8 µm Advanced CMOS T echnology

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 15 ns

Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9560801QYA and 5962-9560801NXD

Package Options include 132-Pin Ceramic Quad Flat (HFP) and 120-Pin Plastic Quad Flat (PCB) Packages

description

The SN54ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 15 ns. The 1024 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion is also possible in word depth.

The SN54ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF

) flag of the FIFO are two-stage synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE

) flag of the FIFO are two-stage synchronized to CLKB. Offset

values for the AF

and AE flags of the FIFO can be programmed from port A or through a serial input. The SN54ACT3641 is characterized for operation over the full military temperature range of – 55°C to 125°C. For more information on this device family, see the following application reports:

•

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA009)

•

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

•

Metastability Performance of Clocked FIFOs

(literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116 115 114 113 112

111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

5251 83828180797877767574737271706968676665646362616059585756555453

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

NC B35 B34 B33 B32

GND

B31 B30 B29 B28 B27 B26

B25 B24

GND

B23 B22 B21 B20 B19 B18

GND

B17 B16

B15 B14 B13 B12

GND

NC NC A35 A34 A33 A32 V

A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 V

A21 A20 A19 A18 GND A17 A16 A15 A14 A13 V

A12 NC

HFP PACKAGE

(TOP VIEW)

NCNCV

CLKB

ENB

W/RB

CSB

GND

MBF1

GND

MBBNCRFM

RTM

FS1/SEN

FSO/SD

GND

RST

MBA

MBF2AEAF

ORIRCSA

W/RA

ENA

CLKA

GND

B1 1

B10

B9B8B7

GND

B5B4B3B2B1

GND

A0A1A2

A3A4A5

GND

A6A7A8

A10

A1 1

GND

NC – No internal connection

SN54ACT3641

1024 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCB PACKAGE

(TOP VIEW)

A35 A34 A33 A32

A31 A30

GND

A29 A28 A27 A26 A25 A24 A23

GND

A22

A21 A20 A19 A18

GND

A17 A16 A15 A14 A13

A12

B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 V

B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 V

B15 B14 B13 B12 GND

GND

CLKA

ENA

GND

A1 1

A10

CSAIROR

MBAAFGND

FS0/SD

FS1/SEN

RTM

MBF1

GND

W/RA

A7A6A5

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

CSB

W/RB

ENB

CLKB

B10

5556575859

RST

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

MBB

GND

B1 1

MBF2

RFM

NC – No internal connection

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Port-A

Control

Logic

CLKA

CSA

W/RA

ENA

MBA

Reset Logic

RST

1024 × 36

SRAM

Input Register

Output Register

Mail1

Write

Pointer

Read

Pointer

Status-Flag

Logic

Flag-Offset

Mail2

Port-B

Control

Logic

FS0/SD

FS1/SEN

A0–A35

MBF2

MBF1

OR AE

B0–B35

CLKB CSB W/RB

ENB MBB

Synch

Retransmit

Logic

RTM

RFM

SN54ACT3641

1024 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

I/O DESCRIPTION

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.

AE O

Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less than or equal to the value in the almost-empty offset register (X).

AF O

Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO is less than or equal to the value in the almost-full offset register (Y).

B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IR and AF

are synchronous to the low-to-high transition of CLKA.

CLKB I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. OR and AE

are synchronous to the low-to-high transition of CLKB.

CSA I

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0–A35 outputs are in the high-impedance state when CSA

is high.

CSB I

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0–B35 outputs are in the high-impedance state when CSB

is high. ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1/SEN,

FS0/SD

Flag offset select 1/serial enable, flag offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset-register programming. During a device reset, FS1/SEN

and FS0/SD select the flag offset-programming method. Three offset-register programming methods are available: automatically load one of two preset values, parallel load from port A, and serial load.

When serial load is selected for flag offset-register programming, FS1/SEN

is used as an enable synchronous to the

low-to-high transition of CLKA. When FS1/SEN

is low, a rising edge on CLKA loads the bit present on FS0/SD into the X-and Y -offset registers. The number of bit writes required to program the offset registers is 20. The first bit write stores the Y -register MSB and the last bit write stores the X-register LSB.

IR O

Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.

MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.

MBB I

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO data for output.

MBF1 O

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by a reset.

MBF2 O

Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by a reset.

OR O

Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.

RFM I

Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset the read pointer to the beginning retransmit location and output the first selected retransmit data.

RST I

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST

is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.

RTM I

Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO out of retransmit mode.

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

I/O DESCRIPTION

W/RA I

Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R

A is high.

W/RB I

Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W

/RB is low.

detailed description

reset

The SN54ACT3641 is reset by taking the reset (RST

) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset initializes the memory read and write pointers and forces the IR flag low, the OR flag low, the AE

flag low, and

the AF

flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its IR flag is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

almost-empty flag and almost-full flag offset programming

Two registers in the SN54ACT3641 are used to hold the of fset values for the AE

and AF flags. The AE flag offset

flag offset register is labeled Y . The of fset registers can be loaded with a value in three ways: one of two preset values are loaded into the offset registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high transition on RST

(see Table 1).

T able 1. Flag Programming

FS1 FS0 RST

X AND Y REGISTERS

†

H H ↑ Serial load H L ↑ 64 L H ↑ 8 L L ↑ Parallel load from port A

†

X register holds the offset for AE; Y register holds the offset for AF

preset values

If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of an RST low-to-high transition according to Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.

parallel load from port A

To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high transition of RST

. After this reset is complete, IR is set high after two low-to-high transitions on CLKA. The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset register of the SN54ACT3641 uses port-A inputs (A9–A0). Data input A9 is used as the most-significant bit of the binary number. Each register value can be programmed from 1 to 1020. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.

SN54ACT3641

1024 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

serial load

To program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN high during the low-to-high transition of RST

. After this reset is complete, the X-and Y -register values are loaded bitwise through

FS0/SD on each low-to-high transition of CLKA that FS1/SEN

is low. T wenty-bit writes are needed to complete the programming. The first bit write stores the most-significant bit of the Y register, and the last bit write stores the least-significant bit of the the X register. Each register value can be programmed from 1 to 1020.

When the option is chosen to program the offset registers serially, IR remains low until all 20 bits are written. IR is set high by the low-to-high transition of CLKA after the last bit is loaded to allow normal FIFO operation.

FIFO write/read operation

The state of the port-A data (A0 –A35) outputs is controlled by the port-A chip select (CSA

) and the port-A

write/read select (W/R

A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

high. The A0–A35 outputs are active when both CSA

and W/RA are low.

Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA

and the

port-A mailbox select (MBA) are low, W/R

A, the port-A enable (ENA), and the IR flag are high (see Table 2).

Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

A0–A35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, mail2 register None L L H L ↑ Active, mail2 register None L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A with the exception that the port-B write/read select (W

/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is

controlled by the port-B chip select (CSB

) and the port-B write/read select (W/RB). The B0–B35 outputs are

in the high-impedance state when either CSB

is high or W/RB is low. The B0–B35 outputs are active when CSB

is low and W/RB is high. Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB

and the port-B

mailbox select (MBB) are low, W

/RB, the port-B enable (ENB), and the OR flag are high (see Table 3). Reads

from the FIFO are independent of any concurrent FIFO writes.

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB CLKB

B0–B35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L L L X X In high-impedance state None L L H L ↑ In high-impedance state None L L H H ↑ In high-impedance state Mail2 write L H L L X Active, FIFO output register None L H H L ↑ Active, FIFO output register FIFO read L H L H X Active, mail1 register None L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setup- and hold-time window of the cycle.

When OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high transition that sets the flag high. When OR is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB

), write/read select (W/RB), enable (ENB), and

mailbox select (MBB).

synchronized FIFO flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flags’ reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another

OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.

Table 4 shows the relationship of each flag to the number of words stored in memory.

Table 4. FIFO Flag Operation

NUMBER OF WORDS IN

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

FIFO

†‡

OR AE AF IR

0 L L H H

1 to X H LHH

(X + 1) to [1024 – (Y + 1)] H HHH

(1024 – Y) to 1023 H HLH

1024 H H L L

†

X is the almost-empty offset for AE. Y is the almost-full offset for AF.

‡

When a word is present in the FIFO output register, its previous memory location is free.

SN54ACT3641

1024 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGBS309A – AUGUST 1995 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output-ready flag (OR)

The OR flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When the OR flag is high, new data is present in the FIFO output register. When OR is low , the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an OR flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty , empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the time the word was written. The OR flag of the FIFO remains low until the third low-to-high transition of CLKB occurs, simultaneously forcing OR high and shifting the word to the FIFO output register.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time t

sk(1)

, or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first

synchronization cycle (see Figure 6).

input-ready flag (IR)

The IR flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When IR is high, a memory location is free in the SRAM to write new data. No memory locations are free when the IR flag is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an IR flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of three cycles of CLKA. Therefore, IR is low if less than two cycles of CLKA have elapsed since the next memory write location has been read. The second low-to-high transition on CLKA after the read sets IR high, and data can be written in the following cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time t

sk(1)

, or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first

synchronization cycle (see Figure 7).

almost-empty flag (AE)

The AE flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The state machine that controls an AE

flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see

almost-empty flag and almost-full flag offset programming

). AE is low when the FIFO contains X or fewer words and is high when the FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory.

Two low-to-high transitions of CLKB are required after a FIFO write for the AE

flag to reflect the new level of

fill. Therefore, the AE

flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have

not elapsed since the write that filled the memory to the (X + 1) level. AE

is set high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time t

sk(2)

, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 8).

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

almost-full flag (AF)

The AF flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The state machine that controls an AF

flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see

almost-empty flag and almost-full flag offset programming

). AF is low when the

number of words in the FIFO is greater than or equal to (1024 – Y). AF

is high when the number of words in the FIFO is less than or equal to [1024 – (Y + 1)]. A data word present in the FIFO output register has been read from memory.

Two low-to-high transitions of CLKA are required after a FIFO read for its AF

flag to reflect the new level of fill.

Therefore, the AF

flag of a FIFO containing [1024 – (Y + 1)] or fewer words remains low if two cycles of CLKA

have not elapsed since the read that reduced the number of words in memory to [1024 – (Y + 1)]. AF

is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of words in memory to [1024 – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time t

sk(2)

, or greater , after the read that reduces the number of words in memory to [1024 – (Y + 1)]. Otherwise, the

subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).

synchronous retransmit

The synchronous-retransmit feature of the SN54ACT3641 allows FIFO data to be read repeatedly , starting at a user-selected position. First the FIFO is put into retransmit mode to select a beginning word and prevent ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode at any time and allow normal device operation.

The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit-mode (RTM) input is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.

When two or more reads have been done, past the initial retransmit word, a retransmit is initiated by a low-to-high transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first retransmit word to the FIFO output register and subsequent reads can begin immediately . Retransmit loops can be done endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that takes the FIFO out of retransmit mode.

When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates normally , incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR and AF

flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that stores (102 – Y) words after the first retransmit word. The IR flag is set low by the 1024th write after the first retransmit word.

When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with the shadow read-pointer value and the OR flag reflects the new level of fill immediately . If the retransmit changes the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are needed to switch AE

high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode

shifts the read pointer used by the IR and AF

flags from the shadow to the current read pointer. If the change

of read pointer used by IR and AF

should cause one or both flags to transition high, at least two CLKA synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of IR if it occurs at time t

sk(1)

, or greater, after the rising CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of AF

if it occurs at time t

sk(2)

, or greater, after the rising CLKB edge (see Figure 14).

SN54ACT3641

1024 × 36

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mailbox registers

Two 36-bit bypass registers are on the SN54ACT3641 to pass command and control information between port A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port A write is selected by CSA

, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data to

the mail2 register when a port-B write is selected by CSB

, W/RB, and ENB with MBB high. Writing data to a mail

or MBF2) low. Attempted writes to a mail register are ignored while

its mail flag is low. When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register

when the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 data is always present on the port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1

)

is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB

, W/RB, and ENB with

MBB high. The mail2 register flag (MBF2

) is set high by a low-to-high transition on CLKA when a port-A read

is selected by CSA

, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read

and changes only when new data is written to the register.

pd(R-F)

CLKA

CLKB

RST

0,1

h(FS)

su(FS)

h(RS)

su(RS)

FS1, FS0

pd(C-IR)

pd(C-OR)

pd(R-F)

MBF1,

MBF2

pd(R-F)

Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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AE Offset

(X)

CLKA

RST

FS1, FS0

ENA

A0–A35

su(FS)

h(FS)

pd(C-IR)

AF Offset

(Y)

First Word Stored in FIFO

h(D)

su(D)

su(EN1)

h(EN1)

NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A

AE Offset

(X) LSB

CLKA

RST

FS1/SEN

FS0/SD

su(FS)

h(FS)

pd(C-IR)

AF Offset

(Y) MSB

h(SD)

su(SD)

h(SD)

su(SD)

h(SEN)

su(SEN)

h(SP)

h(SEN)

su(SEN)

su(FS)

NOTE B: It is not necessary to program of fset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.

Figure 3. Programming the AF Flag and AE Flag Offset Values Serially

SN54ACT3641

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h(EN1)

su(EN1)

su(D)

CLKA

CSA

su(EN2)

w(CLKL)

w(CLKH)

h(EN2)

h(EN1)

su(EN1)

W/RA

MBA

ENA

A0–A35

su(EN2)

h(EN2)

su(EN2)

h(EN2)

su(EN1)

h(D)

h(EN1)

No Operation

High

Figure 4. FIFO Write-Cycle Timing

su(EN1)

Operation

su(EN1)

pd(M-DV)

CLKB

CSB

w(CLKL)

w(CLKH)

h(EN1)

W/RB

MBB

ENB

B0–B35

dis

h(EN1)

High

Figure 5. FIFO Read-Cycle Timing

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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h(EN1)

su(EN1)

CLKA

A0–A35

MBA

ENA

CSA

W/RA

CLKB

CSB

W/RB

MBB

ENB

B0–B35

h(EN2)

su(EN2)

w(CLKH)

w(CLKL)

h(EN1)

pd(C-OR)

Old Data in FIFO Output Register

123

Low

w(CLKL)

w(CLKH)

su(EN1)

h(D)

su(D)

sk(1)

†

Low

High

Low

High

†

sk(1)

is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the

FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t

sk(1)

, the transition

of OR high and the first word load to the output register can occur one CLKB cycle later than shown.

Figure 6. OR-Flag Timing and First Data-Word Fall Through When the FIFO Is Empty

SN54ACT3641

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CLKB

B0–B35

MBB

ENB

CSB

W/RB

CLKA

CSA

W/RA

MBA

ENA

A0–A35

su(EN1)

h(EN1)

su(EN1)

pd(C-IR)

FIFO Full

sk(1)

†

FIFO Output Register Next Word From FIFO

w(CLKH)

w(CLKL)

Write

Low

High

Low

High

h(EN2)

su(EN2)

h(D)

su(D)

High

w(CLKH)

w(CLKL)

pd(C-IR)

†

sk(1)

is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

(1)

, IR can transition high one CLKA cycle later than shown.

Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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(X + 1) Words in FIFO

su(EN1)

CLKA

ENB

ENA

h(EN1)

su(EN1)

sk(2)

†

pd(C-AE)

X Words in FIFO

CLKB

pd(C-AE)

h(EN1)

†

sk(2)

is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than t

sk(2)

, AE

can transition high one CLKB cycle later than shown.

NOTE A: FIFO write (CSA

= L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)

Figure 8. Timing for AE When FIFO Is Almost Empty

(1024 – Y) Words in FIFO

pd(C-AF)

su(EN1)

CLKA

ENB

ENA

su(EN1)

h(EN1)

[1024 – (Y + 1)] Words in FIFO

h(EN1)

sk(2)

‡

CLKB

‡

sk(2)

is the minimum time between a rising CLKA edge and a rising CLKB edge for AF

to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

sk(2)

, AF

can transition high one CLKA cycle later than shown.

NOTE A: FIFO write (CSA

= L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)

Figure 9. Timing for AF When FIFO Is Almost Full

SN54ACT3641

1024 × 36

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CLKB

B0–B35

ENB

su(EN1)

h(EN1)

W0 W1

High

RTM

RFM

Initiate Retransmit Mode With W0 as First Word

Retransmit From Selected Position

su(RM)

h(RM)

su(RM)

h(RM)

su(RM)

h(RM)

End Retransmit

Mode

NOTE A: CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.

Other enables are shown only to relate retransmit operations to the FIFO output register.

Figure 10. Retransmit Timing Showing Minimum Retransmit Length

h(RM)

CLKB

RTM

High

RFM

su(RM)

pd(C-AE)

X or Fewer Words From Empty

(X + 1) or More Words From Empty

NOTE A: X is the value loaded in the AE

flag offset register.

Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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FIFO Filled to First Retransmit Word

CLKA

su(RM)

h(RM)

RTM

sk(1)

†

CLKB

pd(C-IR)

One or More Write Locations Available

†

sk(1)

is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

(1)

, IR can transition high one CLKA cycle later than shown.

Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available

CLKA

su(RM)

h(RM)

RTM

sk(2)

‡

(1024 – Y) or More Words Past First Retransmit Word

CLKB

pd(C-AE)

(Y + 1) or More Write Locations Available

‡

sk(2)

is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than t

sk(2)

, AF

can transition high one CLKA cycle later than shown.

NOTE A: Y is the value loaded in the AF

flag offset register.

Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)

or More Write Locations Are Available

SN54ACT3641

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dis

ППППППП

ООООООО

CLKA

CSA

W/RA

su(EN2)

h(D)

MBA

ENA

A0–A35

ООООООО

h(EN2)

su(D)

CLKB

h(EN1)

CSB

su(EN1)

pd(C-MF)

MBF1

W/RB

MBB

ENB

B0–B35

FIFO Output Register

W1 (remains valid in mail1 register after read)

pd(C-MR)

pd(M-DV)

Figure 14. Timing for Mail1 Register and MBF1 Flag

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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dis

pd(C-MR)

CLKB

CSB

W/RA

MBB

ENB

A0–A35

CLKA

CSA

MBF2

W/RB

MBA

ENA

B0–B35

su(EN2)

h(D)

h(EN2)

su(D)

h(EN1)

su(EN1)

pd(C-MF)

W1 (remains valid in mail2 register after read)

Figure 15. Timing for Mail2 Register and MBF2 Flag

SN54ACT3641

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

recommended operating conditions

MIN MAX UNIT

Supply voltage 4.5 5.5 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

High-level output current –4 mA

Low-level output current 8 mA

Operating free-air temperature –55 125 °C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

VCC = 4.5 V, IOH = –4 mA 2.4 V

VCC = 4.5 V, IOL = 8 mA 0.5 V

VCC = 5.5 V, VI = VCC or 0 ±5 µA

VCC = 5.5 V, VO = VCC or 0 ±5 µA

VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA

CSA = V

A0–A35 0

CSB = V

B0–B35 0

∆I

VCC = 5.5 V , One input at 3.4 V,

CSA = V

A0–A35 1

Other in uts at V

GND

CSB = V

B0–B35 1

All other inputs 1

VI = 0, f = 1 MHz 4 pF

VO = 0, f = 1 MHz 8 pF

‡

All typical values are at VCC = 5 V, TA = 25°C.

ICC is measured in the A to B direction.

This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 16)

MIN MAX UNIT

clock

Clock frequency, CLKA or CLKB 50 MHz

Clock cycle time, CLKA or CLKB 20 ns

w(CH)

Pulse duration, CLKA and CLKB high 8 ns

w(CL)

Pulse duration, CLKA and CLKB low 8 ns

su(D)

Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑ 6 ns

su(EN1)

Setup time, ENA to CLKA↑; ENB to CLKB↑ 6 ns Setup time, CSA, W/RA, and MBA to CLKA↑; CSB, W/RB, and MBB to CLKB↑

7.5

su(EN2)

W/RA to CLKA↑

su(RM)

Setup time, RTM and RFM to CLKB↑ 6.5 ns

su(RS)

Setup time, RST low before CLKA↑ or CLKB↑

†

6 ns

su(FS)

Setup time, FS0 and FS1 before RST high 10 ns

su(SD)

‡

Setup time, FS0/SD before CLKA↑ 6 ns

su(SEN)

‡

Setup time, FS1/SEN before CLKA↑ 6 ns

h(D)

Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑ 0 ns

n(EN1)

Hold time, ENA after CLKA↑; ENB after CLKB↑ 0 ns

n(EN2)

Hold time, CSA, W/RA, and MBA after CLKA↑; CSB

, W/RB, and MBB after CLKB↑

0 ns

n(RM)

Hold time, RTM and RFM after CLKB↑ 0 ns

h(RS)

Hold time, RST low after CLKA↑ or CLKB↑

†

6 ns

h(FS)

Hold time, FS0 and FS1 after RST high 0 ns

h(SP)

‡

Hold time, FS1/SEN high after RST high 0 ns

h(SD)

‡

Hold time, FS0/SD after CLKA↑ 0 ns

h(SEN)

‡

Hold time, FS1/SEN after CLKA↑ 0 ns

sk(1)

Skew time between CLKA↑ and CLKB↑ for OR and IR 11 ns

sk(2)

Skew time between CLKA↑ and CLKB↑ for AE and AF 16 ns

†

Requirement to count the clock edge as one of at least four needed to reset a FIFO

‡

Applies only when serial load method is used to program flag offset registers

Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle.

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switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

= 30 pF (see Figures 1 through 16)

PARAMETER

MIN MAX UNIT

max

50 MHz

Access time, CLKB↑ to B0–B35 3 15 ns

pd(C-IR)

Propagation delay time, CLKA↑ to IR 1 10 ns

pd(C-OR)

Propagation delay time, CLKB↑ to OR 1 10 ns

pd(C-AE)

Propagation delay time, CLKB↑ to AE 1 10 ns

pd(C-AF)

Propagation delay time, CLKA↑ to AF 1 10 ns

pd(C-MF)

Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and CLKB↑ to MBF2

low or MBF1 high

0 10 ns

pd(C-MR)

Propagation delay time, CLKA↑ to B0–B35† and CLKB↑ to A0–A35

‡

3 15 ns

pd(M-DV)

Propagation delay time, MBB to B0–B35 valid 3 15 ns

pd(R-F)

Propagation delay time, RST low to AE low and AF high 1 20 ns

Enable time, CSA and W/RA low to A0–A35 active and CSB

low and W/RB high to B0–B35 active

2 13 ns

dis

Disable time, CSA or W/RA high to A0–A35 at high impedance and CSB

high or W/RB low to B0–B35 at high impedance

1 10 ns

†

Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high

‡

Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high

SN54ACT3641 1024 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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PARAMETER MEASUREMENT INFORMATION

1.5 V

1.5 V1.5 V

3 V

GND

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data,

Enable

Input

1.5 V 1.5 V

3 V

GND

High-Level

Input

Low-Level

Input

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

1.5 V 1.5 V

1.5 V1.5 V

3 V

GND

In-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PLZ

≈ 3 V

PHZ

1.5 V 1.5 V

3 V

GND

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PZL

1.5 V

≈ 0 V

1.5 V

PZH

Output Enable

Low-Level

Output

High-Level

Output

(see Note A)

Output Under Test

Load

LOAD CIRCUIT

VOL + 300mV

VOH – 300mV

NOTES: A. Includes probe and jig capacitance

B. t

PZL

and t

PZH

are the same as ten.

C. t

PLZ

and t

PHZ

are the same as t

dis

CONDITIONS FOR LOAD CIRCUIT

PARAMETER I

Load

†

(typical)

PZH

4 mA 8 mA 0 V 20 pF

PZL

4 mA 8 mA 3 V 20 pF

PHZ

4 mA 8 mA 0 V 20 pF

PLZ

4 mA 8 mA 3 V 20 pF

8 mA 4 mA 1.5 V 20 pF

†

Includes probe and test-fixture capacitance

Figure 16. Load Circuit and Voltage Waveforms

SN54ACT3641

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TYPICAL CHARACTERISTICS

I – Supply Current – mA

CC(f)

SUPPLY CURRENT

CLOCK FREQUENCY

clock

– Clock Frequency – MHz

150

100

0 1020304050

200

250

60 70

data

= 1/2 f

clock

TA = 25°C CL = 0 pF

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

Figure 17

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments SN54ACT3641HFP, SNJ54ACT3641HFP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual