TEXAS INSTRUMENTS SN54ABT853 Technical data

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

Typical V

(Output Ground Bounce)

OLP

< 1 V at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

High-Impedance State During Power Up
and Power Down

D

Parity-Error Flag With Parity
Generator/Checker

D

Latch for Storage of Parity-Error Flag

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs

description

The ’ABT853 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT853 transceivers
provide true data at their outputs.

) output indicates whether or not

SN54ABT853 . . . JT OR W PACKAGE

SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE

SN54ABT853 . . . FK PACKAGE

A3
A4
A5

NC

A6
A7
A8

NC – No internal connection

(TOP VIEW)

OEA

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

ERR

10

CLR

11

GND

12

(TOP VIEW)

A2A1OEANCB1

3212827

426

5
6
7
8
9
10
11

12 13

14 15 16 1718

CLR

ERR

GND

24
23
22
21
20
19
18
17
16
15
14
13

NC

V

CC

LE

V

CC

B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE

B2

25
24
23
22
21
20
19

OEB

PARITY

B3
B4
B5
NC
B6
B7
B8

A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with the ERR

flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT853, SN74ABT853

LHX

X

NANAAHNA

HLXLNA

BNANA

§

H

H

XZZ

Z

LLX

X

NANAALNA

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

description (continued)

The SN54ABT853 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT853 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OEB OEA CLR

H L H H NA X X NA NA NC Store error flag
X X L H X X X NA NA H Clear error flag register

NA = not applicable, NC = no change, X = don’t care
†

Summation of high-level inputs includes PARITY along with Bi inputs.

‡

Output states shown assume ERR

§

In this mode, ERR

LE

H H X NC

LH X
X L L Odd
X L H Even L

(when clocked) shows inverted parity of the A bus.

Ai

Σ OF H

Odd

Even

Odd

Even

was previously high.

†

Bi

Σ OF H

Odd

Even

OUTPUTS AND I/Os

A B PARITY

L

H

ERR

H

L

H
H

‡

FUNCTION

A data to B bus and

generate parity

B data to A bus and

check parity

Isolation

(parity check)

A data to B bus and

generate inverted parity

logic symbol

¶

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

¶

LE

CLR
OEA
OEB

A1
A2
A3
A4
A5
A6
A7
A8

13
11

1
14

2
3
4
5
6
7
8
9

LE
CLR

OEA
OEB

1

8

Φ

ERR

PARITY

A Bus B Bus

10

ERR

15

PARITY

23

1

8

22
21
20
19
18
17
16

B1
B2
B3
B4
B5
B6
B7
B8

2

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ERR

L

LHXHPass

HHX

Store

logic diagram (positive logic)

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

A1–A8

OEB

OEA

LE

CLR

2–9

14

1

13
11

8

8x

EN

8

8

MUX

1
1
1

1
G1

8x

EN

8

9

2k

P

8

23–16

15

10

B1–B8

PARITY

ERR

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

ERROR-FLAG FUNCTION TABLE

INPUTS

CLR LE POINT P ERR

H L

L H X X H Clear

†

The state of ERR before changes at CLR, LE, or point P

INTERNAL

TO DEVICE

L

L X L
X
H HH

OUTPUT

PRESTATE

OUTPUT

†

N–1

L

LL

L L
H H

FUNCTION

Sample

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3