SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
Typical V
(Output Ground Bounce)
OLP
< 1 V at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
High-Impedance State During Power Up
and Power Down
D
Parity-Error Flag With Parity
Generator/Checker
D
Latch for Storage of Parity-Error Flag
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
The ’ABT853 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT853 transceivers
provide true data at their outputs.
) output indicates whether or not
SN54ABT853 . . . JT OR W PACKAGE
SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE
SN54ABT853 . . . FK PACKAGE
A3
A4
A5
NC
A6
A7
A8
NC – No internal connection
(TOP VIEW)
OEA
1
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
ERR
10
CLR
11
GND
12
(TOP VIEW)
A2A1OEANCB1
3212827
426
5
6
7
8
9
10
11
12 13
14 15 16 1718
CLR
ERR
GND
24
23
22
21
20
19
18
17
16
15
14
13
NC
V
CC
LE
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE
B2
25
24
23
22
21
20
19
OEB
PARITY
B3
B4
B5
NC
B6
B7
B8
A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with the ERR
flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT853, SN74ABT853
LHX
X
NANAAHNA
HLXLNA
BNANA
§
H
H
XZZ
Z
LLX
X
NANAALNA
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
description (continued)
The SN54ABT853 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT853 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OEB OEA CLR
H L H H NA X X NA NA NC Store error flag
X X L H X X X NA NA H Clear error flag register
NA = not applicable, NC = no change, X = don’t care
†
Summation of high-level inputs includes PARITY along with Bi inputs.
‡
Output states shown assume ERR
§
In this mode, ERR
LE
H H X NC
LH X
X L L Odd
X L H Even L
(when clocked) shows inverted parity of the A bus.
Ai
Σ OF H
Odd
Even
Odd
Even
was previously high.
†
Bi
Σ OF H
Odd
Even
OUTPUTS AND I/Os
A B PARITY
L
H
ERR
H
L
H
H
‡
FUNCTION
A data to B bus and
generate parity
B data to A bus and
check parity
Isolation
(parity check)
A data to B bus and
generate inverted parity
logic symbol
¶
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
¶
LE
CLR
OEA
OEB
A1
A2
A3
A4
A5
A6
A7
A8
13
11
1
14
2
3
4
5
6
7
8
9
LE
CLR
OEA
OEB
1
8
Φ
ERR
PARITY
A Bus B Bus
10
ERR
15
PARITY
23
1
8
22
21
20
19
18
17
16
B1
B2
B3
B4
B5
B6
B7
B8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ERR
L
LHXHPass
HHX
Store
logic diagram (positive logic)
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
A1–A8
OEB
OEA
LE
CLR
2–9
14
1
13
11
8
8x
EN
8
8
MUX
1
1
1
1
G1
8x
EN
8
9
2k
P
8
23–16
15
10
B1–B8
PARITY
ERR
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
ERROR-FLAG FUNCTION TABLE
INPUTS
CLR LE POINT P ERR
H L
L H X X H Clear
†
The state of ERR before changes at CLR, LE, or point P
INTERNAL
TO DEVICE
L
L X L
X
H HH
OUTPUT
PRESTATE
OUTPUT
†
N–1
L
LL
L L
H H
FUNCTION
Sample
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
error-flag waveforms
OEB
H
L
OEA
Bi + PARITY
LE
CLR
ERR
Pass Store Sample
Clear
H
L
Even
Odd
H
L
H
L
H
L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
: SN54ABT853 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74ABT853 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
recommended operating conditions (see Note 3)
SN54ABT853 SN74ABT853
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
OH
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output voltage ERR 5.5 5.5 V
High-level output current Except ERR –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT853, SN74ABT853
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
V
V
V
GND
A
,
V
CC
5.5 V,
||
D
,
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT853 SN74ABT853
MIN TYP†MAX MIN MAX MIN MAX
V
IK
All outputs
OH
except ERR
V
hys
I
OH
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
The parameters I
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This data sheet limit can vary among suppliers.
||
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
ERR VCC = 4.5 V, VOH = 5.5 V 50 50 50 µA
Control inputs
A or B ports
‡
‡
§
§
¶
A or B ports
ata inputs
CC
Control inputs
Control inputs VI = 2.5 V or 0.5 V 4.5 pF
i
A or B ports VO = 2.5 V or 0.5 V 10.5 pF
io
OZH
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
= 5.5 V,
CC
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –200
V
= 5.5 V
IO = 0,
VI = VCC or GND
VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 24 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
=
or
I
CC
= X
= X
Outputs high 50 50 50 µA
Outputs high 1 250 450 250 µA
Outputs low 24 38 38 38 mA
Outputs disabled 0.5 250 450 250 µA
Outputs enabled 1.5 1.5 1.5 mA
Outputs disabled 50 50 50 µA
±1 ±1 ±1
±100 ±100 ±100
±50 ±50 ±50 µA
±50 ±50 ±50 µA
#
–50 –200#–50 –200
1.5 1.5 1.5 mA
µ
#
mA
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
twPulse duration
ns
tsuSetup time
ns
thHold time
ns
(INPUT)
(OUTPUT)
A or B
B or A
ns
A
PARITY
ns
OE
PARITY
ns
LE
ERR
ns
B or PARITY
ERR
ns
OE
A or B or PARITY
ns
OE
A or B or PARITY
ns
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
LE high or low 3.5 3.5 3.5
CLR low 4 4 4
p
†
This data sheet limit can vary among suppliers.
B or PARITY before LE↓ 9.4
CLR before LE↓ 2 2 2
B or PARITY after LE↓ 0 0 0
CLR after LE↓ 3 3 3
†
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
†
This data sheet limit can vary among suppliers.
PLZ
FROM
CLR ERR
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1.2 4.8 1.2 6.4 1.2 5.3
1 4.8
2.1 9.5 2.1 13.3 2.1 11.2
2.5 9.7 2.5 11 2.5 11
1.8 8.5 1.8 13.6 1.8 10.5
2.3 8.6 2.3 11.7 2.3 10
1 5.5 1 6.3 1 6.2 ns
1.8 5.1 1.8 6.1 1.8 6
†
1
2 10.1 2 11.8 2 11.7
†
2.2
1 5.8
†
1.5
†
1.8
†
2.1
SN54ABT853 SN74ABT853
10.2 9.4
SN54ABT853 SN74ABT853
†
1 5.4 1 5.3
5.8 1
11.5 2.2†12.9 2.2†12.8
5.8 1.5
7.3 1.8
7.2 2.1
†
†
1 8.8 1 6.7
†
†
†
6.7 1 6.6
9.8 1.5
9.5 1.8
8.2 2.1
†
†
6.7
†
7.9
†
8.1
UNIT
UNIT
†
†
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7
SN54ABT853, SN74ABT853
.
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
7 V
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
LOAD CIRCUIT
t
w
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHL
1.5 V
t
1.5 V1.5 V
PLH
3 V
0 V
V
V
V
V
OH
OL
OH
OL
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
t
h
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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