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SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
Th
e'
ABT657A transceivers have eight
noninverting buffers with parity-generator/
checker circuits and control signals. The
transmit/receive (T/R
direction of data flow. When T/R is high, data flows
from the A port to the B port (transmit mode); when
T/R is low, data flows from the B port to the A port
(receive mode). When the output-enable (OE)
input is high, both the A and B ports are in the
high-impedance state.
Odd or even parity is selected by a logic high or
low level on the ODD/EVEN
the parity-bit value; it is an output from the parity
generator/checker in the transmit mode and an
input to the parity generator/checker in the receive
mode.
) input determines the
input. P ARITY carries
SN54ABT657A . . . JT PACKAGE
SN74ABT657A . . . DW OR NT PACKAGE
ODD/EVEN
SN54ABT657A . . . FK PACKAGE
ODD/EVEN
ERR
PARITY
NC
B8
B7
B6
NC – No internal connection
(TOP VIEW)
T/R
1
A1
2
A2
3
A3
4
A4
5
A5
6
V
7
CC
A6
8
A7
9
A8
10
11
ERR
12
(TOP VIEW)
A8A7A6
4 26
5
6
7
8
9
10
11
12 13
B5
NC
3212827
14
15 16 17 18
NC
GND
GND
OE
24
B1
23
B2
22
B3
21
B4
20
GND
19
GND
18
B5
17
B6
16
B7
15
B8
14
PARITY
13
CC
A5
V
B4B3B2
A4
25
24
23
22
21
20
19
A3
A2
A1
NC
T/R
OE
B1
In the transmit mode, after the A bus is polled to determine the number of high bits, P ARITY is set to the logic
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low
(even parity selected) and there are five high bits on the A bus, P ARITY is set to the logic high level so that an
even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN
is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is
low, indicating a parity error.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT657A, SN74ABT657A
0, 2, 4, 6, 8
1, 3, 5, 7
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT657A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT657A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
NUMBER OF A OR B
INPUTS THAT ARE HIGH
Don’t care H X X Z Z Z
INPUTS
OE T/R ODD/EVEN
L H H
L HL
L LH
L LH
L LL
L LL
L H H
L HL
L LH
L LH
L LL
L LL
I/O
PARITY
H
L
H
L
H
L
L
H
H
L
H
L
OUTPUTS
ERR OUTPUT MODE
Z Transmit
Z Transmit
H Receive
L Receive
L Receive
H Receive
Z Transmit
Z Transmit
L Receive
H Receive
H Receive
L Receive
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
logic symbol
†
OE
T/R
ODD/EVEN
A1
A2
A3
A4
A5
A6
A7
A8
24
1
11
2
3
4
5
6
8
9
10
G3
3 EN1/3G5 [REC]
3 EN2 [XMIT]
N4
11
Z11 2
11
12
13
14
15
16
17
18
2 k
4, 2
4, 1
23
B1
22
B2
21
B3
20
B4
17
B5
16
B6
15
B7
14
B8
13
PARITY
5
12
ERR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
logic diagram (positive logic)
1
T/R
24
OE
A1
2
23
B1
A2
A3
A4
A5
A6
A7
A8
3
4
5
6
8
9
10
22
B2
21
B3
20
B4
17
B5
16
B6
15
B7
14
B8
ODD/EVEN
Pin numbers shown are for the DW, JT, and NT packages.
4
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
12
PARITY
ERR
UNIT
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT657A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABT657A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(see Note 2): DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT657A SN74ABT657A
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
∆t/∆V
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT657A, SN74ABT657A
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
A
V
CC
Data inputs
,
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT657A SN74ABT657A
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
The parameters I
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1
A or B ports VCC = 2.1 V to 5.5 V , VI = VCC or GND ±20 ±20 ±20
‡
‡
§
§
¶
p
#
CC
Control inputs
Control inputs VI = 2.5 V or 0.5 V 4 pF
i
A or B ports VO = 2.5 V or 0.5 V 10 pF
io
OZH
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V,
= X
OE
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V,
OE
= X
VCC = 2.1 V to 5.5 V, VO = 2.7 V,
OE
≥ 2 V
VCC = 2.1 V to 5.5 V, VO = 0.5 V,
OE
≥ 2 V
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
±50 ±50 ±50 µA
±50 ±50 ±50 µA
10 10 10 µA
–10 –10 –10 µA
Outputs high 50 50 50 µA
Outputs high 250 250 250 µA
Outputs low 40 40 40 mA
Outputs disabled 250 250 250 µA
Outputs enabled 1.5 1.5 1.5
Outputs disabled 0.25 0.25 0.25 mA
1.5 1.5 1.5
µ
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
A or B
B or A
ns
A
PARITY
ns
ODD/EVEN
PARITY, ERR
ns
B
ERR
ns
PARITY
ERR
ns
OE
A, B, PARITY
ns
OE
ERR
ns
OE
,, ,
ns
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
TO
A, B, PARITY, or
ERR
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1 3.2 4.2 1 5 1 4.6
1 2.8 3.8 1 4.5 1 4.3
1.8 4.8 6.3 1.8 8.5 1.8 8.1
2.3 4.9 6.4 2.3 8.1 2.3 7.7
1.1 3.3 4.2 1.1 5.3 1.1 4.9
1.3 3.4 4.5 1.3 5.1 1.3 4.9
1.6 4.7 6.5 1.6 8.4 1.6 7.9
2.1 4.9 6.9 2.1 8 2.1 7.8
2 4.8 6.3 2 8.1 2 7.7
2.1 4.9 6.7 2.1 8 2.1 7.5
1.4 4 5.4 1.4 6.8 1.4 6.5
1.7 4.1 5.8 1.7 6.7 1.7 6.5
1.8 4.1 5.4 1.8 6.9 1.8 6.6
3.3 6.2 7.6 3.3 9.7 3.3 9.2
2.4 4.2 5.6 2.4 6.3 2.4 6.2
1.8 4.2 6.2 1.8 8.9 1.8 7.8
SN54ABT657A SN74ABT657A
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
7 V
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
LOAD CIRCUIT
t
w
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V1.5 V
t
PHL
1.5 V
t
PLH
3 V
0 V
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
t
h
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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