TEXAS INSTRUMENTS SN54ABT657A Technical data

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SN54ABT657A, SN74ABT657A

OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS

AND 3-STATE OUTPUTS

SCBS192E – JANUARY 1991 – REVISED JUNE 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs

description

Th

e'

ABT657A transceivers have eight
noninverting buffers with parity-generator/
checker circuits and control signals. The
transmit/receive (T/R
direction of data flow. When T/R is high, data flows
from the A port to the B port (transmit mode); when
T/R is low, data flows from the B port to the A port
(receive mode). When the output-enable (OE)
input is high, both the A and B ports are in the
high-impedance state.

Odd or even parity is selected by a logic high or
low level on the ODD/EVEN
the parity-bit value; it is an output from the parity
generator/checker in the transmit mode and an
input to the parity generator/checker in the receive
mode.

) input determines the

input. P ARITY carries

SN54ABT657A . . . JT PACKAGE

SN74ABT657A . . . DW OR NT PACKAGE

ODD/EVEN

SN54ABT657A . . . FK PACKAGE

ODD/EVEN

ERR

PARITY

NC

B8
B7
B6

NC – No internal connection

(TOP VIEW)

T/R

1

A1

2

A2

3

A3

4

A4

5

A5

6

V

7

CC

A6

8

A7

9

A8

10
11

ERR

12

(TOP VIEW)

A8A7A6

4 26

5
6
7
8
9
10
11

12 13

B5

NC

3212827

14

15 16 17 18

NC

GND

GND

OE

24

B1

23

B2

22

B3

21

B4

20

GND

19

GND

18

B5

17

B6

16

B7

15

B8

14

PARITY

13

CC

A5

V

B4B3B2

A4

25
24
23
22
21
20
19

A3
A2
A1
NC
T/R
OE
B1

In the transmit mode, after the A bus is polled to determine the number of high bits, P ARITY is set to the logic
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low
(even parity selected) and there are five high bits on the A bus, P ARITY is set to the logic high level so that an
even number of the nine total bits (eight A-bus bits plus parity bit) are high.

In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN

is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is

low, indicating a parity error.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT657A, SN74ABT657A

0, 2, 4, 6, 8

1, 3, 5, 7

OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS

SCBS192E – JANUARY 1991 – REVISED JUNE 1997

description (continued)

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT657A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT657A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

NUMBER OF A OR B

INPUTS THAT ARE HIGH

Don’t care H X X Z Z Z

INPUTS

OE T/R ODD/EVEN

L H H
L HL
L LH
L LH
L LL
L LL
L H H
L HL
L LH
L LH
L LL
L LL

I/O

PARITY

H

L

H

L

H

L

L
H
H

L
H

L

OUTPUTS

ERR OUTPUT MODE

Z Transmit
Z Transmit
H Receive
L Receive
L Receive
H Receive
Z Transmit
Z Transmit
L Receive
H Receive
H Receive
L Receive

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT657A, SN74ABT657A

OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS

AND 3-STATE OUTPUTS

SCBS192E – JANUARY 1991 – REVISED JUNE 1997

logic symbol

†

OE

T/R

ODD/EVEN

A1

A2
A3
A4
A5
A6
A7
A8

24
1

11

2

3
4
5
6
8
9
10

G3
3 EN1/3G5 [REC]
3 EN2 [XMIT]
N4

11

Z11 2

11
12
13
14
15
16
17
18

2 k

4, 2

4, 1

23

B1

22

B2

21

B3

20

B4

17

B5

16

B6

15

B7

14

B8

13

PARITY

5

12

ERR

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, and NT packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3