TEXAS INSTRUMENTS SN54ABT534 Technical data

SN54ABT534, SN74ABT534A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package

description

These 8-bit flip-flops with 3-state outputs are
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.

The eight flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK), the Q
the logic levels set up at the data (D) inputs.

outputs are set to the complement of

SN54ABT534 ...J OR W PACKAGE

SN74ABT534A . . . DB, DW, N, OR PW PACKAGE

SN54ABT534 . . . FK PACKAGE

2D
2Q
3Q
3D
4D

(TOP VIEW)

OE

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

(TOP VIEW)

1D1QOE

3212019

4
5
6
7
8

9

4Q

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

CC

V

10 11 12 13

5Q

CLK

GND

V

CC

8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK

8Q

18
17
16
15
14

5D

8D
7D
7Q
6Q
6D

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.

OE does not affect the internal operations of the flip-flop. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.

T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT534 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT534A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54ABT534, SN74ABT534A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

FUNCTION TABLE

(each flip-flop)

INPUTS

OE CLK D

L ↑ H L
L ↑ LH
L H or L X Q

H X X Z

OUTPUT

Q

0

logic symbol

1

OE

11

CLK

3

1D

4

2D

7

3D

8

4D

13

5D

14

6D

17

7D

18

8D

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

†

EN

C1

12
15
16
19

2

1Q

5

2Q

6

3Q

9

4Q
5Q
6Q

7Q
8Q

1D

logic diagram (positive logic)

1

OE

11

CLK

C1

1D

1D

3

To Seven Other Channels

2

1Q

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I

Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

: SN54ABT534 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

SN74ABT534A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

4.5 V

V

V

I

V

CC

GND

SN54ABT534, SN74ABT534A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

recommended operating conditions (see Note 3)

SN54ABT534 SN74ABT534A

MAX MIN MAX

V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This data sheet limit may vary among suppliers.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

A

TA = 25°C SN54ABT534 SN74ABT534A

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

OL

V

hys

I

I

I

OZH

I

OZL

I

off

I

CEX

I

O

I

CC

∆I
C

i

C

o

§

CC

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA
VCC = 5 V, IOH = –3 mA

or

IOH = –24 mA
IOH = –32 mA
IOL = 48 mA
IOL = 64 mA

Outputs high
Outputs low
Outputs disabled

= 4.5

CC

=

CC

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 5.5 V, VO = 2.7 V 10
VCC = 5.5 V, VO = 0.5 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180

VCC = 5.5 V, IO = 0,

=

VCC = 5.5 V, One input at 3.4 V,

¶

Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 6.5 pF

2.5 2.5 2.5
3 3 3
2 2

2* 2

0.55 0.55

0.55* 0.55

100 mV

‡
‡

‡

–50 –180

1 250 250 250

24 30 30 30

0.5 250 250 250

1.5 1.5 1.5 mA

10

–10

CC

‡
‡

‡

–50 –180

0 V

10

–10

CC

V

‡

µA

‡

µA

‡

mA

µA

mA

µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ABT534, SN74ABT534A

CLK

Q

ns

OE

Q

ns

OE

Q

ns

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

SN54ABT534

VCC = 5 V,

f

clock

t

w

t

su

t

h

TA = 25°C
MIN MAX

Clock frequency 125 125 MHz
Pulse duration CLK high or low 3.5 3.5 ns
Setup time, data before CLK↑

Hold time, data after CLK↑ High or low 1.6 1.6 ns

High or low 1.6 1.6 ns

MIN MAX

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

SN74ABT534A

VCC = 5 V,

f

clock

t

w

t

su

t

h

†

This data sheet limit may vary among suppliers.

Clock frequency 125 125 MHz
Pulse duration CLK high or low 3.5 3.5 ns
Setup time, data before CLK↑

Hold time, data after CLK↑ High or low 2

TA = 25°C
MIN MAX

High or low 1.6 1.6 ns

†

MIN MAX

†

2

UNIT

UNIT

ns

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

TO

(OUTPUT)

SN54ABT534

VCC = 5 V,

TA = 25°C

MIN TYP MAX

125 175 125 MHz

2.6 4.5 6.1 2.6 7

3.4 5.5 6.7 3.4 7.9
1 3.4 5.2 1 5.8

2.6 4 5.8 2.6 7

2.4 4.7 6.6 2.4 7.6

2.3 3.8 5.8 2.3 6.8

MIN MAX

UNIT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLK

Q

ns

OE

Q

ns

OE

Q

ns

SN54ABT534, SN74ABT534A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

TO

(OUTPUT)

SN74ABT534A

VCC = 5 V,

TA = 25°C

MIN TYP MAX

125 175 125 MHz

2.6 4.5 5.9 2.6 6.7

3.4 5.5 6.7 3.4 7.6
1 3.4 4.2 1 5

2.6 4 5.8 2.6 6.8

2.4 4.7 6.6 2.4 7.3

2.3 3.8 5.8 2.3 6.5

MIN MAX

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54ABT534, SN74ABT534A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS187F – JANUARY 1991 – REVISED JANUARY 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

1.5 V1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

3 V

0 V

V

V

V

V

7 V

GND

OH

OL

OH

OL

Open

3 V

0 V

Timing Input

Data Input

Output

Output

Control

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-9314701Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9314701QRA ACTIVE CDIP J 20 1 TBD A42 SNPB N /A for Pkg Type
5962-9314701QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type

SN74ABT534ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI

SN74ABT534ADBR ACTIVE SSOP DB 20 2000 Green (RoHS &

SN74ABT534ADBRE4 ACTIVE SSOP DB 20 2000 Green(RoHS &

SN74ABT534ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &

SN74ABT534ADW ACTIVE SOIC DW 20 25 Green (RoHS &

SN74ABT534ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS &

SN74ABT534ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

SN74ABT534ADWR ACTIVE SOIC DW 20 2000 Green (RoHS &

SN74ABT534ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS&

SN74ABT534ADWRG4 ACTIVE SOIC DW 20 2000 Green(RoHS&

SN74ABT534AN ACTIVE PDIP N 20 20 Pb-Free

SN74ABT534ANE4 ACTIVE PDIP N 20 20 Pb-Free

SN74ABT534ANSR ACTIVE SO NS 20 2000 Green (RoHS &

SN74ABT534ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS &

SN74ABT534ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS &

SN74ABT534APW ACTIVE TSSOP PW 20 70 Green (RoHS &

SN74ABT534APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS &

SN74ABT534APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

SN74ABT534APWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI

SN74ABT534APWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

SN74ABT534APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

SN74ABT534APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS&

SNJ54ABT534FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A forPkg Type

SNJ54ABT534J ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type

SNJ54ABT534W ACTIVE CFP W 20 1 TBD A42 N / A for PkgType

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

9-Oct-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(1)

The marketing status values are defined asfollows:

9-Oct-2007

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the devicewill be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but isnot in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production ofthe device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information andadditional product content details.

TBD: The Pb-Free/Green conversion plan has notbeen defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products aresuitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

SN74ABT534ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74ABT534ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

SN74ABT534APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Type

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74ABT534ADBR SSOP DB 20 2000 346.0 346.0 33.0
SN74ABT534ADWR SOIC DW 20 2000 346.0 346.0 41.0
SN74ABT534APWR TSSOP PW 20 2000 346.0 346.0 33.0

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38
0,22

15

14

A

0,05 MIN

0,15

5,60
5,00

M

8,20
7,40

Seating Plane

0,10

0,25
0,09

0°–ā8°

Gage Plane

0,25

0,95
0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

14

6,50

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

19

20

21

22

23

24

25

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342
(8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358

(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

(10,31)

(12,58)

(12,58)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307

(7,80)

0.406

0.495

0.495

0.850

(21,6)

1.047

(26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358

(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858

(21,8)

1.063

(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30

0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

6,60
6,20

14

0,10

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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