Texas Instruments SN54ABT3614HFP Datasheet

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

Two Independent 64 × 36 Clocked FIFOs Buffering Data in Opposite Directions

Mailbox-Bypass Register for Each FIFO

Dynamic Port-B Bus Sizing of 36 Bits (Long Word), 18 Bits (Word), and 9 Bits (Byte)

Selection of Big- or Little-Endian Format for Word and Byte Bus Sizes

Three Modes of Byte-Order Swapping on Port B

Almost-Full and Almost-Empty Flags

Microprocessor Interface Control Logic

EFA, FFA, AEA, and AFA Flags Synchronized by CLKA

description

SN54ABT3614

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

EFB, FFB, AEB, and AFB Flags Synchronized by CLKB

Passive Parity Checking on Each Port

Parity Generation Can Be Selected for Each Port

Low-Power Advanced BiCMOS Technology

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 12 ns

Released as DSCC SMD (Standard Microcircuit Drawing) 5962-9560901QYA and 5962-9560901NXD

Package Options Include 132-Pin Ceramic Quad Flat (HFP) and 120-Pin Plastic Quad Flat (PCB) Packages

The SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory . It supports clock frequencies up to 50 MHz and has read-access times as fast as 12 ns. Two independent 64 × 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory . FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port.

The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface.

The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its array . The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads data from its array.

The SN54ABT3614 is characterized for operation over the full military temperature range of –55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54ABT3614 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

HFP PACKAGE

(TOP VIEW)

GND

AEA

EFA

A0 A1 A2

GND

A3 A4 A5 A6

A7 A8 A9

GND

A10

A11

A12 A13 A14

GND

A15 A16 A17 A18 A19 A20

GND

A21 A22 A23

CLKA

W/RA

PGA

PEFA

GND

MBF2

MBA

FS1

FS0

ODD/EVEN

RST

GNDBESW1

131

130

SW0

129

SIZ1

SIZ0

128

127

MBF1

GND

126

125

CSA

AFA

FFA

ENA

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

51 52 5354 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 7778 79 80 81 8283

PGB

PEFB

124

123

122

W/RB

CLKB

120

121

ENB

119

CSB

118

FFB

117

AFB

116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6 V

B7 B8 B9 GND B10 B11 V

B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23

NC – No internal connection

A24

A25

A26

A27CCA29

GND

A30

A31

A32

A33

A34

A28

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GND

A35

GND

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

GND

B25

B24

SN54ABT3614

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

PCB PACKAGE

(TOP VIEW)

A23 A22 A21

GND

A20 A19 A18 A17 A16 A15 A14 A13 A12

A11

A10

GND

A9 A8 A7

A6 A5 A4 A3

GND

A2 A1 A0

EFA

AEA

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

A24

120

A25

119

A26

118

117

A27

116

A28

115

A29

114

GND

A30

112

113

A31

111

A32

110

A33

109

A34

108

A35

107

GND

B35

105

106

B34

104

B33

103

B32

102

B31

101

B30

100

GND

B29

B28

B27

B26

B25

B24

B23

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 V

B6 B5 B4 B3 GND B2 B1 B0 EFB AEB AFB

FFA

AFA

CSA

ENA

CLKA

W/RA

PGA

PEFA

MBA

MBF2

FS1

FS0

RST

GND

SW1

SW0

SIZ1

SIZ0

PEFB

MBF1

PGB

W/RB

CLKB

ENB

FFB

CSB

ODD/EVEN

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SGBS308F – AUGUST 1995 – REVISED MA Y 2000

functional block diagram

CLKA

CSA

W/RA

ENA

MBA

RST

ODD/

EVEN

Device

Control

Port-A

Control

Logic

64 × 36

SRAM

Input Register

Write

Pointer

Mail1

Read

Pointer

Gen/Check

Parity

Generation

Parity

Output Register

Byte Swapping

Bus Matching and

MBF1 PEFB

PGB

FFA

AFA

FS0 FS1

A0–A35

EFA

AEA

PGA

PEFA MBF2

Status-Flag

Programmable-Flag

FIFO2

Parity

Output Register

Parity

Gen/Check

Logic

Offset Register

Status-Flag

Logic

Read

Pointer

64 × 36

SRAM

Generation

Write

Pointer

Mail2

FIFO1

Byte Swapping

Bus Matching and

Input Register

Port-B

Control

Logic

EFB AEB

B0–B35

FFB AFB

CLKB CSB

W/RB ENB BE SIZ0

SIZ1 SW0

SW1

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SN54ABT3614

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

Terminal Functions

TERMINAL

NAME

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A. AEA

AEB

AFA

AFB B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B. BE I

CLKA I

CLKB I

CSA I

CSB I

EFA

EFB

ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FFA

FFB

FS1, FS0 I

MBA I

MBF1 O

MBF2 O

I/O DESCRIPTION

(port A)

(port B)

(port A)

(port B)

(port A)

(port B)

(port A)

(port B)

Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words in FIFO2 is less than or equal to value in offset register X.

Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words in FIFO1 is less than or equal to value in offset register X.

Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty locations in FIFO1 is less than or equal to the value in offset register X.

Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty locations in FIFO2 is less than or equal to the value in offset register X.

Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the most-significant bytes on B0–B35 for use, and a high selects the least-significant bytes.

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA CLKA.

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data-port sizing operations are also synchronous to the low-to-high transition of CLKB. EFB CLKB.

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0–A35 outputs are in the high-impedance state when CSA

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0–B35 outputs are in the high-impedance state when CSB

Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EF A is low , FIFO2 is empty and

reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA forced low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty FIFO2 memory.

Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and

reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO1 memory.

Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FF A is low , FIFO1 is full and writes

to its memory are disabled. FFA transition of CLKA after reset.

Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes

to its memory are disabled. FFB transition of CLKB after reset.

Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the almost-empty flag and almost-full flag offset.

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output register data for output.

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites to the mail1 register are inhibited while MBF1 port-B read is selected and both SIZ1 and SIZ0 are high. MBF1

Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites to the mail2 register are inhibited while MBF2 port-A read is selected and MBA is high. MBF2

is forced low when the device is reset and is set high by the second low-to-high

, FFA, AFA, and AEA are synchronized to the low-to-high transition of

, FFB, AFB, and AEB are synchronized to the low-to-high transition of

is low. MBF1 is set high by a low-to-high transition of CLKB when a

is low. MBF2 is set high by a low-to-high transition of CLKA when a

is set high when the device is reset.

is high.

is high. EFA is

is high. EFB is

is set high when the device is reset.

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SN54ABT3614 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

Terminal Functions (Continued)

TERMINAL

NAME

ODD/EVEN I

PEFA

PEFB

PGA I

PGB I

RST I

SIZ0, SIZ1

SW0, SW1

W/RA I

W/RB I

(port A)

(port B)

I/O DESCRIPTION

Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when ODD/EVEN for a read operation.

Port-A parity-error flag. When any byte applied to terminals A0–A35 fails parity, PEFA is low. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of ODD/EVEN

The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/R high, and PGA high, the PEFA

Port-B parity-error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by

the state of ODD/EVEN The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/R and SIZ0 high, and PGB high, the PEFB

Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity generated is selected by the state of ODD/EVEN The generated parity bits are output in the most-significant bit of each byte.

Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated is selected by the state of ODD/EVEN The generated parity bits are output in the most-significant bit of each byte.

Reset. T o reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST low-to-high transition of RST flag offset.

Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the

following low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.

Port-B byte-swap selects. At the beginning of each long-word transfer, one of four modes of byte-order swapping

is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection.

Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R

Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/R

is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled

flag is forced high, regardless of the state of the A0–A35 inputs.

flag is forced high, regardless of the state of the B0–B35 inputs.

. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.

. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.

is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low. The

latches the status of the FS1 and FS0 inputs to select almost-full flag and almost-empty

A low, MBA

B low, SIZ1

A is high.

B is high.

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SN54ABT3614

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

detailed description

reset

The SN54ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the empty flags (EFA A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after power up before data is written to its memory.

A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

, EFB) low, the almost-empty flags (AEA, AEB) low , and the almost-full flags (AF A, AFB) high.

Table 1. Flag Programming

FS1 FS0

H H ↑ 16 H L ↑ 12

L H ↑ 8 L L ↑ 4

RST

ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X)

FIFO write/read operation

The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA

) and the port-A write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0–A35 outputs are active when both CSA

and W/RA are low. Data is loaded into FIFO1 from the A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FFA is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

H X X X X In high-impedance state None

L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO1 write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

A0–A35 OUTPUTS PORT FUNCTION

The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0–B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the B0–B35 inputs on a low-to-high transition of CLKB when CSB

is low, W/RB is high, ENB is high, FFB is high, and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).

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SN54ABT3614

WORDS IN FIFO1

†

WORDS IN FIFO2

†

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB SIZ1, SIZ0 CLKB

H X X X X In high-impedance state None

L H L X X In high-impedance state None L H H One, both low ↑ In high-impedance state FIFO2 write L H H Both high ↑ In high-impedance state Mail2 write L L L One, both low X Active, FIFO1 output register None L L H One, both low ↑ Active, FIFO1 output register FIFO1 read L L L Both high X Active, mail1 register None L L H Both high ↑ Active, mail1 register Mail1 read (set MBF1 high)

B0–B35 OUTPUTS PORT FUNCTION

The setup- and hold-time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read selects (W/R

A, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select can change states during the setup- and hold-time window of the cycle.

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another (see the application report

High-Performance FIFO Memories Data Book

Metastability Performance of Clocked FIFOs

in the 1996

, literature number SCAD003). EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.

Table 4. FIFO1 Flag Operation

NUMBER OF 36-BIT

0 L L H H

1 to X H L H H

(X + 1) to [64 – (X + 1)] H H H H

(64 – X) to 63 H H L H

64 H H L L

†

X is the value in the almost-empty flag and almost-full flag offset register .

SYNCHRONIZED

TO CLKB

EFB AEB AFA FFA

SYNCHRONIZED

TO CLKA

Table 5. FIFO2 Flag Operation

NUMBER OF 36-BIT

0 L L H H

1 to X H L H H

(X + 1) to [64 – (X + 1)] H H H H

(64 – X) to 63 H H L H

64 H H L L

†

X is the value in the almost-empty flag and almost-full flag offset register .

SYNCHRONIZED

TO CLKA

EFA AEA AFB FFB

SYNCHRONIZED

TO CLKB

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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

empty flags (EFA, EFB)

The empty flag of a FIFO is synchronized to the port clock that reads data from its array . When the empty flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when the fourth byte or second word of the last long word is read.

The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty , empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty-flag synchronizing clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t be the first synchronization cycle (see Figures 13 and 14).

full flags (FFA, FFB)

The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is low and attempted writes to the FIFO are ignored.

, or greater, after the write. Otherwise, the subsequent clock cycle can

sk1

Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full–1, or full–2. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full-flag synchronizing clock; therefore, a full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data can be written in the following clock cycle.

A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t first synchronization cycle (see Figures 15 and 16).

, or greater, after the read. Otherwise, the subsequent clock cycle can be the

sk1

almost-empty flags (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty , almost empty+1, or almost empty+2. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see fewer long words in memory and is high when the FIFO contains (X + 1) or more long words.

Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 17 and 18).

reset

). An almost-empty flag is low when the FIFO contains X or

sk2

, or greater,

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SGBS308F – AUGUST 1995 – REVISED MA Y 2000

almost-full flags (AFA, AFB)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array . The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words.

Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64 – (X + 1)]. An almost-full flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to [64 – (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization cycle if it occurs at time t [64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 19 and 20).

mailbox registers

Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by CSA writes B0–B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0 and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low . Attempted writes to a mail register are ignored while the mail flag is low.

reset

). An almost-full flag is low when the FIFO contains (64 – X) or more long words in

, or greater, after the read that reduces the number of long words in memory to

sk2

, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB

When the port-A data outputs (A0–A35) are active, the data on the bus comes from the FIFO2 output register when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0–B35) are active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high by a rising CLKB edge when a port-B read is selected by CSB (SIZ1 and SIZ0) inputs are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only when new data is written to the register.

dynamic bus sizing

The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths.

The levels applied to SIZ0 and SIZ1 and the big-endian select (BE) input are stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to Figure 1.

Only 36-bit long-word data is written to or read from the two FIFO memories on the SN54ABT3614. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. Port-B bus sizing does not apply to mail-register operations.

, W/RB, and ENB and both port-B bus-size select

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A35 A27 A26 A18 A17 A9 A8 A0

BYTE ORDER ON PORT A:

XLL

LLH

HLH

SIZ1 SIZ0

ABCD

B35 B27 B26 B18 B17 B9 B8 B0

ABCD

(a) LONG WORD SIZE

B35 B27 B26 B18 B17 B9 B8 B0

(b) WORD SIZE – BIG ENDIAN

B35 B27 B26 B18 B17 B9 B8 B0

Write to FIFO1/Read From FIFO2

Read From FIFO1/Write to FIFO2

1st: Read From FIFO1/Write to FIFO2

2nd: Read From FIFO1/Write to FIFO2

1st: Read From FIFO1/Write to FIFO2

BE SIZ1 SIZ0

LHL

B35 B27 B26 B18 B17 B9 B8 B0

(d) BYTE SIZE – BIG ENDIAN

Figure 1. Dynamic Bus Sizing

2nd: Read From FIFO1/Write to FIFO2

1st: Read From FIFO1/Write to FIFO2

2nd: Read From FIFO1/Write to FIFO2

3rd: Read From FIFO1/Write to FIFO2

4th: Read From FIFO1/Write to FIFO2

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SN54ABT3614 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

B35 B27 B26 B18 B17 B9 B8 B0

HHL

bus-matching FIFO1 reads

Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1.

SIZ1 SIZ0

B35 B27 B26 B18 B17 B9 B8 B0

(e) BYTE SIZE – LITTLE ENDIAN

Figure 1. Dynamic Bus Sizing (Continued)

1st: Read From FIFO1/Write to FIFO2

2nd: Read From FIFO1/Write to FIFO2

3rd: Read From FIFO1/Write to FIFO2

4th: Read From FIFO1/Write to FIFO2

Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1 read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread long-word data.

When reading data from FIFO1 in byte or word format, the unused B0–B35 outputs remain inactive but static with the unused FIFO1 output register bits holding the last data value to decrease power consumption.

bus-matching FIFO2 writes

Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes, with a long-word bus size, immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner shown in Figure 1.

Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.

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SN54ABT3614

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MA Y 2000

port-B mail-register access

In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed immediately and any bus-sizing operation that can be underway is unaffected by the the mail-register access. After the mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE

CLKB

_Q.

MUX

SIZ0 SIZ1

Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register

byte swapping

The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is rearranged within the long word, but the bit order within the bytes remains constant.

Byte arrangement is chosen by the port-B swap select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first word of a new long-word read from FIFO1 or written to FIFO2 is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for a FIFO1 read rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1. Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes load the data according to Figure 1, then swap the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM.

SIZ0_Q SIZ1_Q

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Texas Instruments SN54ABT3614HFP Datasheet

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