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SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Impedance State During Power Up
and Power Down
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16843 18-bit bus-interface D-type
latches are designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The ’ABT16843 can be used as two 9-bit latches
or one 18-bit latch. The 18 latches are transparent
D-type latches. The device provides true data at
its outputs.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are in the
high-impedance state during power up and power
down. The outputs remain in the high-impedance
state while the device is powered down. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
SN54ABT16843 ...WD PACKAGE
SN74ABT16843 . . . DGG OR DL PACKAGE
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1LE
1PRE
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2PRE
2LE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
description (continued)
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16843 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16843 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit latch)
INPUTS
PRE CLR OE
L X L X X H
H LLXX L
H HLHL L
H HLHH H
H HLLX Q
X X H X X Z
LE D
should be tied to VCC through a pullup resistor;
OUTPUT
Q
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
2
1OE
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
1PRE
1CLR
1LE
1D1
2OE
2PRE
2CLR
55
1
56
54
27
30
28
S2
C1
1D
R
To Eight Other Channels
3
1Q1
2LE
2D1
29
42
S2
C1
1D
R
To Eight Other Channels
15
2Q1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT16843, SN74ABT16843
UNIT
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16843 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θJA (see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABT16843 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT16843 SN74ABT16843
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
V
I
V
CC
GND
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16843 SN74ABT16843
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
I
I
‡
I
OZPU
‡
I
OZPD
I
OZH
I
OZL
I
off
I
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
CEX
§
I
O
Outputs high
I
Outputs low
CC
Outputs disabled
¶
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 0 to 5.5 V,
VI = VCC or GND
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = 0,
=
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 8 pF
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
±1 ±1 ±1 µA
= X
= X
≥ 2 V
≥ 2 V
or
±50 ±50 ±50 µA
±50 ±50 ±50 µA
10 10 10 µA
–10 –10 –10 µA
0.5 0.5 0.5
85 85 85
0.5 0.5 0.5
1.5 1.5 1.5 mA
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT16843, SN74ABT16843
tsuSetup time, data before LE↓
ns
thHold time, data after LE↓
ns
(INPUT)
(OUTPUT)
D
Q
ns
LE
Q
ns
PRE
Q
ns
CLR
Q
ns
OE
Q
ns
OE
Q
ns
18-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
CLR low 3.3 3.3 3.3
t
w
Pulse duration
p
PRE
low 3.3 3.3 3.3
LE high 3.3 3.3 3.3
High 0.9 0.9 0.9
Low 0.6 0.6 0.6
High 1.7 1.7 1.7
Low 1.8 1.8 1.8
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1.6 3.1 4.2 1.6 5.1 1.6 4.8
1.6 3.2 4.2 1.6 5 1.6 4.8
2.3 4 5 2.3 6.3 2.3 5.9
2.5 3.9 4.8 2.5 5.6 2.5 5.3
2.1 4 5.1 2.1 6.3 2.1 6.1
2.2 3.7 4.6 2.2 5.3 2.2 5
1.9 3.7 4.8 1.9 5.7 1.9 5.4
2.2 4.2 5.3 2.2 6.1 2.2 6
1.6 3.3 4.3 1.6 5.5 1.6 5.4
2 3.2 4.6 2 5.9 2 5.8
1.7 4 5.5 1.7 6.4 1.7 6.3
1.7 3.7 4.4 1.7 5.3 1.7 5.2
SN54ABT16843 SN74ABT16843
SN54ABT16843 SN74ABT16843
UNIT
ns
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
Input
CL = 50 pF
(see Note A)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
500 Ω
LOAD CIRCUIT
t
w
SN54ABT16843, SN74ABT16843
18-BIT BUS-INTERFACE D-TYPE LATCHES
SCBS223E – OCTOBER 1992 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
7 V
500 Ω
S1
Open
GND
3 V
0 V
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
WITH 3-STATE OUTPUTS
Open
7 V
Open
3 V
1.5 V
0 V
t
su
h
3 V
0 V
Input
t
PLH
Output
t
PHL
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V
1.5 V1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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