TEXAS INSTRUMENTS SN54ABT16657 Technical data

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SN54ABT16657, SN74ABT16657

16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS

AND 3-STATE OUTPUTS

SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’ABT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.

(or 2T/R) is low, data flows

or

SN54ABT16657 . . . WD PACKAGE

SN74ABT16657 . . . DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56

1T/R

55

1ODD/EVEN

54

1PARITY

53

GND

52

1B1

51

1B2

50

V

CC

49

1B3

48

1B4

47

1B5

46

GND

45

1B6

44

1B7

43

1B8

42

2B1

41

2B2

40

2B3

39

GND

38

2B4

37

2B5

36

2B6

35

V

CC

34

2B7

33

2B8

32

GND

31

2PARITY

30

2ODD/EVEN

29

2T/R

1OE

NC

1ERR

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

2ERR

NC

2OE

NC – No internal connection

Odd or even parity is selected by a logic high or low level, respectively , on the 1ODD/EVEN (or 2ODD/EVEN)
input. 1P ARITY (or 2P ARITY) carries the parity bit value; it is an output from the parity generator/checker in the
transmit mode and an input to the parity generator/checker in the receive mode.

In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2P ARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN

) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1P ARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT16657, SN74ABT16657

NUMBER OF A OR B

INPUT/OUTPUT

0, 2, 4, 6, 8

1, 3, 5, 7

16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS

SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997

description (continued)

In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR)
output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example,
if 1ODD/EVEN
1ERR is low, indicating a parity error.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16657 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16657 is characterized for operation from –40°C to 85°C.

is high (odd parity selected), 1P ARITY is high, and there are three high bits on the 1B bus, then

FUNCTION TABLE

(each 8-bit section)

NUMBER OF A OR B

INPUTS THAT ARE HIGH

Don’t care H X X Z Z Z

OE

INPUTS

T/R

ODD/EVEN

L H H H Z Transmit
L HL L Z Transmit
L LH H H Receive
L LH L L Receive
L LL H L Receive
L LL L H Receive
L H H L Z Transmit
L HL H Z Transmit
L LH H L Receive
L LH L H Receive
L LL H H Receive
L LL L L Receive

INPUT/OUTPUT

PARITY

ERR

OUTPUTS

OUTPUT MODE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16657, SN74ABT16657

16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS

AND 3-STATE OUTPUTS

SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997

logic symbol

†

1

1OE

1T/R

1ODD/EVEN

2OE

2T/R

2ODD/EVEN

1A1

1A2
1A3
1A4
1A5
1A6
1A7
1A8

2A1

2A2
2A3
2A4
2A5
2A6
2A7
2A8

56

55
28
29

30

5

6
8
9
10
12
13
14

15

16
17
19
20
21
23
24

G3
3 EN1/3G5 [REC]

3 EN2 [XMIT]
N4

G8
8 EN6/8G10 [REC]

8 EN7 [XMIT]
N9

6

1
12

, 2

4

4

, 1

1
12k7

2k

9, 7

9, 6

Z11

11

•

•

•

18

Z21

21

•

•

•

28

1

10

52

1B1

51

1B2

49

1B3

48

1B4

47

1B5

45

1B6

44

1B7

43

1B8

54

1PARITY

5

42

41
40
38
37
36
34
33

31

26

3

1ERR

2B1

2B2
2B3
2B4
2B5
2B6
2B7
2B8

2PARITY

2ERR

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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