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SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16952 are 16-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. The ’ABT16952 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB
output-enable (OEAB or OEBA) input low
accesses the data on either port.
or CLKENBA) input is low. Taking the
SN54ABT16952 ...WD PACKAGE
SN74ABT16952 . . . DGG OR DL PACKAGE
1OEAB
1CLKAB
1CLKENAB
2CLKENAB
2CLKAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16952 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16952 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE
INPUTS
CLKENAB CLKAB OEAB
H X L X B
X LLXB
L ↑ LL L
L ↑ LH H
X X H X Z
†
A-to-B data flow is shown; B-to-A data flow is similar, but
uses CLKENBA
‡
Level of B before the indicated steady-state input
conditions were established
, CLKBA, and OEBA.
†
OUTPUT
A
B
0
0
‡
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol
†
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
EN3
G1
1C5
EN4
G2
EN9
G7
EN10
G8
3
6D
9
12D
11D
10
5D
4
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OEBA
1CLKENBA
1CLKBA
1OEAB
1CLKENAB
1CLKAB 2C6
2OEBA
2CLKENBA
2CLKBA 7C11
2OEAB
2CLKENAB
2CLKAB 8C12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
logic diagram (positive logic)
1A1
2A1
3
2
56
5
26
27
29
15
One of Eight
Channels
One of Eight
Channels
C1
CE
1D
C1
CE
1D
To Seven Other Channels
C1
CE
1D
1CLKENAB
1CLKAB
1OEBA
2CLKENAB
2CLKAB
2OEBA 2OEAB
54
55
1
52
31
30
28
42
1CLKENBA
1CLKBA
1OEAB
1B1
2CLKENBA
2CLKBA
2B1
C1
CE
1D
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
Current into any output in the low state, IO: SN54ABT16952 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16952 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Package thermal impedance, θJA (see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
stg
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions (see Note 3)
SN54ABT16952 SN74ABT16952
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
0 V
CC
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT16952, SN74ABT16952
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
V
V
V
GND
A
V
CC
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16952 SN74ABT16952
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
I
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Control inputs
A or B ports
‡
‡
§
A or B ports
¶
CC
Control inputs VI = 2.5 V or 0.5 V 3 pF
i
A or B ports VO = 2.5 V or 0.5 V 8.5 pF
io
OZH
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.7 V 50 50 50 µA
VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
=
or
I
CC
Outputs high 50 50 50 µA
Outputs high 2 2 2
Outputs low 35 35 35
Outputs disabled 2 2 2
±1 ±1 ±1
±100 ±100 ±100
0.5 0.5 0.5 mA
µ
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
,
ns
t
,
ns
(INPUT)
(OUTPUT)
CLK
A or B
ns
OE
A or B
ns
OE
A or B
ns
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
f
clock
t
w
su
h
†
This parameter is warranted, but not production tested.
Clock frequency 0 150 0 150 0 150 MHz
†
Pulse duration, CLKAB or CLKBA high or low 3.3 3.3 3.3 ns
Setup time,
before CLKAB↑ or CLKBA↑
Hold time,
after CLKAB↑ or CLKBA↑
A or B 3.5 3.5 3.5
CLKENAB
A or B 1 1 1
CLKENAB or CLKENBA 1 1 1
or CLKENBA 3 3 3
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
150 150 150 MHz
1 2.6 3.9 1 4.4 1 4.3
1 2.6 4.2 1 4.6 1 4.5
1 2.5 3.8 1 4.7 1 4.6
1 2.8 5.1 1 6.1 1 6
1.7 3.4 4.7 1.7 6.1 1.7 5.5
1.3 3 3.9 1.3 4.8 1.3 4.2
SN54ABT16952 SN74ABT16952
SN54ABT16952 SN74ABT16952
UNIT
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Output
Control
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
74ABT16952DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br)
SN74ABT16952DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br)
SN74ABT16952DL ACTIVE SSOP DL 56 20 Green (RoHS &
no Sb/Br)
SN74ABT16952DLR ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br)
SN74ABT16952DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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