TEXAS INSTRUMENTS SN54ABT16373A Technical data

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SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS160C – DECEMBER 1992 – REVISED MA Y 1997

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

Typical V

(Output Ground Bounce)

OLP

< 0.8 V at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’ABT16373A are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.

SN54ABT16373A . . . WD PACKAGE

SN74ABT16373A . . . DGG OR DL PACKAGE

1OE

1Q1
1Q2

GND

1Q3
1Q4

V

CC

1Q5
1Q6

GND

1Q7
1Q8
2Q1
2Q2

GND

2Q3
2Q4

V

CC

2Q5
2Q6

GND

2Q7
2Q8

2OE

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

1LE
1D1
1D2
GND
1D3
1D4
V

CC

1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V

CC

2D5
2D6
GND
2D7
2D8
2LE

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16373A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS160C – DECEMBER 1992 – REVISED MA Y 1997

FUNCTION TABLE

(each 8-bit section)

INPUTS

OE

L H H H
L HL L
L LX Q

H X X Z

LE D

OUTPUT

Q

0

logic symbol

†

1LE

2LE

1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8

1
48
24
25

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

1EN
C3
2EN
C4

3D

4D

11
12
13
14
16
17
19
20
22
23

2

1Q1

3

1Q2

5

1Q3

6

1Q4

8

1Q5

9

1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8

1

2

1OE

2OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1

1OE

48

1LE

47

1D1

To Seven Other Channels

2

C1
1D

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1Q1

2OE

2LE

2D1

24

25

36

C1
1D

To Seven Other Channels

132

2Q1

UNIT

SN54ABT16373A, SN74ABT16373A

16-BIT TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS160C – DECEMBER 1992 – REVISED MA Y 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT16373A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

SN74ABT16373A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54ABT16373A SN74ABT16373A

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

CC

0 V

CC

V

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ABT16373A, SN74ABT16373A

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

VOLV

V

V

V

I

V

CC

GND

16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS160C – DECEMBER 1992 – REVISED MA Y 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT16373A SN74ABT16373A

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

V

hys

I

I

‡

I

OZPU

‡

I

OZPD

I

OZH

I

OZL

I

off

I

Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA

CEX

§

I

O

Outputs high

I

Outputs low

CC

Outputs disabled

¶

∆I

CC

C

i

C

o

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This parameter is characterized, but not production tested.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

VCC = 0 to 5.5 V,
VI = VCC or GND

VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE

VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE

VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE

VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

VCC = 5.5 V, IO = 0,

=

or

VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 9.5 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

±1 ±1 ±1 µA

= X

= X

≥ 2 V

≥ 2 V

±50 ±50 ±50 µA

±50 ±50 ±50 µA

10 10 10 µA

–10 –10 –10 µA

2 2 2

85 85 85

2 2 2

1.5 1.5 1.5 mA

mA

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

#

4

t

w

t

su

t

h

These values apply only to the SN74ABT16373A.

Pulse duration, LE high 3.3 3.3 3.3 ns
Setup time, data before LE↓ 1.5 2.4 1.5 ns
Hold time, data after LE↓ 1 2.2 1 ns

VCC = 5 V,

TA = 25°C

MIN MAX MIN MAX MIN MAX

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

#

SN54ABT16373A SN74ABT16373A

UNIT