Texas Instruments SN28837FS, SN28837FS-X Datasheet

SN28837

1/2-INCH PAL TIMER

SOCS031B – JULY 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• PAL-Timing Operation

• Solid-State Reliability

• Color and Monochrome Operation

• Five Selectable-Antiblooming Modes

• Variable-Integration-Time Option

• Surface-Mount Package

• Clamp-Pulse Select Option

• Horizontal and Vertical Resets for External

Synchronization

description

The SN28837 is a monolithic integrated circuit designed to supply timing signals for the Texas Instruments (TI) 8-mm-diagonal TC276 (PAL color) and TC277 (P AL monochrome) CCD image sensors. The SN28837 supplies both CCD-drive signals and PAL-television synchronization signals at standard video rates. It requires a single 5-V supply voltage and a 13.37-MHz crystal-oscillator input. The SN28837 provides the user with several options including multiple antiblooming modes, variable-integration time, external synchronization, clamp-pulse selection, and delayed horizontal transfer.

The SN28837 is designed to drive the CCD image sensor through intermediary level-shifting devices such as the TI TMS3473B parallel driver and the SN28846 serial driver. It also supplies sample-and-hold signals for the TI TL1593 3-channel sample-and-hold circuit and multiplex signals for the TI TL1051 video preprocessor. In color applications, the SN28837 interfaces with the SN28838 color-subcarrier generator to generate the PAL color subcarrier.

The SN28837 is supplied in a 60-pin plastic flat package and is characterized for operation from –20°C to 45°C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these

high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication

Guidelines for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices and Assemblies

available from Texas Instruments.

TI is a trademark of Texas Instruments Incorporated.

CC1

X2 X1 GND V

PI ABIN GT PS NC S3 S2 S1 T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

BCP1 BCP2

CP1 CP2

CSYNC

CBLK

SCBLK

IDP

HGATE

TESTA

SFI

17 18 19 20 21 22 23 24 25 26 27 28 29

59 58 57 56 55 5453 525150 4948 47

HCR

VCR

GT2

SH1

CLK

LSW

CLK13M

GT3/SH2

GT1/SH3

16 30

GND

TESTC

VDS

HIGH

GPS

VD2

ABS1

ABS2

ABS0

VGATE

TESTB

E/L

FS PACKAGE

(TOP VIEW)

NC – No internal connection

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN28837 1/2-INCH PAL TIMER

SOCS031B – JULY 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Oscillator

Divide

by 4

13 MHz

3.3 MHz

Horizontal

Counter

Vertical Counter

Clock

Generator

Antiblooming

Generator

Serial

Generator

Decoder

49 37 39 36 31

PD GT PI PS T

S1 S2 S3 SH1 GT3/SH2 GT1/SH3 GT2

32 33 34 51 53 56 57

ABIN

GPS

VDS

ABS0 ABS1 ABS2

21 22 23

E/L

HCR

VCR

CLK

CLK13M

26 27

18 29

1 2 3 4 5 6

7 8 48

9 10 12 16 17 28 20 11 12 14

BCP1 BCP2 CP1 CP2 CSYNC CBLK BF VD LSW SCBLK IDP TESTA TESTB TESTC VD2 VGATE HGATE

FI SFI

The levels on these three terminals determine which of the five antiblooming modes is selected:

Mode

ABS2 ABS1 ABS0 Operation 0 NC L L No ABG pulses 1 NC H L 2-MHz burst of ABG pulses 2 NC L H 1-MHz burst of ABG pulses 3 H H H 1-MHz continuous ABG pulses 4 L H H 2-MHz continuous ABG pulses

SN28837

1/2-INCH PAL TIMER

SOCS031B – JULY 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ABIN 38 O Antiblooming in

ABS0 21 I

ABS1 22 I

ABS2 23 I

Mode 1 is used for normal operation. BCP1 1 O Optical black clamp BCP2 2 O Optical black clamp BF 7 O Burst flag CBLK 6 O Composite blank CLK 50 O 3.34-MHz clock (factory-test point) CLK13M 47 O 13-MHz clock (connect to SN28838 color-subcarrier generator for color operation) CP1 3 O Clamp 1 (signal processing) CP2 4 O Clamp 2 (signal processing) CSYNC 5 O Composite sync

E/L 19 I

Delay select for S1, S2, S3. When E/L is high, the three serial-transfer pulses occur early relative to the

sample-and-hold pulses SH1, SH2, and SH3. When E/L

is low, the three serial-transfer pulses occur late

relative to the sample-and-hold pulses. FI 13 O Field index GND 41, 60 Ground GP 27 I Exposure control: GP gates the PS and PI outputs (see the description of GPS)

GPS 26 I

When GPS is high, the timer operates in the normal-integration-time mode (t

int

= 20 ms) and VD is connected internally to GP. To operate the imager in the variable-integration-time mode, GPS must be held low and a user-defined logic circuit must be inserted between VD and GP to vary the integration time (see Figure 1).

GT 37 O TMS3473B parallel-driver MIDSEL input switch GT1/SH3 56 O

GT1/SH3 is a logic signal for both Y gate 1 of the TL1051 video preprocessor and sample-and-hold channel 3 of the TL1593 3-channel sample-and-hold circuit.

GT2 57 O Y gate 2 for the TL1051 video preprocessor GT3/SH2 53 O

GT3/SH2 is a logic signal for both Y gate 3 of the TL1051 video preprocessor and sample-and-hold channel 2 of the TL1593 3-channel sample-and-hold circuit.

HCR 59 I Horizontal-counter reset HGATE 11 O Decoded H count signal. HGATE is a test point and is not used in normal operation. HIGH 25 I Not used (tie high) IDP 10 O ID pulse (for SECAM operation) LSW 48 O Line switch (connect to SN28838 for color operation)

15, 30, 35, 46,

52, 54, 55

No connect

PD 49 O Power down. A low-logic level on PD causes the device to enter a low power-consumption mode. PI 39 O Parallel-image-area gate clock PS 36 O Parallel-storage-area gate clock

SB 29 I

Standby-mode select. When SB is high, normal operation is selected; when SB is low, the power-down mode is selected.

SCBLK 9 O Subcarrier blank (for SECAM applications)

SN28837 1/2-INCH PAL TIMER

SOCS031B – JULY 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

SFI 14 O Second field index SH1 51 O Sample and hold 1 S1 32 O Serial clock 1 S2 33 O Serial clock 2 S3 34 O Serial clock 3 T 31 O Transfer-gate clock TESTA 12 O Test A (factory-test point) TESTB 16 O Test B (factory-test point) TESTC 17 O Test C (factory-test point) V

24, 40, 45 DC power VCC1 44 Oscillator power VCR 58 I Vertical-counter reset VD 8 O Vertical drive

VDS 18 I

Vertical-dump speed. When VDS is high, the vertical-dump frequency is 3.3MHz; when VDS is low, the

vertical-dump frequency is 2 MHz. VD2 28 O Real-display-area signal. VD2 is a test point and is not used in normal operation. VGATE 20 O Decoded V count signal. VGATE is a test point and is not used in normal operation. X1 42 X2 43

Crystal oscillator (see Figure 2)

12 3

int

Flush Pulses Transfer Pulse

Figure 1. GP Flush and Transfer Pulses

SN28837

1/2-INCH PAL TIMER

SOCS031B – JULY 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

variable-integration-time mode

In addition to the normal TV mode of operation, the SN28837 timing generator offers an optional variable-integration mode for use with the TC276 and TC277 CCD area-array image sensors. The variable-integration mode is selected by applying a low-logic level to GPS. This low-logic level disables the vertical-drive (VD) signal from controlling, internal to the timer, the image-area and storage-area parallel transfer signal (GP).

Prior to the start of a new integration period, the charge that has accumulated in the image area must be transferred out. To flush this previous signal or dark-current charge from the image area, GP is pulsed low two times. Each low pulse generates 302 pulses image-area and storage-area gate and transfer signals that shift the unwanted charge into the clearing drain. This clearing function should be performed during the high time of the VD signal (see Figure 3 through Figure 13).

The new integration period continues as long as GP remains high. GPS must be held at a low-logic level to prevent VD from controlling GP internally . The integration ceases and the readout occurs when VD and GP are pulsed low simultaneously; this is accomplished by taking GPS to a high-logic level. The readout timing is dependent on the vertical-drive pulse; this means that the total-integration time is a multiple of 1/50 of a second plus the time interval between the last GP low pulse and the next VD low pulse. The image readout occurs within the normal 1/50-second readout interval. If the integration time is less than 1/50 of a second, normal output operation occurs; if the integration time is greater than 1/50 of a second, a frame buffer may be required to capture the image.

Integration times greater than 1/50 of a second result in image degradation at temperatures greater than 25°C due to dark-current generation. The degradation is seen as a decrease in dynamic range (contrast) and an increase in noise. It is recommended that the image sensor be cooled for long-exposure operation. The dark-current generation is reduced by a factor of two for each 7°C temperature decrease. The sensor operates at –30°C. Cooling can be accomplished by using a thermoelectric or Peltier cooler attached to the image sensor . Condensation on the header must be prevented by isolating the cooled sensor from moist air. V acuum isolation is preferred; however, the continual flushing of dry nitrogen across the header can also prevent condensation.

X1 X2

42 43

C1 ≈ 40 pF C2 ≈ 40 pF

SN28837

NOTE: The SN28837 is designed for use with a

crystal oscillator. The X1 and X2 terminals should not connect directly to external driver outputs.

Figure 2. Connection of an External Crystal Oscillator to the SN28837

SN28837 1/2-INCH PAL TIMER

SOCS031B – JULY 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

–0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) T

= 25°C 300 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

–20°C to 45°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

STG

–55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.5 5 5.5 V

High-level input voltage, V

VDD x 0.7 V

Low-level input voltage, V

0.8 V Operating frequency 13.375 MHz Power-up time 300 µs Operating free-air temperature, T

–20 45 °C

electrical characteristics over recommended operating ranges of supply voltage and free-air temperature (unless otherwise noted)

‡

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

GT3/SH2 and GT1/SH3 VDD = 4.5 V, IOH = –4 mA 3.5

All other outputs VDD = 4.5 V, IOH = –2 mA 3.5

GT3/SH2 and GT1/SH3 VDD = 4.5 V, IOL = 4 mA 0.5

All other outputs VDD = 4.5 V, IOL = 2 mA 0.5

VIH = 5 V 1 µA

VIL = 0 –30 –200 –500 µA

DD(AV)

Average supply current 10 30 mA

DD(S)

Standby supply current 1 mA

‡

The HCR, SB, and VCR inputs are Schmitt-trigger inputs with 0.1-V to 1-V hysteresis.

All inputs except X1 have pullup-current sources.

switching characteristics over recommended operating free-air temperature range, VDD = 5 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

clock

Frequency

S1, S2, S3, SH1, GT2, GT1/SH3, GT3/SH2

4.458333

MHz

Pulse duration

S1, S2, S3, SH1, GT2, GT1/SH3, GT3/SH2

= 50

GT1/SH3 and GT3/SH2 10

trRise time

All other outputs

GT1/SH3 and GT3/SH2

50 pF

tfFall time

All other outputs 50

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