SN10KHT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990
Copyright 1990, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 10KH Compatible
• ECL Clock and TTL Control Inputs
• Flow-Through Architecture Optimizes PCB
Layout
• Center Pin V
CC
, VEE, and GND
Configurations Minimize High-Speed
Switching Noise
• Package Options Include “Small Outline”
Packages and Standard Plastic DIPs
description
This octal ECL-to-TTL translator is designed to
provide efficient translation between a 10KH ECL
signal environment and a TTL signal environment.
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented
functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the
clock, the Q outputs are set to the logic levels that were set up at the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive
bus lines without need for interface or pullup components.
The output-enable input OE
does not affect the internal operations of the flip-flops. Old data can be retained
or new data can be entered while the outputs are off.
The SN10KHT5574 is characterized for operation from 0°C to 75°C.
FUNCTION TABLE
OE CLK D
INPUTS
Q
OUTPUT
(TTL)
L ↑ LL
L↑HH
LLX
Q
o
HXX Z
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
V
CC
GND
GND
GND
5Q
6Q
7Q
8Q
1D
2D
3D
4D
OE
(TTL)
V
EE
GND
CLK(ECL)
5D
6D
7D
8D
DW OR NT PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN10KHT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
logic diagram (positive logic)
1D
CLK
2D
3D
4D
5D
6D
7D
8D
20
17
24
23
22
21
16
15
14
13
12
11
10
9
4
3
2
1
1D
EN
C1
ECL/TTL
ECL/TTL
OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1D
CLK
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
20
17
24
23
22
21
16
15
14
13
12
11
10
9
4
3
2
1
1D
C1
C1
C1
C1
C1
C1
C1
C1
1D
1D
1D
1D
1D
1D
1D
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
OE
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
ECL/TTL
SN10KHT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, V
EE
–8 V to 0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: TTL (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECL V
EE
to 0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any output in the high state –0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range, (TTL) –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
TTL supply voltage 4.5 5 5.5 V
V
EE
ECL supply voltage –4.94 –5.2 –5.46 V
V
IH
TTL high-level input voltage 2 V
V
IL
TTL low-level input voltage 0.8 V
TA = 0°C –1170 –840
V
IH
ECL high-level input voltage
‡
TA = 25°C –1130 –810 mV
TA = 75°C –1070 –735
TA = 0°C –1950 –1480
V
IL
ECL low-level input voltage
‡
TA = 25°C –1950 –1480 mV
TA = 75°C –1950 –1450
I
IK
TTL input clamp current –18 mA
I
OH
High-level output current –15 mA
I
OL
Low-level output current 48 mA
T
A
Operating free-air temperature range 0 75 °C
‡
The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
V
OH V
UNIT
ns
ns
ns
t
su
Setup time before CLK↑
Hold time after CLK↑
Pulse duration
t
h
t
w
SN10KHT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIKOE only VCC = 4.5 V, VEE = –4.94 V, II = –18 mA –1.2 V
VCC = 4.5 V, VEE = –5.2 V ±5%, IOH = –3 mA 2.4 3.3
VCC = 4.5 V, VEE = –5.2 V ±5%, IOH = –15 mA 2 3.1
V
OL
VCC = 4.5 V, VEE = –5.2 V ±5%, IOL = 48 mA 0.38 0.55 V
I
I
OE only VCC = 5.5 V, VEE = –5.46 V, VI = 7 V 0.1 mA
I
IH
OE only VCC = 5.5 V, VEE = –5.46 V, VI = 2.7 V 20 µA
I
IL
OE only VCC = 5.5 V, VEE = –5.46 V, VI = 0.5 V –0.5 mA
VCC = 5.5 V, VEE = –5.46 V, VI = –840 mV TA = 0°C 350
I
IH
Data inputs and CLK VCC = 5.5 V, VEE = –5.46 V, VI = –810 mV TA = 25°C 350 µA
VCC = 5.5 V, VEE = –5.46 V, VI = –735 mV TA = 75°C 350
TA = 0°C 0.5
I
IL
Data inputs and CLK VCC = 5.5 V, VEE = –5.46 V, VI = –1950 mV TA = 25°C 0.5 µA
TA = 75°C 0.5
I
OZH
VCC = 5.5 V, VEE = –5.46 V, VO = 2.7 V 50 µA
I
OZL
VCC = 5.5 V, VEE = –5.46 V, VO = 0.5 V –50 µA
I
OS
‡
VCC = 5.5 V, VEE = –5.46 V, VO = 0 V –100 –225 mA
I
CCH
VCC = 5.5 V, VEE = –5.46 V 66 95 mA
I
CCL
VCC = 5.5 V, VEE = –5.46 V 76 110 mA
I
CCZ
VCC = 5.5 V, VEE = –5.46 V 74 106 mA
I
EE
VCC = 5.5 V, VEE = –5.46 V –43 –61 mA
C
i
VCC = 5.5 V, VEE = –5.2 V, f = 10 MHz 5 pF
C
o
VCC = 5.5 V, VEE = –5.2 V, f = 10 MHz 7 pF
†
All typical values are at VCC = 5 V, VEE = –5.2 V, TA = 25°C.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements
VCC = 4.5 V to 5.5 V,
VEE = –4.94 V to –5.46 V,
TA = MIN to MAX
§
MIN MAX
CLK high 4
CLK low 4
Data high 1
Data low 1
Data high 1
Data low 1
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
ns
ns
ns
CLK Q
Q
Q
OE
OE
PARAMETER UNIT
SN10KHT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of operating free-air temperature and supply voltage
(see Figure 1)
CL = 50 pF,
FROM TO R1 = 500 Ω,
(INPUT) (OUTPUT) R2 = 500 Ω
MIN TYP†MAX
f
max
200 300 MHz
t
PLH
2.3 4.1 7
t
PHL
2.9 4.6 7.4
t
PZH
1.9 3.6 6.3
t
PZL
2.7 4.8 7.7
t
PHZ
2.1 3.9 6.1
t
PLZ
0.5 3.4 6.3
†
All typical values are at VCC = 5 V, VEE = –5.2 V, TA = 25°C.
SN10KHT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT
t
PHL
t
PLH
V
OH
V
OL
–890 mV
–1690 mV
50%
50%
Test Point
R1
R2
S1
C
L
7 V
(See Note A)
Open
1.5 V
1.5 V
–890 mV
TEST
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
S1
Open
Open
Open
Closed
Open
Closed
SWITCH POSITION TABLE
High-Level
Input
Low-Level
Input
t
w
50%50%
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
3 V
0
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note D)
Output
Waveform 2
(See Note D)
0
V
OH
V
OL
3.5 V
VOLTAGE WAVEFORMS
TTL ENABLE AND DISABLE TIMES
t
PLZ
t
PZL
t
PZH
t
PHZ
1.5 V
1.5 V
0.3 V
0.3 V
1.5 V
50%
–1690 mV
Timing
Input
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
ECL Input
(See Note C)
Out-of-Phase
TTL Output
VOLTAGE WAVEFORMS
ECL-INPUT PROPAGATION DELAY TIMES
80%
20%
80%
20%
t
r
t
f
V
OH
V
OL
1.5 V
1.5 V
In-Phase
TTL Output
t
PLH
t
PHL
–890 mV
–1690 mV
80%
20%
t
r
20%
t
f
80%
50%
–890 mV
–1690 mV
–890 mV
–1690 mV
50%
50%
t
h
t
su
t
f
t
r
80%
20%
80%
20%
NOTES: A.CL includes probe and jig capacitance.
B.For TTL inputs, input pulses are supplied by generators having the following characteristics PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns.
C.For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 1.5 ns,
tf≤ 1.5 ns.
D.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
E.The outputs are measured one at a time with one transition per measurement.
Figure 1. Load circuit and voltage waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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