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SimpleLink Wi-Fi CC323x
Technical Reference Manual
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Texas Instruments SimpleLink Wi-Fi CC323x Technical Reference Manual

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SimpleLink™ Wi-Fi® CC323x
Technical Reference Manual
Literature Number: SWRU543A
JANUARY 2019 – REVISED SEPTEMBER 2020
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Table of Contents

Read This First.........................................................................................................................................................................25
Audience................................................................................................................................................................................ 25
About This Manual................................................................................................................................................................. 25
Register Bit Conventions........................................................................................................................................................25
Glossary.................................................................................................................................................................................25
Related Documentation..........................................................................................................................................................26
Community Resources...........................................................................................................................................................26
Trademarks............................................................................................................................................................................27
1.1 Introduction...................................................................................................................................................................... 30
1.2 Architecture Overview...................................................................................................................................................... 31
1.3 Functional Overview.........................................................................................................................................................32
1.3.1 Processor Core..........................................................................................................................................................32
1.3.2 Memory......................................................................................................................................................................33
1.3.3 Micro-Direct Memory Access Controller (µDMA).......................................................................................................34
1.3.4 General-Purpose Timer (GPT).................................................................................................................................. 34
1.3.5 Watchdog Timer (WDT).............................................................................................................................................35
1.3.6 Multichannel Audio Serial Port (McASP)................................................................................................................... 35
1.3.7 Serial Peripheral Interface (SPI)................................................................................................................................36
1.3.8 Inter-Integrated Circuit (I2C) Interface.......................................................................................................................36
1.3.9 Universal Asynchronous Receiver/Transmitter (UART)............................................................................................ 36
1.3.10 General-Purpose Input/Output (GPIO).................................................................................................................... 37
1.3.11 Analog-to-Digital Converter (ADC)...........................................................................................................................37
1.3.12 SD Card Host.......................................................................................................................................................... 37
1.3.13 Parallel Camera Interface........................................................................................................................................38
1.3.14 Debug Interface.......................................................................................................................................................38
1.3.15 Hardware Cryptography Accelerator....................................................................................................................... 38
1.3.16 Clock, Reset, and Power Management................................................................................................................... 38
1.3.17 SimpleLink™ Subsystem.........................................................................................................................................39
1.3.18 I/O Pads and Pin Multiplexing................................................................................................................................. 39
2 Cortex®-M4 Processor.........................................................................................................................................................41
2.1 Overview.......................................................................................................................................................................... 42
2.1.1 Block Diagram........................................................................................................................................................... 43
2.1.2 System-Level Interface..............................................................................................................................................43
2.1.3 Integrated Configurable Debug................................................................................................................................. 43
2.1.4 Trace Port Interface Unit (TPIU)................................................................................................................................44
2.1.5 Cortex®-M4 System Component Details................................................................................................................... 44
2.2 Functional Description......................................................................................................................................................45
2.2.1 Programming Model.................................................................................................................................................. 45
2.2.2 Register Description.................................................................................................................................................. 46
2.2.3 Memory Model...........................................................................................................................................................49
2.2.4 Exception Model........................................................................................................................................................53
2.2.5 Fault Handling........................................................................................................................................................... 59
2.2.6 Power Management.................................................................................................................................................. 62
2.2.7 Instruction Set Summary........................................................................................................................................... 64
3 Cortex®-M4 Peripherals.......................................................................................................................................................69
3.1 Overview.......................................................................................................................................................................... 70
3.2 Functional Description......................................................................................................................................................70
3.2.1 System Timer (SysTick).............................................................................................................................................70
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3.2.2 Nested Vectored Interrupt Controller (NVIC).............................................................................................................71
3.2.3 System Control Block (SCB)..................................................................................................................................... 72
3.3 Register Map....................................................................................................................................................................72
3.3.1 Cortex Registers........................................................................................................................................................75
4 Direct Memory Access (DMA)............................................................................................................................................113
4.1 Overview.........................................................................................................................................................................114
4.2 Functional Description....................................................................................................................................................114
4.2.1 Channel Assignment................................................................................................................................................115
4.2.2 Priority......................................................................................................................................................................115
4.2.3 Arbitration Size.........................................................................................................................................................116
4.2.4 Channel Configuration............................................................................................................................................. 116
4.2.5 Transfer Mode..........................................................................................................................................................118
4.2.6 Transfer Size and Increment................................................................................................................................... 121
4.2.7 Peripheral Interface................................................................................................................................................. 122
4.2.8 Interrupts and Errors................................................................................................................................................122
4.3 Register Description.......................................................................................................................................................123
4.3.1 DMA Register Map.................................................................................................................................................. 123
4.3.2 µDMA Channel Control Structure............................................................................................................................124
4.3.3 DMA Registers........................................................................................................................................................ 124
4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers................................................................................ 129
5 General-Purpose Input/Outputs (GPIOs)..........................................................................................................................153
5.1 Overview........................................................................................................................................................................ 154
5.2 Functional Description....................................................................................................................................................154
5.2.1 Data Control............................................................................................................................................................ 154
5.3 Interrupt Control............................................................................................................................................................. 155
5.3.1 µDMA Trigger Source..............................................................................................................................................156
5.4 Initialization and Configuration.......................................................................................................................................156
5.5 GPIO Registers..............................................................................................................................................................158
6 Universal Asynchronous Receivers/Transmitters (UARTs)............................................................................................171
6.1 Overview........................................................................................................................................................................ 172
6.1.1 Block Diagram......................................................................................................................................................... 172
6.2 Functional Description....................................................................................................................................................173
6.2.1 Transmit and Receive Logic.................................................................................................................................... 173
6.2.2 Baud-Rate Generation.............................................................................................................................................174
6.2.3 Data Transmission...................................................................................................................................................174
6.2.4 Initialization and Configuration................................................................................................................................ 177
6.3 UART Registers............................................................................................................................................................. 179
7 Inter-Integrated Circuit (I2C) Interface.............................................................................................................................. 203
7.1 Overview........................................................................................................................................................................ 204
7.1.1 Block Diagram......................................................................................................................................................... 204
7.1.2 Signal Description....................................................................................................................................................205
7.2 Functional Description....................................................................................................................................................206
7.2.1 I2C Bus Functional Overview.................................................................................................................................. 206
7.2.2 Supported Speed Modes.........................................................................................................................................209
7.2.3 Interrupts................................................................................................................................................................. 210
7.2.4 Loopback Operation.................................................................................................................................................211
7.2.5 FIFO and µDMA Operation......................................................................................................................................211
7.2.6 Command Sequence Flow Charts...........................................................................................................................213
7.2.7 Initialization and Configuration................................................................................................................................ 220
7.3 I2C Registers................................................................................................................................................................. 221
8 SPI (Serial Peripheral Interface)........................................................................................................................................ 267
8.1 Overview........................................................................................................................................................................ 268
8.1.1 Features.................................................................................................................................................................. 268
8.2 Functional Description....................................................................................................................................................269
8.2.1 SPI...........................................................................................................................................................................269
8.2.2 SPI Transmission.....................................................................................................................................................269
8.2.3 Master Mode............................................................................................................................................................273
8.2.4 Slave Mode..............................................................................................................................................................280
8.2.5 Interrupts................................................................................................................................................................. 282
8.2.6 DMA Requests........................................................................................................................................................ 283
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8.2.7 Reset....................................................................................................................................................................... 284
8.3 Initialization and Configuration.......................................................................................................................................284
8.3.1 Basic Initialization....................................................................................................................................................284
8.3.2 Master Mode Operation Without Interrupt (Polling)................................................................................................. 284
8.3.3 Slave Mode Operation With Interrupt...................................................................................................................... 284
8.3.4 Generic Interrupt Handler Implementation.............................................................................................................. 285
8.4 Access to Data Registers...............................................................................................................................................285
8.5 Module Initialization........................................................................................................................................................286
8.5.1 Common Transfer Sequence...................................................................................................................................286
8.5.2 End-of-Transfer Sequences.....................................................................................................................................287
8.5.3 FIFO Mode.............................................................................................................................................................. 288
8.6 SPI Registers................................................................................................................................................................. 292
9 General-Purpose Timers....................................................................................................................................................309
9.1 Overview........................................................................................................................................................................ 310
9.2 Block Diagram................................................................................................................................................................310
9.3 Functional Description....................................................................................................................................................311
9.3.1 GPTM Reset Conditions..........................................................................................................................................312
9.3.2 Timer Modes............................................................................................................................................................312
9.3.3 DMA Operation........................................................................................................................................................317
9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values....................................................................................317
9.4 Initialization and Configuration.......................................................................................................................................318
9.4.1 One-Shot and Periodic Timer Mode........................................................................................................................ 318
9.4.2 Input Edge-Count Mode.......................................................................................................................................... 318
9.4.3 Input Edge-Time Mode............................................................................................................................................319
9.4.4 PWM Mode..............................................................................................................................................................319
9.5 Timer Registers..............................................................................................................................................................321
10 Watchdog Timer................................................................................................................................................................351
10.1 Overview...................................................................................................................................................................... 352
10.1.1 Block Diagram....................................................................................................................................................... 352
10.2 Functional Description..................................................................................................................................................352
10.2.1 Initialization and Configuration.............................................................................................................................. 353
10.3 WATCHDOG Registers................................................................................................................................................ 354
10.4 MCU Watchdog Controller Usage Caveats..................................................................................................................362
10.4.1 System Watchdog..................................................................................................................................................362
10.4.2 System Watchdog Recovery Sequence................................................................................................................ 364
11 SD Host Controller Interface............................................................................................................................................365
11.1 Overview.......................................................................................................................................................................366
11.2 SD Host Features.........................................................................................................................................................366
11.3 1-Bit SD Interface.........................................................................................................................................................366
11.3.1 Clock and Reset Management...............................................................................................................................368
11.4 Initialization and Configuration Using Peripheral APIs.................................................................................................368
11.4.1 Basic Initialization and Configuration.....................................................................................................................368
11.4.2 Sending Command................................................................................................................................................369
11.4.3 Card Detection and Initialization............................................................................................................................370
11.4.4 Block Read.............................................................................................................................................................371
11.4.5 Block Write.............................................................................................................................................................372
11.5 Performance and Testing..............................................................................................................................................372
11.6 Peripheral Library APIs.................................................................................................................................................373
11.7 SD-HOST Registers.....................................................................................................................................................378
12 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port....................................................................................... 407
12.1 Overview...................................................................................................................................................................... 408
12.1.1 I2S Format.............................................................................................................................................................408
12.2 Functional Description..................................................................................................................................................409
12.3 Programming Model.....................................................................................................................................................409
12.3.1 Clock and Reset Management.............................................................................................................................. 409
12.3.2 I2S Data Port Interface..........................................................................................................................................410
12.3.3 Initialization and Configuration.............................................................................................................................. 410
12.4 Peripheral Library APIs for I2S Configuration.............................................................................................................. 412
12.4.1 Basic APIs for Enabling and Configuring the Interface..........................................................................................412
12.4.2 APIs for Data Access if DMA is Not Used............................................................................................................. 414
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12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral...................................................415
12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral......................................................................... 419
12.5 I2S Registers................................................................................................................................................................421
13 Analog-to-Digital Converter (ADC)..................................................................................................................................469
13.1 Overview...................................................................................................................................................................... 470
13.2 Key Features................................................................................................................................................................470
13.3 ADC Register Mapping................................................................................................................................................ 471
13.4 ADC_MODULE Registers............................................................................................................................................ 472
13.5 Initialization and Configuration.....................................................................................................................................491
13.6 Peripheral Library APIs for ADC Operation..................................................................................................................491
13.6.1 Overview................................................................................................................................................................491
13.6.2 Configuring the ADC Channels............................................................................................................................. 491
13.6.3 Basic APIs for Enabling and Configuring the Interface..........................................................................................492
13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup].......................................................................... 493
13.6.5 APIs for Interrupt Usage........................................................................................................................................494
13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples..........................................................................497
14 Parallel Camera Interface Module................................................................................................................................... 499
14.1 Overview...................................................................................................................................................................... 500
14.2 Image Sensor Interface................................................................................................................................................500
14.3 Functional Description..................................................................................................................................................501
14.3.1 Modes of Operation...............................................................................................................................................501
14.3.2 FIFO Buffer............................................................................................................................................................503
14.3.3 Reset..................................................................................................................................................................... 503
14.3.4 Clock Generation...................................................................................................................................................503
14.3.5 Interrupt Generation.............................................................................................................................................. 504
14.3.6 DMA Interface........................................................................................................................................................504
14.4 Programming Model.....................................................................................................................................................505
14.4.1 Camera Core Reset...............................................................................................................................................505
14.4.2 Enable the Picture Acquisition...............................................................................................................................505
14.4.3 Disable the Picture Acquisition.............................................................................................................................. 506
14.5 Interrupt Handling.........................................................................................................................................................506
14.5.1 FIFO_OF_IRQ (FIFO Overflow)............................................................................................................................ 506
14.5.2 FIFO_UF_IRQ (FIFO Underflow)...........................................................................................................................506
14.6 Camera Registers........................................................................................................................................................ 507
14.7 Peripheral Library APIs................................................................................................................................................ 521
14.8 Developer’s Guide........................................................................................................................................................524
14.8.1 Using Peripheral Driver APIs for Capturing an Image........................................................................................... 524
14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors................................................................ 527
15 Power, Reset, and Clock Management........................................................................................................................... 529
15.1 Overview...................................................................................................................................................................... 530
15.1.1 Power Management Unit (PMU)............................................................................................................................530
15.1.2 VBAT Wide-Voltage Connection............................................................................................................................ 531
15.1.3 Supply Brownout and Blackout..............................................................................................................................531
15.1.4 Application Processor Power Modes.....................................................................................................................532
15.2 Power Management Control Architecture.................................................................................................................... 533
15.2.1 Global Power-Reset-Clock Manager (GPRCM).................................................................................................... 534
15.2.2 Application Reset-Clock Manager (ARCM)........................................................................................................... 536
15.3 PRCM APIs..................................................................................................................................................................536
15.3.1 MCU Initialization...................................................................................................................................................536
15.3.2 Reset Control.........................................................................................................................................................536
15.3.3 Peripheral Reset....................................................................................................................................................536
15.3.4 Reset Cause..........................................................................................................................................................537
15.3.5 Clock Control.........................................................................................................................................................537
15.3.6 Low-Power Modes.................................................................................................................................................538
15.3.7 Sleep (SLEEP)...................................................................................................................................................... 538
15.3.8 Low-Power Deep Sleep (LPDS)............................................................................................................................ 539
15.3.9 Hibernate (HIB)......................................................................................................................................................540
15.3.10 Slow Clock Counter............................................................................................................................................. 542
15.4 Peripheral Macros........................................................................................................................................................543
15.5 Power Management Framework.................................................................................................................................. 543
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15.6 PRCM Registers.......................................................................................................................................................... 543
16 I/O Pads and Pin Multiplexing..........................................................................................................................................595
16.1 Overview...................................................................................................................................................................... 596
16.2 I/O Pad Electrical Specifications.................................................................................................................................. 597
16.3 Analog and Digital Pin Multiplexing..............................................................................................................................598
16.4 Special Analog/Digital Pins.......................................................................................................................................... 598
16.4.1 Pins 45 and 52.......................................................................................................................................................598
16.4.2 Pins 29 and 30.......................................................................................................................................................598
16.4.3 Pins 57, 58, 59, and 60..........................................................................................................................................598
16.5 Analog Mux Control Registers..................................................................................................................................... 601
16.6 Pins Available for Applications..................................................................................................................................... 603
16.7 Functional Pin Mux Configurations.............................................................................................................................. 607
16.8 Pin Mapping Recommendations.................................................................................................................................. 617
16.8.1 Pad Configuration Registers for Application Pins..................................................................................................618
16.8.2 PAD Behavior During Reset and Hibernate...........................................................................................................619
16.8.3 Control Architecture...............................................................................................................................................620
16.8.4 CC32xx Pin-mux Examples...................................................................................................................................621
16.8.5 Wake on Pad.........................................................................................................................................................625
16.8.6 Sense on Power.................................................................................................................................................... 626
17 Advance Encryption Standard Accelerator (AES).........................................................................................................627
17.1 AES Overview..............................................................................................................................................................628
17.2 AES Functional Description......................................................................................................................................... 628
17.2.1 AES Block Diagram............................................................................................................................................... 628
17.2.2 AES Algorithm....................................................................................................................................................... 631
17.2.3 AES Operating Modes...........................................................................................................................................632
17.2.4 Hardware Requests...............................................................................................................................................642
17.3 AES Module Programming Guide................................................................................................................................ 643
17.3.1 AES Low-Level Programming Models...................................................................................................................643
17.4 AES Registers..............................................................................................................................................................648
18 Data Encryption Standard Accelerator (DES)................................................................................................................ 681
18.1 DES Functional Description......................................................................................................................................... 682
18.2 DES Block Diagram..................................................................................................................................................... 682
18.2.1 µDMA Control........................................................................................................................................................683
18.2.2 Interrupt Control.....................................................................................................................................................683
18.2.3 Register Interface.................................................................................................................................................. 684
18.2.4 DES Enginer..........................................................................................................................................................684
18.3 DES-Supported Modes of Operation........................................................................................................................... 684
18.3.1 ECB Feedback Mode............................................................................................................................................ 684
18.4 DES Module Programming Guide – Low-Level Programming Models........................................................................ 686
18.4.1 Surrounding Modules Global Initialization............................................................................................................. 686
18.4.2 Operational Modes Configuration..........................................................................................................................687
18.4.3 DES Events Servicing........................................................................................................................................... 689
18.5 DES Registers..............................................................................................................................................................691
19 SHA/MD5 Accelerator....................................................................................................................................................... 711
19.1 SHA/MD5 Functional Description.................................................................................................................................712
19.1.1 SHA/MD5 Block Diagram...................................................................................................................................... 712
19.1.2 µDMA and Interrupt Requests...............................................................................................................................713
19.1.3 Operation Description............................................................................................................................................713
19.1.4 SHA/MD5 Programming Guide............................................................................................................................. 719
19.2 SHA-MD5 Registers.....................................................................................................................................................723
20 Cyclical Redundancy Check (CRC).................................................................................................................................773
20.1 Functional Description..................................................................................................................................................774
20.1.1 CRC Support......................................................................................................................................................... 774
20.2 Initialization and Configuration.....................................................................................................................................776
20.2.1 CRC Initialization and Configuration......................................................................................................................776
20.3 CRC Registers............................................................................................................................................................. 777
21 On-Chip Parallel Flash..................................................................................................................................................... 783
21.1 Flash Memory Configuration........................................................................................................................................ 784
21.2 Interrupts......................................................................................................................................................................784
21.3 Flash Memory Programming........................................................................................................................................784
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21.4 32-Word Flash Memory Write Buffer............................................................................................................................785
21.5 Flash Registers............................................................................................................................................................ 786
21.6 CC323xSF Boot Flow...................................................................................................................................................799
21.7 Flash User Application and Memory Partition.............................................................................................................. 800
21.8 Programming, Bootstrapping, and Updating the Flash User Application..................................................................... 802
21.9 Image Authentication and Integrity Check................................................................................................................... 803
21.10 Debugging Flash User Application Using JTAG.........................................................................................................805
A Software Development Kit Examples...............................................................................................................................807
B CC323x Device Miscellaneous Registers........................................................................................................................ 809
23.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]......................................................................................................810
23.2 DMA_IMS Register (offset = 90h) [reset = 0h]............................................................................................................. 812
23.3 DMA_IMC Register (offset = 94h) [reset = 0h].............................................................................................................814
23.4 DMA_ICR Register (offset = 9Ch) [reset = 0h].............................................................................................................816
23.5 DMA_MIS Register (offset = A0h) [reset = 0h].............................................................................................................818
23.6 DMA_RIS Register (offset = A4h) [reset = 0h]............................................................................................................. 820
23.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]...................................................................................................... 822
Revision History.................................................................................................................................................................... 823
List of Figures
Figure 1-1. CC32xx MCU and Wi-Fi® System-on-Chip.............................................................................................................31
Figure 2-1. Application CPU Block Diagram..............................................................................................................................43
Figure 2-2. TPIU Block Diagram................................................................................................................................................44
Figure 2-3. Cortex®-M4 Register Set........................................................................................................................................ 46
Figure 2-4. Data Storage........................................................................................................................................................... 52
Figure 2-5. Vector Table.............................................................................................................................................................57
Figure 2-6. Exception Stack Frame........................................................................................................................................... 59
Figure 2-7. Power-Management Architecture in CC32xx SoC.................................................................................................. 63
Figure 3-1. ACTLR Register...................................................................................................................................................... 76
Figure 3-2. STCTRL Register.................................................................................................................................................... 78
Figure 3-3. STRELOAD Register...............................................................................................................................................80
Figure 3-4. STCURRENT Register............................................................................................................................................81
Figure 3-5. EN_0 to EN_6 Register........................................................................................................................................... 82
Figure 3-6. DIS_0 to DIS_6 Register......................................................................................................................................... 83
Figure 3-7. PEND_0 to PEND_6 Register................................................................................................................................. 84
Figure 3-8. UNPEND_0 to UNPEND_6 Register.......................................................................................................................85
Figure 3-9. ACTIVE_0 to ACTIVE_6 Register........................................................................................................................... 86
Figure 3-10. PRI_0 to PRI_49 Register..................................................................................................................................... 87
Figure 3-11. CPUID Register..................................................................................................................................................... 88
Figure 3-12. INTCTRL Register.................................................................................................................................................89
Figure 3-13. VTABLE Register...................................................................................................................................................92
Figure 3-14. APINT Register..................................................................................................................................................... 93
Figure 3-15. SYSCTRL Register............................................................................................................................................... 95
Figure 3-16. CFGCTRL Register............................................................................................................................................... 96
Figure 3-17. SYSPRI1 Register.................................................................................................................................................98
Figure 3-18. SYSPRI2 Register.................................................................................................................................................99
Figure 3-19. SYSPRI3 Register...............................................................................................................................................100
Figure 3-20. SYSHNDCTRL Register......................................................................................................................................101
Figure 3-22. HFAULTSTAT Register........................................................................................................................................109
Figure 3-23. FAULTDDR Register............................................................................................................................................110
Figure 3-24. SWTRIG Register................................................................................................................................................ 111
Figure 4-1. Ping-Pong Mode....................................................................................................................................................119
Figure 4-2. Memory Scatter-Gather Mode...............................................................................................................................120
Figure 4-3. Peripheral Scatter-Gather Mode........................................................................................................................... 121
Figure 4-5. DMA_DSTENDP Register.....................................................................................................................................125
Figure 4-6. DMA_CHCTL Register.......................................................................................................................................... 126
Figure 4-7. DMA_STAT Register............................................................................................................................................. 130
Figure 4-8. DMA_CFG Register.............................................................................................................................................. 131
Figure 4-9. DMA_CTLBASE Register......................................................................................................................................132
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Figure 4-10. DMA_ALTBASE Register....................................................................................................................................133
Figure 4-11. DMA_WAITSTAT Register...................................................................................................................................134
Figure 4-12. DMA_SWREQ Register...................................................................................................................................... 135
Figure 4-13. DMA_USEBURSTSET Register......................................................................................................................... 136
Figure 4-14. DMA_USEBURSTCLR Register......................................................................................................................... 137
Figure 4-15. DMA_REQMASKSET Register........................................................................................................................... 138
Figure 4-16. DMA_REQMASKCLR Register...........................................................................................................................139
Figure 4-17. DMA_ENASET Register......................................................................................................................................140
Figure 4-18. DMA_ENACLR Register..................................................................................................................................... 141
Figure 4-19. DMA_ALTSET Register.......................................................................................................................................142
Figure 4-20. DMA_ALTCLR Register.......................................................................................................................................143
Figure 4-23. DMA_ERRCLR Register..................................................................................................................................... 146
Figure 4-24. DMA_CHASGN Register.....................................................................................................................................147
Figure 4-25. DMA_CHMAP0 Register..................................................................................................................................... 148
Figure 4-26. DMA_CHMAP1 Register..................................................................................................................................... 149
Figure 4-27. DMA_CHMAP2 Register..................................................................................................................................... 150
Figure 4-28. DMA_CHMAP3 Register..................................................................................................................................... 151
Figure 5-1. Digital I/O Pads..................................................................................................................................................... 154
Figure 5-2. GPIODATA Write Example.................................................................................................................................... 155
Figure 5-3. GPIODATA Read Example....................................................................................................................................155
Figure 5-4. GPIODATA Register.............................................................................................................................................. 159
Figure 5-5. GPIODIR Register.................................................................................................................................................160
Figure 5-6. GPIOIS Register....................................................................................................................................................161
Figure 5-7. GPIOIBE Register................................................................................................................................................. 162
Figure 5-8. GPIOIEV Register................................................................................................................................................. 163
Figure 5-9. GPIOIM Register................................................................................................................................................... 164
Figure 5-11. GPIOMIS Register...............................................................................................................................................166
Figure 5-13. GPIO_TRIG_EN Register................................................................................................................................... 168
Figure 6-1. UART Module Block Diagram................................................................................................................................173
Figure 6-2. UART Character Frame.........................................................................................................................................173
Figure 6-3. UARTDR Register................................................................................................................................................. 180
Figure 6-4. UARTRSR_UARTECR Register........................................................................................................................... 182
Figure 6-5. UARTFR Register..................................................................................................................................................184
Figure 6-6. UARTIBRD Register..............................................................................................................................................186
Figure 6-7. UARTFBRD Register.............................................................................................................................................187
Figure 6-8. UARTLCRH Register.............................................................................................................................................188
Figure 6-9. UARTCTL Register................................................................................................................................................190
Figure 6-10. UARTIFLS Register.............................................................................................................................................192
Figure 6-11. UARTIM Register.................................................................................................................................................193
Figure 6-12. UARTRIS Register.............................................................................................................................................. 195
Figure 6-13. UARTMIS Register..............................................................................................................................................197
Figure 6-14. UARTICR Register.............................................................................................................................................. 200
Figure 6-15. UARTDMACTL Register......................................................................................................................................202
Figure 7-1. I2C Block Diagram................................................................................................................................................ 205
Figure 7-2. I2C Bus Configuration........................................................................................................................................... 206
Figure 7-3. START and STOP Conditions............................................................................................................................... 206
Figure 7-4. Complete Data Transfer With a 7-Bit Address...................................................................................................... 207
Figure 7-5. R/S Bit in First Byte............................................................................................................................................... 207
Figure 7-6. Data Validity During Bit Transfer on the I2C Bus...................................................................................................207
Figure 7-7. Master Single TRANSMIT..................................................................................................................................... 214
Figure 7-8. Master Single RECEIVE........................................................................................................................................215
Figure 7-9. Master TRANSMIT of Multiple Data Bytes............................................................................................................ 216
Figure 7-10. Master RECEIVE of Multiple Data Bytes.............................................................................................................217
Figure 7-11. Master RECEIVE with Repeated START after Master TRANSMIT.....................................................................218
Figure 7-12. Master TRANSMIT with Repeated START after Master RECEIVE.....................................................................218
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Figure 7-13. Slave Command Sequence.................................................................................................................................219
Figure 7-14. I2CMSA Register.................................................................................................................................................222
Figure 7-15. I2CMCS Register................................................................................................................................................ 223
Figure 7-16. I2CMDR Register................................................................................................................................................ 228
Figure 7-17. I2CMTPR Register.............................................................................................................................................. 229
Figure 7-18. I2CMIMR Register...............................................................................................................................................230
Figure 7-19. I2CMRIS Register............................................................................................................................................... 232
Figure 7-20. I2CMMIS Register............................................................................................................................................... 235
Figure 7-21. I2CMICR Register............................................................................................................................................... 238
Figure 7-22. I2CMCR Register................................................................................................................................................ 240
Figure 7-23. I2CMCLKOCNT Register.................................................................................................................................... 241
Figure 7-24. I2CMBMON Register...........................................................................................................................................242
Figure 7-25. I2CMBLEN Register............................................................................................................................................ 243
Figure 7-26. I2CMBCNT Register............................................................................................................................................244
Figure 7-27. I2CSOAR Register.............................................................................................................................................. 245
Figure 7-28. I2CSCSR Register.............................................................................................................................................. 246
Figure 7-29. I2CSDR Register.................................................................................................................................................248
Figure 7-30. I2CSIMR Register............................................................................................................................................... 249
Figure 7-31. I2CSRIS Register................................................................................................................................................ 251
Figure 7-32. I2CSMIS Register................................................................................................................................................253
Figure 7-33. I2CSICR Register................................................................................................................................................255
Figure 7-34. I2CSOAR2 Register............................................................................................................................................ 257
Figure 7-35. I2CSACKCTL Register........................................................................................................................................258
Figure 7-36. I2CFIFODATA Register....................................................................................................................................... 259
Figure 7-37. I2CFIFOCTL Register......................................................................................................................................... 260
Figure 7-38. I2CFIFOSTATUS Register...................................................................................................................................262
Figure 7-39. I2CPP Register....................................................................................................................................................264
Figure 7-40. I2CPC Register................................................................................................................................................... 265
Figure 8-1. SPI Block Diagram................................................................................................................................................ 268
Figure 8-2. SPI Full-Duplex Transmission (Example)..............................................................................................................270
Figure 8-3. Phase and Polarity Combinations......................................................................................................................... 271
Figure 8-4. Full-Duplex Single Transfer Format With PHA = 0................................................................................................272
Figure 8-5. Full-Duplex Single Transfer Format With PHA = 1................................................................................................273
Figure 8-6. Contiguous Transfers With SPIEN Kept Active (Two Data Pins Interface Mode)................................................. 275
Figure 8-7. Transmit/Receive Mode With No FIFO Used........................................................................................................ 277
Figure 8-8. Transmit/Receive Mode With Only Receive FIFO Enabled...................................................................................277
Figure 8-11. Buffer Almost Full Level (AFL).............................................................................................................................279
Figure 8-12. Buffer Almost Empty Level (AEL)........................................................................................................................279
Figure 8-13. 3-Pin Mode System Overview............................................................................................................................. 280
Figure 8-14. Flow Chart – Module Initialization....................................................................................................................... 286
Figure 8-15. Flow Chart – Common Transfer Sequence.........................................................................................................287
Figure 8-16. Flow Chart – Transmit and Receive (Master and Slave).....................................................................................288
Figure 8-17. Flow Chart – FIFO Mode Common Sequence (Master)......................................................................................289
Figure 8-20. SPI_SYSCONFIG Register................................................................................................................................. 293
Figure 8-21. SPI_SYSSTATUS Register................................................................................................................................. 294
Figure 8-22. SPI_IRQSTATUS Register.................................................................................................................................. 295
Figure 8-23. SPI_IRQENABLE Register..................................................................................................................................297
Figure 8-24. SPI_MODULCTRL Register................................................................................................................................299
Figure 8-25. SPI_CHCONF Register.......................................................................................................................................300
Figure 8-26. SPI_CHSTAT Register........................................................................................................................................ 303
Figure 8-27. SPI_CHCTRL Register........................................................................................................................................305
Figure 8-28. SPI_TX Register..................................................................................................................................................306
Figure 8-29. SPI_RX Register................................................................................................................................................. 307
Figure 8-30. SPI_XFERLEVEL Register................................................................................................................................. 308
Figure 9-1. GPTM Module Block Diagram...............................................................................................................................310
Figure 9-2. Input Edge-Count Mode Example, Counting Down...............................................................................................315
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Figure 9-3. 16-Bit Input Edge-Time Mode Example.................................................................................................................316
Figure 9-4. 16-Bit PWM Mode Example.................................................................................................................................. 317
Figure 9-5. GPTMCFG Register.............................................................................................................................................. 322
Figure 9-6. GPTMTAMR Register............................................................................................................................................323
Figure 9-7. GPTMTBMR Register............................................................................................................................................325
Figure 9-8. GPTMCTL Register...............................................................................................................................................327
Figure 9-9. GPTMIMR Register............................................................................................................................................... 329
Figure 9-10. GPTMRIS Register..............................................................................................................................................331
Figure 9-11. GPTMMIS Register..............................................................................................................................................333
Figure 9-13. GPTMTAILR Register..........................................................................................................................................337
Figure 9-14. GPTMTBILR Register......................................................................................................................................... 338
Figure 9-16. GPTMTBMATCHR Register................................................................................................................................340
Figure 9-17. GPTMTAPR Register.......................................................................................................................................... 341
Figure 9-18. GPTMTBPR Register.......................................................................................................................................... 342
Figure 9-19. GPTMTAPMR Register....................................................................................................................................... 343
Figure 9-20. GPTMTBPMR Register....................................................................................................................................... 344
Figure 9-22. GPTMTBR Register............................................................................................................................................ 346
Figure 9-23. GPTMTAV Register............................................................................................................................................. 347
Figure 9-24. GPTMTBV Register.............................................................................................................................................348
Figure 9-25. GPTMDMAEV Register.......................................................................................................................................349
Figure 10-1. WDT Module Block Diagram............................................................................................................................... 352
Figure 10-2. WDTLOAD Register............................................................................................................................................ 355
Figure 10-3. WDTVALUE Register.......................................................................................................................................... 356
Figure 10-5. WDTICR Register................................................................................................................................................358
Figure 10-6. WDTRIS Register................................................................................................................................................359
Figure 10-7. WDTTEST Register.............................................................................................................................................360
Figure 10-8. WDTLOCK Register............................................................................................................................................ 361
Figure 10-9. Watchdog Flow Chart..........................................................................................................................................363
Figure 10-10. System Watchdog Recovery Sequence............................................................................................................364
Figure 11-2. MMCHS_CSRE Register.....................................................................................................................................379
Figure 11-3. MMCHS_CON Register.......................................................................................................................................380
Figure 11-4. MMCHS_BLK Register........................................................................................................................................382
Figure 11-5. MMCHS_ARG Register.......................................................................................................................................384
Figure 11-6. MMCHS_CMD Register.......................................................................................................................................385
Figure 11-7. MMCHS_RSP10 Register................................................................................................................................... 388
Figure 11-8. MMCHS_RSP32 Register................................................................................................................................... 389
Figure 11-9. MMCHS_RSP54 Register................................................................................................................................... 390
Figure 11-10. MMCHS_RSP76 Register................................................................................................................................. 391
Figure 11-11. MMCHS_DATA Register.................................................................................................................................... 392
Figure 11-12. MMCHS_PSTATE Register............................................................................................................................... 393
Figure 11-13. MMCHS_HCTL Register................................................................................................................................... 395
Figure 11-15. MMCHS_STAT Register....................................................................................................................................399
Figure 11-16. MMCHS_IE Register......................................................................................................................................... 403
Figure 11-17. MMCHS_ISE Register.......................................................................................................................................405
Figure 12-1. I2S Protocol.........................................................................................................................................................408
Figure 12-2. I2S Module.......................................................................................................................................................... 409
Figure 12-4. AFIFOREV Register............................................................................................................................................ 423
Figure 12-5. WFIFOCTL Register............................................................................................................................................424
Figure 12-6. PDIR Register..................................................................................................................................................... 426
Figure 12-7. RFIFOCTL Register............................................................................................................................................ 428
Figure 12-8. RFIFOSTS Register............................................................................................................................................ 430
Figure 12-9. GBLCTL Register................................................................................................................................................ 431
Figure 12-10. RGBLCTL Register........................................................................................................................................... 433
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Figure 12-11. RMASK Register................................................................................................................................................435
Figure 12-12. RFMT Register.................................................................................................................................................. 436
Figure 12-13. AFSRCTL Register............................................................................................................................................438
Figure 12-14. RTDM Register..................................................................................................................................................440
Figure 12-15. RINTCTL Register.............................................................................................................................................441
Figure 12-16. RSTAT Register.................................................................................................................................................443
Figure 12-17. RSLOT Register................................................................................................................................................ 445
Figure 12-18. REVTCTL Register............................................................................................................................................446
Figure 12-19. XGBLCTL Register............................................................................................................................................447
Figure 12-20. XMASK Register............................................................................................................................................... 449
Figure 12-21. XFMT Register.................................................................................................................................................. 450
Figure 12-22. AFSXCTL Register............................................................................................................................................452
Figure 12-23. ACLKXCTL Register......................................................................................................................................... 454
Figure 12-24. AHCLKXCTL Register.......................................................................................................................................456
Figure 12-25. XTDM Register..................................................................................................................................................457
Figure 12-27. XSTAT Register................................................................................................................................................. 460
Figure 12-28. XSLOT Register................................................................................................................................................ 462
Figure 12-29. XEVTCTL Register............................................................................................................................................463
Figure 12-30. SRCTLn Registers............................................................................................................................................ 464
Figure 12-31. XBUFn Registers...............................................................................................................................................466
Figure 12-32. RBUFn Registers.............................................................................................................................................. 467
Figure 13-1. Architecture of the ADC Module in CC32xx........................................................................................................ 470
Figure 13-2. Operation of the ADC..........................................................................................................................................471
Figure 13-4. ADC_CH0_IRQ_EN Register..............................................................................................................................474
Figure 13-5. ADC_CH2_IRQ_EN Register..............................................................................................................................475
Figure 13-6. ADC_CH4_IRQ_EN Register..............................................................................................................................476
Figure 13-7. ADC_CH6_IRQ_EN Register..............................................................................................................................477
Figure 13-8. ADC_CH0_IRQ_STATUS Register..................................................................................................................... 478
Figure 13-9. ADC_CH2_IRQ_STATUS Register..................................................................................................................... 479
Figure 13-10. ADC_CH4_IRQ_STATUS Register................................................................................................................... 480
Figure 13-11. ADC_CH6_IRQ_STATUS Register................................................................................................................... 481
Figure 13-12. ADC_DMA_MODE_EN Register.......................................................................................................................482
Figure 13-13. ADC_TIMER_CONFIGURATION Register....................................................................................................... 483
Figure 13-14. ADC_TIMER_CURRENT_COUNT Register.....................................................................................................483
Figure 13-15. CHANNEL0FIFODATA Register........................................................................................................................484
Figure 13-16. CHANNEL2FIFODATA Register........................................................................................................................484
Figure 13-17. CHANNEL4FIFODATA Register........................................................................................................................485
Figure 13-18. CHANNEL6FIFODATA Register........................................................................................................................485
Figure 13-21. ADC_CH4_FIFO_LVL Register.........................................................................................................................488
Figure 13-22. ADC_CH6_FIFO_LVL Register.........................................................................................................................489
Figure 13-23. ADC_CH_ENABLE Register............................................................................................................................. 490
Figure 14-1. Camera Module Interfaces.................................................................................................................................. 500
Figure 14-2. Synchronization Signals and Frame Timing........................................................................................................501
Figure 14-3. Synchronization Signals and Data Timing...........................................................................................................501
Figure 14-4. Different Scenarios of CAM_P_HS and CAM_P_VS.......................................................................................... 502
Figure 14-5. CAM_P_HS Toggles Between Pixels in Decimation........................................................................................... 502
Figure 14-6. Parallel Camera Interface State Machine............................................................................................................502
Figure 14-7. FIFO Image Data Format.................................................................................................................................... 503
Figure 14-8. Assertion and Deassertion of the DMA Request Signal......................................................................................505
Figure 14-9. CC_SYSCONFIG Register..................................................................................................................................508
Figure 14-10. CC_SYSSTATUS Register................................................................................................................................ 509
Figure 14-11. CC_IRQSTATUS Register.................................................................................................................................510
Figure 14-12. CC_IRQENABLE Register................................................................................................................................ 513
Figure 14-13. CC_CTRL Register........................................................................................................................................... 515
Figure 14-14. CC_CTRL_DMA Register................................................................................................................................. 518
Figure 14-15. CC_CTRL_XCLK Register................................................................................................................................ 519
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Figure 14-16. CC_FIFODATA Register....................................................................................................................................520
Figure 15-1. Power Management Unit Configuration.............................................................................................................. 531
Figure 15-2. Sleep Modes....................................................................................................................................................... 533
Figure 15-3. Power Management Control Architecture in CC32xx..........................................................................................535
Figure 15-4. CAMCLKCFG Register....................................................................................................................................... 545
Figure 15-5. CAMCLKEN Register.......................................................................................................................................... 546
Figure 15-6. CAMSWRST Register......................................................................................................................................... 547
Figure 15-7. MCASPCLKEN Register..................................................................................................................................... 548
Figure 15-8. MCASPSWRST Register.................................................................................................................................... 549
Figure 15-9. SDIOMCLKCFG Register....................................................................................................................................550
Figure 15-11. SDIOMSWRST Register....................................................................................................................................552
Figure 15-12. APSPICLKCFG Register...................................................................................................................................553
Figure 15-13. APSPICLKEN Register..................................................................................................................................... 554
Figure 15-14. APSPISWRST Register.................................................................................................................................... 555
Figure 15-15. DMACLKEN Register........................................................................................................................................ 556
Figure 15-16. DMASWRST Register....................................................................................................................................... 557
Figure 15-17. GPIO0CLKEN Register..................................................................................................................................... 558
Figure 15-19. GPIO1CLKEN Register..................................................................................................................................... 560
Figure 15-21. GPIO2CLKEN Register..................................................................................................................................... 562
Figure 15-22. GPIO2SWRST Register.................................................................................................................................... 563
Figure 15-23. GPIO3CLKEN Register..................................................................................................................................... 564
Figure 15-24. GPIO3SWRST Register.................................................................................................................................... 565
Figure 15-25. GPIO4CLKEN Register..................................................................................................................................... 566
Figure 15-26. GPIO4SWRST Register.................................................................................................................................... 567
Figure 15-27. WDTCLKEN Register........................................................................................................................................568
Figure 15-28. WDTSWRST Register.......................................................................................................................................569
Figure 15-29. UART0CLKEN Register.................................................................................................................................... 570
Figure 15-30. UART0SWRST Register................................................................................................................................... 571
Figure 15-31. UART1CLKEN Register.................................................................................................................................... 572
Figure 15-32. UART1SWRST Register................................................................................................................................... 573
Figure 15-33. GPT0CLKCFG Register.................................................................................................................................... 574
Figure 15-34. GPT0SWRST Register......................................................................................................................................575
Figure 15-35. GPT1CLKEN Register.......................................................................................................................................576
Figure 15-36. GPT1SWRST Register......................................................................................................................................577
Figure 15-37. GPT2CLKEN Register.......................................................................................................................................578
Figure 15-38. GPT2SWRST Register......................................................................................................................................579
Figure 15-39. GPT3CLKEN Register.......................................................................................................................................580
Figure 15-40. GPT3SWRST Register......................................................................................................................................581
Figure 15-41. MCASPCLKCFG0 Register...............................................................................................................................582
Figure 15-42. MCASPCLKCFG1 Register...............................................................................................................................583
Figure 15-43. I2CLCKEN Register.......................................................................................................................................... 584
Figure 15-44. I2CSWRST Register......................................................................................................................................... 585
Figure 15-45. LPDSREQ Register...........................................................................................................................................586
Figure 15-46. TURBOREQ Register........................................................................................................................................587
Figure 15-47. DSLPWAKECFG Register.................................................................................................................................588
Figure 15-48. DSLPTIMRCFG Register.................................................................................................................................. 589
Figure 15-49. SLPWAKEEN Register......................................................................................................................................590
Figure 15-50. SLPTMRCFG Register......................................................................................................................................591
Figure 15-51. WAKENWP Register......................................................................................................................................... 592
Figure 15-52. RCM_IS Register.............................................................................................................................................. 593
Figure 15-53. RCM_IEN Register............................................................................................................................................594
Figure 16-1. Board Configuration to Use Pins 45 and 52........................................................................................................ 599
Figure 16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals........................................................................... 600
Figure 16-3. I/O Pad Data and Control Path Architecture in CC32xx......................................................................................620
Figure 16-4. Wake on Pad for Hibernate Mode....................................................................................................................... 625
Figure 17-1. AES Block Diagram.............................................................................................................................................629
Figure 17-2. AES - ECB Feedback Mode................................................................................................................................632
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Figure 17-3. AES - CBC Feedback Mode................................................................................................................................633
Figure 17-4. AES Encryption With CTR/ICM Mode................................................................................................................. 634
Figure 17-5. AES - CFB Feedback Mode................................................................................................................................ 635
Figure 17-6. AES - F8 Mode....................................................................................................................................................636
Figure 17-7. AES - XTS Operation.......................................................................................................................................... 637
Figure 17-8. AES - F9 Operation.............................................................................................................................................638
Figure 17-9. AES - CBC-MAC Authentication Mode............................................................................................................... 639
Figure 17-10. AES - GCM Operation.......................................................................................................................................640
Figure 17-11. AES - CCM Operation....................................................................................................................................... 641
Figure 17-12. AES Polling Mode............................................................................................................................................. 645
Figure 17-13. AES Interrupt Service........................................................................................................................................647
Figure 17-14. AES_KEY2_6 Register......................................................................................................................................650
Figure 17-15. AES_KEY2_7 Register......................................................................................................................................650
Figure 17-16. AES_KEY2_4 Register......................................................................................................................................651
Figure 17-17. AES_KEY2_5 Register......................................................................................................................................651
Figure 17-18. AES_KEY2_2 Register......................................................................................................................................652
Figure 17-19. AES_KEY2_3 Register......................................................................................................................................652
Figure 17-20. AES_KEY2_0 Register......................................................................................................................................653
Figure 17-21. AES_KEY2_1 Register......................................................................................................................................653
Figure 17-22. AES_KEY1_6 Register......................................................................................................................................654
Figure 17-23. AES_KEY1_7 Register......................................................................................................................................654
Figure 17-24. AES_KEY1_4 Register......................................................................................................................................655
Figure 17-25. AES_KEY1_5 Register......................................................................................................................................655
Figure 17-26. AES_KEY1_2 Register......................................................................................................................................656
Figure 17-27. AES_KEY1_3 Register......................................................................................................................................656
Figure 17-28. AES_KEY1_0 Register......................................................................................................................................657
Figure 17-29. AES_KEY1_1 Register......................................................................................................................................657
Figure 17-30. AES_IV_IN_0 Register......................................................................................................................................658
Figure 17-31. AES_IV_IN_1 Register......................................................................................................................................658
Figure 17-32. AES_IV_IN_2 Register......................................................................................................................................659
Figure 17-33. AES_IV_IN_3 Register......................................................................................................................................659
Figure 17-34. AES_CTRL Register......................................................................................................................................... 660
Figure 17-35. AES_C_LENGTH_0 Register............................................................................................................................663
Figure 17-36. AES_C_LENGTH_1 Register............................................................................................................................664
Figure 17-37. AES_AUTH_LENGTH Register........................................................................................................................ 665
Figure 17-38. AES_DATA_IN_0 Register................................................................................................................................ 666
Figure 17-39. AES_DATA_IN_1 Register................................................................................................................................ 666
Figure 17-40. AES_DATA_IN_2 Register................................................................................................................................ 667
Figure 17-41. AES_DATA_IN_3 Register................................................................................................................................ 667
Figure 17-44. AES_TAG_OUT_2 Register..............................................................................................................................669
Figure 17-45. AES_TAG_OUT_3 Register..............................................................................................................................669
Figure 17-46. AES_REVISION Register..................................................................................................................................670
Figure 17-47. AES_SYSCONFIG Register..............................................................................................................................672
Figure 17-48. AES_IRQSTATUS Register...............................................................................................................................673
Figure 17-49. AES_IRQENABLE Register.............................................................................................................................. 674
Figure 17-50. CRYPTOCLKEN Register................................................................................................................................. 675
Figure 17-51. DTHE_AES_IM Register................................................................................................................................... 676
Figure 17-52. DTHE_AES_RIS Register................................................................................................................................. 677
Figure 17-53. DTHE_AES_MIS Register.................................................................................................................................678
Figure 17-54. DTHE_AES_IC Register................................................................................................................................... 679
Figure 18-1. DES Block Diagram.............................................................................................................................................683
Figure 18-2. DES – ECB Feedback Mode...............................................................................................................................685
Figure 18-3. DES3DES – CBC Feedback Mode..................................................................................................................... 685
Figure 18-4. DES3DES – CFB Feedback Mode......................................................................................................................686
Figure 18-5. DES Polling Mode............................................................................................................................................... 688
Figure 18-6. DES Interrupt Service..........................................................................................................................................689
Figure 18-7. DES Context Input Event Service....................................................................................................................... 690
Figure 18-8. DTHE_DES_IM Register.....................................................................................................................................692
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Figure 18-9. DTHE_DES_RIS Register...................................................................................................................................693
Figure 18-10. DTHE_DES_MIS Register................................................................................................................................ 694
Figure 18-11. DTHE_DES_IC Register....................................................................................................................................695
Figure 18-12. DES_KEY3_L Register..................................................................................................................................... 696
Figure 18-13. DES_KEY3_H Register.....................................................................................................................................697
Figure 18-14. DES_KEY2_L Register..................................................................................................................................... 698
Figure 18-15. DES_KEY2_H Register.....................................................................................................................................699
Figure 18-16. DES_KEY1_L Register..................................................................................................................................... 700
Figure 18-17. DES_KEY1_H Register.....................................................................................................................................701
Figure 18-18. DES_IV_L Register........................................................................................................................................... 702
Figure 18-19. DES_IV_H Register...........................................................................................................................................703
Figure 18-20. DES_CTRL Register......................................................................................................................................... 704
Figure 18-22. DES_DATA_L Register......................................................................................................................................706
Figure 18-23. DES_DATA_H Register..................................................................................................................................... 707
Figure 18-24. DES_SYSCONFIG Register............................................................................................................................. 708
Figure 18-25. DES_IRQSTATUS Register...............................................................................................................................709
Figure 19-1. SHA/MD5 Module Block Diagram....................................................................................................................... 712
Figure 19-2. SHA/MD5 Polling Mode.......................................................................................................................................721
Figure 19-3. SHA/MD5 Interrupt Subroutine............................................................................................................................722
Figure 19-5. SHAMD5_ODIGEST_A Register........................................................................................................................ 727
Figure 19-6. SHAMD5_ODIGEST_B Register........................................................................................................................ 728
Figure 19-7. SHAMD5_ODIGEST_C Register........................................................................................................................ 729
Figure 19-8. SHAMD5_ODIGEST_D Register........................................................................................................................ 730
Figure 19-9. SHAMD5_ODIGEST_E Register........................................................................................................................ 731
Figure 19-10. SHAMD5_ODIGEST_F Register.......................................................................................................................732
Figure 19-11. SHAMD5_ODIGEST_G Register...................................................................................................................... 733
Figure 19-12. SHAMD5_ODIGEST_H Register...................................................................................................................... 734
Figure 19-13. SHAMD5_IDIGEST_A Register........................................................................................................................ 736
Figure 19-14. SHAMD5_IDIGEST_B Register........................................................................................................................ 737
Figure 19-15. SHAMD5_IDIGEST_C Register........................................................................................................................ 738
Figure 19-16. SHAMD5_IDIGEST_D Register........................................................................................................................ 739
Figure 19-17. SHAMD5_IDIGEST_E Register........................................................................................................................ 740
Figure 19-18. SHAMD5_IDIGEST_F Register........................................................................................................................ 741
Figure 19-19. SHAMD5_IDIGEST_G Register........................................................................................................................742
Figure 19-20. SHAMD5_IDIGEST_H Register........................................................................................................................ 743
Figure 19-21. SHAMD5_DIGEST_COUNT Register...............................................................................................................744
Figure 19-23. SHAMD5_LENGTH Register............................................................................................................................ 747
Figure 19-24. SHAMD5_DATA0_IN Register.......................................................................................................................... 749
Figure 19-25. SHAMD5_DATA1_IN Register.......................................................................................................................... 750
Figure 19-26. SHAMD5_DATA2_IN Register.......................................................................................................................... 751
Figure 19-27. SHAMD5_DATA3_IN Register.......................................................................................................................... 752
Figure 19-28. SHAMD5_DATA4_IN Register.......................................................................................................................... 753
Figure 19-29. SHAMD5_DATA5_IN Register.......................................................................................................................... 754
Figure 19-30. SHAMD5_DATA6_IN Register.......................................................................................................................... 755
Figure 19-31. SHAMD5_DATA7_IN Register.......................................................................................................................... 756
Figure 19-32. SHAMD5_DATA8_IN Register.......................................................................................................................... 757
Figure 19-33. SHAMD5_DATA9_IN Register.......................................................................................................................... 758
Figure 19-34. SHAMD5_DATA10_IN Register........................................................................................................................ 759
Figure 19-35. SHAMD5_DATA11_IN Register.........................................................................................................................760
Figure 19-36. SHAMD5_DATA12_IN Register........................................................................................................................ 761
Figure 19-37. SHAMD5_DATA13_IN Register........................................................................................................................ 762
Figure 19-38. SHAMD5_DATA14_IN Register........................................................................................................................ 763
Figure 19-39. SHAMD5_DATA15_IN Register........................................................................................................................ 764
Figure 19-40. SHAMD5_SYSCONFIG Register......................................................................................................................765
Figure 19-41. SHAMD5_IRQSTATUS Register....................................................................................................................... 766
Figure 19-42. SHAMD5_IRQENABLE Register...................................................................................................................... 767
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Figure 19-43. DTHE_SHA_IM Register...................................................................................................................................768
Figure 19-44. DTHE_SHA_RIS Register.................................................................................................................................769
Figure 19-45. DTHE_SHA_MIS Register................................................................................................................................ 770
Figure 19-46. DTHE_SHA_IC Register................................................................................................................................... 771
Figure 20-1. CRCCTRL Register.............................................................................................................................................778
Figure 20-2. CRCSEED Register............................................................................................................................................ 780
Figure 20-3. CRCDIN Register................................................................................................................................................ 781
Figure 20-4. CRCRSLTPP Register.........................................................................................................................................782
Figure 21-1. FMA Register...................................................................................................................................................... 787
Figure 21-2. FMD Register...................................................................................................................................................... 788
Figure 21-3. FMC Register...................................................................................................................................................... 789
Figure 21-4. FCRIS Register................................................................................................................................................... 791
Figure 21-5. FCIM Register..................................................................................................................................................... 793
Figure 21-6. FCMISC Register................................................................................................................................................ 795
Figure 21-7. FMC2 Register.................................................................................................................................................... 797
Figure 21-8. FWBVAL Register................................................................................................................................................798
Figure 21-9. FWBn Register.................................................................................................................................................... 799
Figure 21-10. CC323xSF Boot Flow........................................................................................................................................800
Figure 21-11. Flash Memory Partition......................................................................................................................................801
Figure 21-12. User Application Image Binary Structure on Serial Flash................................................................................. 802
Figure 21-13. On-Chip Flash Programming and Update......................................................................................................... 804
Figure 21-14. Flash Debug Image Layout............................................................................................................................... 805
Figure 23-2. DMA_IMS Register..............................................................................................................................................812
Figure 23-4. DMA_ICR Register..............................................................................................................................................816
Figure 23-5. DMA_MIS Register..............................................................................................................................................818
Figure 23-6. DMA_RIS Register.............................................................................................................................................. 820
Figure 23-7. GPTTRIGSEL Register....................................................................................................................................... 822
List of Tables
Table 1-1. Register Bit Accessibility and Initial Condition.......................................................................................................... 25
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use.................................................................................45
Table 2-2. Processor Register Map........................................................................................................................................... 46
Table 2-3. PSR Register Combinations..................................................................................................................................... 48
Table 2-4. Memory Map............................................................................................................................................................. 50
Table 2-5. SRAM Memory Bit-Banding Regions........................................................................................................................51
Table 2-6. Exception Types........................................................................................................................................................55
Table 2-7. CC32xx Application Processor Interrupts................................................................................................................. 55
Table 2-8. Faults........................................................................................................................................................................ 59
Table 2-9. Fault Status and Fault Address Registers................................................................................................................ 60
Table 2-10. Cortex®-M4 Instruction Summary...........................................................................................................................64
Table 3-1. Core Peripheral Register Regions............................................................................................................................ 70
Table 3-2. Peripherals Register Map......................................................................................................................................... 72
Table 3-3. Cortex Registers....................................................................................................................................................... 75
Table 3-4. ACTLR Register Field Descriptions.......................................................................................................................... 76
Table 3-5. STCTRL Register Field Descriptions........................................................................................................................78
Table 3-6. STRELOAD Register Field Descriptions...................................................................................................................80
Table 3-7. STCURRENT Register Field Descriptions................................................................................................................81
Table 3-8. EN_0 to EN_6 Register Field Descriptions...............................................................................................................82
Table 3-9. DIS_0 to DIS_6 Register Field Descriptions.............................................................................................................83
Table 3-10. PEND_0 to PEND_6 Register Field Descriptions...................................................................................................84
Table 3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions.........................................................................................85
Table 3-12. ACTIVE_0 to ACTIVE_6 Register Field Descriptions.............................................................................................86
Table 3-13. PRI_0 to PRI_49 Register Field Descriptions.........................................................................................................87
Table 3-14. CPUID Register Field Descriptions.........................................................................................................................88
Table 3-15. INTCTRL Register Field Descriptions.....................................................................................................................89
Table 3-16. VTABLE Register Field Descriptions.......................................................................................................................92
Table 3-17. APINT Register Field Descriptions......................................................................................................................... 93
Table 3-18. SYSCTRL Register Field Descriptions................................................................................................................... 95
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Table 3-19. CFGCTRL Register Field Descriptions...................................................................................................................96
Table 3-20. SYSPRI1 Register Field Descriptions.....................................................................................................................98
Table 3-21. SYSPRI2 Register Field Descriptions.....................................................................................................................99
Table 3-22. SYSPRI3 Register Field Descriptions...................................................................................................................100
Table 3-23. SYSHNDCTRL Register Field Descriptions..........................................................................................................101
Table 3-24. FAULTSTAT Register Field Descriptions.............................................................................................................. 105
Table 3-25. HFAULTSTAT Register Field Descriptions............................................................................................................109
Table 3-26. FAULTDDR Register Field Descriptions................................................................................................................110
Table 3-27. SWTRIG Register Field Descriptions.................................................................................................................... 111
Table 4-1. DMA Channel Assignment...................................................................................................................................... 115
Table 4-2. Channel Control Memory........................................................................................................................................ 116
Table 4-3. Individual Control Structure.....................................................................................................................................117
Table 4-4. 8-Bit Data Peripheral Configuration........................................................................................................................ 122
Table 4-5. µDMA Register Map................................................................................................................................................123
Table 4-6. DM Registers.......................................................................................................................................................... 124
Table 4-7. DMA_SRCENDP Register Field Descriptions........................................................................................................ 125
Table 4-8. DMA_DSTENDP Register Field Descriptions.........................................................................................................125
Table 4-9. DMA_CHCTL Register Field Descriptions..............................................................................................................126
Table 4-10. DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers..............................................................................129
Table 4-11. DMA_STAT Register Field Descriptions................................................................................................................130
Table 4-12. DMA_CFG Register Field Descriptions................................................................................................................ 131
Table 4-13. DMA_CTLBASE Register Field Descriptions........................................................................................................132
Table 4-14. DMA_ALTBASE Register Field Descriptions........................................................................................................ 133
Table 4-15. DMA_WAITSTAT Register Field Descriptions.......................................................................................................134
Table 4-16. DMA_SWREQ Register Field Descriptions.......................................................................................................... 135
Table 4-17. DMA_USEBURSTSET Register Field Descriptions............................................................................................. 136
Table 4-18. DMA_USEBURSTCLR Register Field Descriptions............................................................................................. 137
Table 4-19. DMA_REQMASKSET Register Field Descriptions...............................................................................................138
Table 4-20. DMA_REQMASKCLR Register Field Descriptions...............................................................................................139
Table 4-21. DMA_ENASET Register Field Descriptions..........................................................................................................140
Table 4-22. DMA_ENACLR Register Field Descriptions......................................................................................................... 141
Table 4-23. DMA_ALTSET Register Field Descriptions...........................................................................................................142
Table 4-24. DMA_ALTCLR Register Field Descriptions...........................................................................................................143
Table 4-25. DMA_PRIOSET Register Field Descriptions........................................................................................................ 144
Table 4-26. DMA_PRIOCLR Register Field Descriptions........................................................................................................145
Table 4-27. DMA_ERRCLR Register Field Descriptions......................................................................................................... 146
Table 4-28. DMA_CHASGN Register Field Descriptions.........................................................................................................147
Table 4-29. DMA_CHMAP0 Register Field Descriptions.........................................................................................................148
Table 4-30. DMA_CHMAP1 Register Field Descriptions.........................................................................................................149
Table 4-31. DMA_CHMAP2 Register Field Descriptions.........................................................................................................150
Table 4-32. DMA_CHMAP3 Register Field Descriptions.........................................................................................................151
Table 4-33. DMA_PV Register Field Descriptions................................................................................................................... 152
Table 5-1. GPIO Pad Configuration Examples........................................................................................................................ 157
Table 5-2. GPIO Interrupt Configuration Examples................................................................................................................. 157
Table 5-3. GPIO Registers....................................................................................................................................................... 158
Table 5-4. GPIODATA Register Field Descriptions..................................................................................................................159
Table 5-5. GPIODIR Register Field Descriptions.....................................................................................................................160
Table 5-6. GPIOIS Register Field Descriptions........................................................................................................................161
Table 5-7. GPIOIBE Register Field Descriptions..................................................................................................................... 162
Table 5-8. GPIOIEV Register Field Descriptions..................................................................................................................... 163
Table 5-9. GPIOIM Register Field Descriptions....................................................................................................................... 164
Table 5-10. GPIORIS Register Field Descriptions...................................................................................................................165
Table 5-11. GPIOMIS Register Field Descriptions...................................................................................................................166
Table 5-12. GPIOICR Register Field Descriptions...................................................................................................................167
Table 5-13. GPIO_TRIG_EN Register Field Descriptions....................................................................................................... 168
Table 5-14. GPIO Mapping...................................................................................................................................................... 168
Table 6-1. Flow Control Mode..................................................................................................................................................175
Table 6-2. UART Registers...................................................................................................................................................... 179
Table 6-3. UARTDR Register Field Descriptions..................................................................................................................... 180
Table 6-4. UARTRSR_UARTECR Register Field Descriptions............................................................................................... 182
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Table 6-5. UARTFR Register Field Descriptions......................................................................................................................184
Table 6-6. UARTIBRD Register Field Descriptions..................................................................................................................186
Table 6-7. UARTFBRD Register Field Descriptions.................................................................................................................187
Table 6-8. UARTLCRH Register Field Descriptions.................................................................................................................188
Table 6-9. UARTCTL Register Field Descriptions....................................................................................................................190
Table 6-10. UARTIFLS Register Field Descriptions.................................................................................................................192
Table 6-11. UARTIM Register Field Descriptions.....................................................................................................................193
Table 6-12. UARTRIS Register Field Descriptions.................................................................................................................. 195
Table 6-13. UARTMIS Register Field Descriptions.................................................................................................................. 197
Table 6-14. UARTICR Register Field Descriptions.................................................................................................................. 200
Table 6-15. UARTDMACTL Register Field Descriptions..........................................................................................................202
Table 7-1. I2C Signals (64QFN)...............................................................................................................................................205
Table 7-2. Timer Periods..........................................................................................................................................................210
Table 7-3. I2C Registers.......................................................................................................................................................... 221
Table 7-4. I2CMSA Register Field Descriptions.......................................................................................................................222
Table 7-5. I2CMCS Register Field Descriptions...................................................................................................................... 223
Table 7-6. Write Field Decoding for I2CMCS[6:0].................................................................................................................... 225
Table 7-7. I2CMDR Register Field Descriptions...................................................................................................................... 228
Table 7-8. I2CMTPR Register Field Descriptions.................................................................................................................... 229
Table 7-9. I2CMIMR Register Field Descriptions.....................................................................................................................230
Table 7-10. I2CMRIS Register Field Descriptions................................................................................................................... 232
Table 7-11. I2CMMIS Register Field Descriptions................................................................................................................... 235
Table 7-12. I2CMICR Register Field Descriptions................................................................................................................... 238
Table 7-13. I2CMCR Register Field Descriptions.................................................................................................................... 240
Table 7-14. I2CMCLKOCNT Register Field Descriptions........................................................................................................ 241
Table 7-15. I2CMBMON Register Field Descriptions...............................................................................................................242
Table 7-16. I2CMBLEN Register Field Descriptions................................................................................................................243
Table 7-17. I2CMBCNT Register Field Descriptions................................................................................................................244
Table 7-18. I2CSOAR Register Field Descriptions.................................................................................................................. 245
Table 7-19. I2CSCSR Register Field Descriptions.................................................................................................................. 246
Table 7-20. I2CSDR Register Field Descriptions.....................................................................................................................248
Table 7-21. I2CSIMR Register Field Descriptions................................................................................................................... 249
Table 7-22. I2CSRIS Register Field Descriptions....................................................................................................................251
Table 7-23. I2CSMIS Register Field Descriptions....................................................................................................................253
Table 7-24. I2CSICR Register Field Descriptions....................................................................................................................255
Table 7-25. I2CSOAR2 Register Field Descriptions................................................................................................................ 257
Table 7-26. I2CSACKCTL Register Field Descriptions............................................................................................................258
Table 7-27. I2CFIFODATA Register Field Descriptions........................................................................................................... 259
Table 7-28. I2CFIFOCTL Register Field Descriptions............................................................................................................. 260
Table 7-29. I2CFIFOSTATUS Register Field Descriptions.......................................................................................................262
Table 7-30. I2CPP Register Field Descriptions........................................................................................................................264
Table 7-31. I2CPC Register Field Descriptions....................................................................................................................... 265
Table 8-1. SPI.......................................................................................................................................................................... 269
Table 8-2. Phase and Polarity Combinations...........................................................................................................................271
Table 8-3. Clock Ratio Granularity...........................................................................................................................................275
Table 8-4. Granularity Examples..............................................................................................................................................276
Table 8-5. SPI Word Length WL.............................................................................................................................................. 276
Table 8-6. SPI Registers.......................................................................................................................................................... 292
Table 8-7. SPI_SYSCONFIG Register Field Descriptions.......................................................................................................293
Table 8-8. SPI_SYSSTATUS Register Field Descriptions....................................................................................................... 294
Table 8-9. SPI_IRQSTATUS Register Field Descriptions........................................................................................................ 295
Table 8-10. SPI_IRQENABLE Register Field Descriptions......................................................................................................297
Table 8-11. SPI_MODULCTRL Register Field Descriptions.................................................................................................... 299
Table 8-12. SPI_CHCONF Register Field Descriptions...........................................................................................................300
Table 8-13. SPI_CHSTAT Register Field Descriptions............................................................................................................ 303
Table 8-14. SPI_CHCTRL Register Field Descriptions............................................................................................................305
Table 8-15. SPI_TX Register Field Descriptions......................................................................................................................306
Table 8-16. SPI_RX Register Field Descriptions..................................................................................................................... 307
Table 8-17. SPI_XFERLEVEL Register Field Descriptions..................................................................................................... 308
Table 9-1. Available CCP Pins and PWM Outputs/Signals Pins.............................................................................................. 311
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Table 9-2. General-Purpose Timer Capabilities....................................................................................................................... 311
Table 9-4. 16-Bit Timer With Prescaler Configurations............................................................................................................ 313
Table 9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode................................................................ 314
Table 9-7. Counter Values When the Timer is Enabled in PWM Mode....................................................................................316
Table 9-8. Timer Registers.......................................................................................................................................................321
Table 9-9. GPTMCFG Register Field Descriptions.................................................................................................................. 322
Table 9-10. GPTMTAMR Register Field Descriptions..............................................................................................................323
Table 9-11. GPTMTBMR Register Field Descriptions..............................................................................................................325
Table 9-12. GPTMCTL Register Field Descriptions.................................................................................................................327
Table 9-13. GPTMIMR Register Field Descriptions.................................................................................................................329
Table 9-14. GPTMRIS Register Field Descriptions..................................................................................................................331
Table 9-15. GPTMMIS Register Field Descriptions................................................................................................................. 333
Table 9-16. GPTMICR Register Field Descriptions................................................................................................................. 335
Table 9-17. GPTMTAILR Register Field Descriptions..............................................................................................................337
Table 9-18. GPTMTBILR Register Field Descriptions............................................................................................................. 338
Table 9-21. GPTMTAPR Register Field Descriptions.............................................................................................................. 341
Table 9-22. GPTMTBPR Register Field Descriptions..............................................................................................................342
Table 9-23. GPTMTAPMR Register Field Descriptions........................................................................................................... 343
Table 9-24. GPTMTBPMR Register Field Descriptions...........................................................................................................344
Table 9-25. GPTMTAR Register Field Descriptions.................................................................................................................345
Table 9-26. GPTMTBR Register Field Descriptions................................................................................................................ 346
Table 9-27. GPTMTAV Register Field Descriptions................................................................................................................. 347
Table 9-28. GPTMTBV Register Field Descriptions.................................................................................................................348
Table 9-29. GPTMDMAEV Register Field Descriptions...........................................................................................................349
Table 10-1. WATCHDOG Registers.........................................................................................................................................354
Table 10-2. WDTLOAD Register Field Descriptions................................................................................................................355
Table 10-3. WDTVALUE Register Field Descriptions.............................................................................................................. 356
Table 10-4. WDTCTL Register Field Descriptions...................................................................................................................357
Table 10-5. WDTICR Register Field Descriptions....................................................................................................................358
Table 10-6. WDTRIS Register Field Descriptions....................................................................................................................359
Table 10-7. WDTTEST Register Field Descriptions.................................................................................................................360
Table 10-8. WDTLOCK Register Field Descriptions................................................................................................................361
Table 11-1. Card Types............................................................................................................................................................372
Table 11-2. Throughput Data................................................................................................................................................... 373
Table 11-4. SD-HOST Registers..............................................................................................................................................378
Table 11-5. MMCHS_CSRE Register Field Descriptions.........................................................................................................379
Table 11-6. MMCHS_CON Register Field Descriptions...........................................................................................................380
Table 11-8. MMCHS_ARG Register Field Descriptions...........................................................................................................384
Table 11-9. MMCHS_CMD Register Field Descriptions...........................................................................................................385
Table 11-10. MMCHS_RSP10 Register Field Descriptions..................................................................................................... 388
Table 11-11. MMCHS_RSP32 Register Field Descriptions......................................................................................................389
Table 11-12. MMCHS_RSP54 Register Field Descriptions..................................................................................................... 390
Table 11-13. MMCHS_RSP76 Register Field Descriptions..................................................................................................... 391
Table 11-15. MMCHS_PSTATE Register Field Descriptions...................................................................................................393
Table 11-16. MMCHS_HCTL Register Field Descriptions....................................................................................................... 395
Table 11-17. MMCHS_SYSCTL Register Field Descriptions...................................................................................................396
Table 11-18. MMCHS_STAT Register Field Descriptions........................................................................................................399
Table 11-19. MMCHS_IE Register Field Descriptions............................................................................................................. 403
Table 11-20. MMCHS_ISE Register Field Descriptions...........................................................................................................405
Table 12-1. ulIntFlags Parameter.............................................................................................................................................417
Table 12-2. ulStatFlags Parameter.......................................................................................................................................... 418
Table 12-3. I2S Registers Accessed Through Peripheral Configuration Port..........................................................................421
Table 12-4. I2S Registers Accessed Through DMA Port.........................................................................................................422
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Table 12-5. I2S AFIFO Registers Accessed Through Peripheral Configuration Port.............................................................. 422
Table 12-6. AFIFOREV Register Field Descriptions................................................................................................................423
Table 12-7. WFIFOCTL Register Field Descriptions................................................................................................................424
Table 12-8. PDIR Register Field Descriptions......................................................................................................................... 426
Table 12-9. RFIFOCTL Register Field Descriptions................................................................................................................ 428
Table 12-10. RFIFOSTS Register Field Descriptions.............................................................................................................. 430
Table 12-11. GBLCTL Register Field Descriptions.................................................................................................................. 431
Table 12-12. RGBLCTL Register Field Descriptions............................................................................................................... 433
Table 12-13. RMASK Register Field Descriptions................................................................................................................... 435
Table 12-14. RFMT Register Field Descriptions......................................................................................................................436
Table 12-15. AFSRCTL Register Field Descriptions................................................................................................................438
Table 12-16. RTDM Register Field Descriptions......................................................................................................................440
Table 12-17. RINTCTL Register Field Descriptions.................................................................................................................441
Table 12-18. RSTAT Register Field Descriptions.....................................................................................................................443
Table 12-19. RSLOT Register Field Descriptions....................................................................................................................445
Table 12-20. REVTCTL Register Field Descriptions................................................................................................................446
Table 12-21. XGBLCTL Register Field Descriptions................................................................................................................447
Table 12-22. XMASK Register Field Descriptions................................................................................................................... 449
Table 12-23. XFMT Register Field Descriptions...................................................................................................................... 450
Table 12-24. AFSXCTL Register Field Descriptions................................................................................................................452
Table 12-25. ACLKXCTL Register Field Descriptions............................................................................................................. 454
Table 12-26. AHCLKXCTL Register Field Descriptions...........................................................................................................456
Table 12-27. XTDM Register Field Descriptions......................................................................................................................457
Table 12-28. XINTCTL Register Field Descriptions.................................................................................................................458
Table 12-29. XSTAT Register Field Descriptions.....................................................................................................................460
Table 12-30. XSLOT Register Field Descriptions.................................................................................................................... 462
Table 12-31. XEVTCTL Register Field Descriptions................................................................................................................463
Table 12-32. SRCTLn Register Field Descriptions.................................................................................................................. 464
Table 12-33. XBUFn Register Field Descriptions.................................................................................................................... 466
Table 12-34. RBUFn Register Field Descriptions.................................................................................................................... 467
Table 13-1. ADC Registers...................................................................................................................................................... 471
Table 13-2. ADC_MODULE Registers.....................................................................................................................................472
Table 13-3. ADC_CTRL Register Field Descriptions...............................................................................................................473
Table 13-4. ADC_CH0_IRQ_EN Register Field Descriptions..................................................................................................474
Table 13-5. ADC_CH2_IRQ_EN Register Field Descriptions..................................................................................................475
Table 13-6. ADC_CH4_IRQ_EN Register Field Descriptions..................................................................................................476
Table 13-7. ADC_CH6_IRQ_EN Register Field Descriptions..................................................................................................477
Table 13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions......................................................................................... 478
Table 13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions......................................................................................... 479
Table 13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions....................................................................................... 480
Table 13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions....................................................................................... 481
Table 13-12. ADC_DMA_MODE_EN Register Field Descriptions...........................................................................................482
Table 13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions........................................................................... 483
Table 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions.........................................................................483
Table 13-15. CHANNEL0FIFODATA Register Field Descriptions............................................................................................484
Table 13-16. CHANNEL2FIFODATA Register Field Descriptions............................................................................................484
Table 13-17. CHANNEL4FIFODATA Register Field Descriptions............................................................................................485
Table 13-18. CHANNEL6FIFODATA Register Field Descriptions............................................................................................485
Table 13-19. ADC_CH0_FIFO_LVL Register Field Descriptions.............................................................................................486
Table 13-20. ADC_CH2_FIFO_LVL Register Field Descriptions.............................................................................................487
Table 13-21. ADC_CH4_FIFO_LVL Register Field Descriptions.............................................................................................488
Table 13-22. ADC_CH6_FIFO_LVL Register Field Descriptions.............................................................................................489
Table 13-23. ADC_CH_ENABLE Register Field Descriptions.................................................................................................490
Table 13-24. ulChannel Tags................................................................................................................................................... 491
Table 13-25. ulIntFlags Tags....................................................................................................................................................492
Table 14-1. Image Sensor Interface Signals............................................................................................................................501
Table 14-2. Ratio of the XCLK Frequency Generator..............................................................................................................504
Table 14-3. Camera Registers.................................................................................................................................................507
Table 14-4. CC_SYSCONFIG Register Field Descriptions......................................................................................................508
Table 14-5. CC_SYSSTATUS Register Field Descriptions......................................................................................................509
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Table 14-6. CC_IRQSTATUS Register Field Descriptions.......................................................................................................510
Table 14-7. CC_IRQENABLE Register Field Descriptions...................................................................................................... 513
Table 14-8. CC_CTRL Register Field Descriptions................................................................................................................. 515
Table 14-9. CC_CTRL_DMA Register Field Descriptions....................................................................................................... 518
Table 14-10. CC_CTRL_XCLK Register Field Descriptions....................................................................................................519
Table 15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN)..................534
Table 15-2. Peripheral Macro Table.........................................................................................................................................543
Table 15-3. PRCM Registers................................................................................................................................................... 543
Table 15-4. CAMCLKCFG Register Field Descriptions........................................................................................................... 545
Table 15-5. CAMCLKEN Register Field Descriptions..............................................................................................................546
Table 15-6. CAMSWRST Register Field Descriptions.............................................................................................................547
Table 15-7. MCASPCLKEN Register Field Descriptions......................................................................................................... 548
Table 15-8. MCASPSWRST Register Field Descriptions........................................................................................................ 549
Table 15-9. SDIOMCLKCFG Register Field Descriptions........................................................................................................550
Table 15-10. SDIOMCLKEN Register Field Descriptions........................................................................................................ 551
Table 15-11. SDIOMSWRST Register Field Descriptions........................................................................................................552
Table 15-12. APSPICLKCFG Register Field Descriptions.......................................................................................................553
Table 15-13. APSPICLKEN Register Field Descriptions......................................................................................................... 554
Table 15-14. APSPISWRST Register Field Descriptions........................................................................................................ 555
Table 15-15. DMACLKEN Register Field Descriptions............................................................................................................556
Table 15-16. DMASWRST Register Field Descriptions...........................................................................................................557
Table 15-17. GPIO0CLKEN Register Field Descriptions.........................................................................................................558
Table 15-18. GPIO0SWRST Register Field Descriptions........................................................................................................559
Table 15-19. GPIO1CLKEN Register Field Descriptions.........................................................................................................560
Table 15-20. GPIO1SWRST Register Field Descriptions........................................................................................................561
Table 15-21. GPIO2CLKEN Register Field Descriptions.........................................................................................................562
Table 15-22. GPIO2SWRST Register Field Descriptions........................................................................................................563
Table 15-23. GPIO3CLKEN Register Field Descriptions.........................................................................................................564
Table 15-24. GPIO3SWRST Register Field Descriptions........................................................................................................565
Table 15-25. GPIO4CLKEN Register Field Descriptions.........................................................................................................566
Table 15-26. GPIO4SWRST Register Field Descriptions........................................................................................................567
Table 15-27. WDTCLKEN Register Field Descriptions............................................................................................................568
Table 15-28. WDTSWRST Register Field Descriptions...........................................................................................................569
Table 15-29. UART0CLKEN Register Field Descriptions........................................................................................................ 570
Table 15-30. UART0SWRST Register Field Descriptions....................................................................................................... 571
Table 15-31. UART1CLKEN Register Field Descriptions........................................................................................................ 572
Table 15-32. UART1SWRST Register Field Descriptions....................................................................................................... 573
Table 15-33. GPT0CLKCFG Register Field Descriptions........................................................................................................574
Table 15-34. GPT0SWRST Register Field Descriptions..........................................................................................................575
Table 15-35. GPT1CLKEN Register Field Descriptions...........................................................................................................576
Table 15-36. GPT1SWRST Register Field Descriptions..........................................................................................................577
Table 15-37. GPT2CLKEN Register Field Descriptions...........................................................................................................578
Table 15-38. GPT2SWRST Register Field Descriptions..........................................................................................................579
Table 15-39. GPT3CLKEN Register Field Descriptions...........................................................................................................580
Table 15-40. GPT3SWRST Register Field Descriptions..........................................................................................................581
Table 15-41. MCASPCLKCFG0 Register Field Descriptions...................................................................................................582
Table 15-42. MCASPCLKCFG1 Register Field Descriptions...................................................................................................583
Table 15-43. I2CLCKEN Register Field Descriptions.............................................................................................................. 584
Table 15-44. I2CSWRST Register Field Descriptions............................................................................................................. 585
Table 15-45. LPDSREQ Register Field Descriptions...............................................................................................................586
Table 15-46. TURBOREQ Register Field Descriptions............................................................................................................587
Table 15-47. DSLPWAKECFG Register Field Descriptions.....................................................................................................588
Table 15-48. DSLPTIMRCFG Register Field Descriptions...................................................................................................... 589
Table 15-49. SLPWAKEEN Register Field Descriptions..........................................................................................................590
Table 15-50. SLPTMRCFG Register Field Descriptions..........................................................................................................591
Table 15-51. WAKENWP Register Field Descriptions............................................................................................................. 592
Table 15-52. RCM_IS Register Field Descriptions.................................................................................................................. 593
Table 15-53. RCM_IEN Register Field Descriptions................................................................................................................594
Table 16-1. GPIO Pin Electrical Specifications (25°C) (Except Pins 29, 30, 45, 50, 52, 53)................................................... 597
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Table 16-2. GPIO Pin Electrical Specifications (25°C) For Pins 29, 30, 45, 50, 52, 53........................................................... 597
Table 16-3. Pin Internal Pullup and Pulldown Electrical Specifications (25°C)........................................................................597
Table 16-4. Analog Mux Control Registers and Bits................................................................................................................ 601
Table 16-5. Board-Level Behavior........................................................................................................................................... 602
Table 16-6. GPIO/Pins Available for Application......................................................................................................................603
Table 16-7. Pin Multiplexing.....................................................................................................................................................607
Table 16-8. Pin Groups for Audio Interface (I2S)..................................................................................................................... 617
Table 16-10. Pin Groups for SD-Card Interface....................................................................................................................... 617
Table 16-11. Pad Configuration Registers............................................................................................................................... 618
Table 16-12. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description....................................................... 619
Table 16-13. Recommended Pin Multiplexing Configurations................................................................................................. 621
Table 16-14. Sense-on-Power Configurations.........................................................................................................................626
Table 17-1. Key-Block-Round Combinations...........................................................................................................................631
Table 17-2. Interrupts and Events............................................................................................................................................ 642
Table 17-3. AES Registers.......................................................................................................................................................648
Table 17-4. AES_KEY2_6 Register Field Descriptions............................................................................................................650
Table 17-5. AES_KEY2_7 Register Field Descriptions............................................................................................................650
Table 17-6. AES_KEY2_4 Register Field Descriptions............................................................................................................651
Table 17-7. AES_KEY2_5 Register Field Descriptions............................................................................................................651
Table 17-8. AES_KEY2_2 Register Field Descriptions............................................................................................................652
Table 17-9. AES_KEY2_3 Register Field Descriptions............................................................................................................652
Table 17-10. AES_KEY2_0 Register Field Descriptions..........................................................................................................653
Table 17-11. AES_KEY2_1 Register Field Descriptions..........................................................................................................653
Table 17-12. AES_KEY1_6 Register Field Descriptions..........................................................................................................654
Table 17-13. AES_KEY1_7 Register Field Descriptions..........................................................................................................654
Table 17-14. AES_KEY1_4 Register Field Descriptions..........................................................................................................655
Table 17-15. AES_KEY1_5 Register Field Descriptions..........................................................................................................655
Table 17-16. AES_KEY1_2 Register Field Descriptions..........................................................................................................656
Table 17-17. AES_KEY1_3 Register Field Descriptions..........................................................................................................656
Table 17-18. AES_KEY1_0 Register Field Descriptions..........................................................................................................657
Table 17-19. AES_KEY1_1 Register Field Descriptions..........................................................................................................657
Table 17-20. AES_IV_IN_0 Register Field Descriptions..........................................................................................................658
Table 17-21. AES_IV_IN_1 Register Field Descriptions..........................................................................................................658
Table 17-22. AES_IV_IN_2 Register Field Descriptions..........................................................................................................659
Table 17-23. AES_IV_IN_3 Register Field Descriptions..........................................................................................................659
Table 17-24. AES_CTRL Register Field Descriptions............................................................................................................. 660
Table 17-25. AES_C_LENGTH_0 Register Field Descriptions................................................................................................663
Table 17-26. AES_C_LENGTH_1 Register Field Descriptions................................................................................................664
Table 17-27. AES_AUTH_LENGTH Register Field Descriptions............................................................................................ 665
Table 17-28. AES_DATA_IN_0 Register Field Descriptions.................................................................................................... 666
Table 17-29. AES_DATA_IN_1 Register Field Descriptions.................................................................................................... 666
Table 17-30. AES_DATA_IN_2 Register Field Descriptions.................................................................................................... 667
Table 17-31. AES_DATA_IN_3 Register Field Descriptions.................................................................................................... 667
Table 17-32. AES_TAG_OUT_0 Register Field Descriptions.................................................................................................. 668
Table 17-33. AES_TAG_OUT_1 Register Field Descriptions.................................................................................................. 668
Table 17-34. AES_TAG_OUT_2 Register Field Descriptions.................................................................................................. 669
Table 17-35. AES_TAG_OUT_3 Register Field Descriptions.................................................................................................. 669
Table 17-36. AES_REVISION Register Field Descriptions......................................................................................................670
Table 17-37. AES_SYSCONFIG Register Field Descriptions..................................................................................................672
Table 17-38. AES_IRQSTATUS Register Field Descriptions...................................................................................................673
Table 17-39. AES_IRQENABLE Register Field Descriptions.................................................................................................. 674
Table 17-40. CRYPTOCLKEN Register Field Descriptions..................................................................................................... 675
Table 17-41. DTHE_AES_IM Register Field Descriptions.......................................................................................................676
Table 17-42. DTHE_AES_RIS Register Field Descriptions.....................................................................................................677
Table 17-43. DTHE_AES_MIS Register Field Descriptions.....................................................................................................678
Table 17-44. DTHE_AES_IC Register Field Descriptions....................................................................................................... 679
Table 18-1. Key Repartition..................................................................................................................................................... 682
Table 18-2. DES Global Initialization....................................................................................................................................... 686
Table 18-3. DES Algorithm Type Configuration....................................................................................................................... 686
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Table 18-4. 3DES Algorithm Type Configuration..................................................................................................................... 687
Table 18-5. DES Interrupt Mode.............................................................................................................................................. 689
Table 18-6. DES DMA Mode....................................................................................................................................................689
Table 18-7. DES Register Map................................................................................................................................................ 691
Table 18-8. DTHE_DES_IM Register Field Descriptions.........................................................................................................692
Table 18-9. DTHE_DES_RIS Register Field Descriptions.......................................................................................................693
Table 18-10. DTHE_DES_MIS Register Field Descriptions.................................................................................................... 694
Table 18-11. DTHE_DES_IC Register Field Descriptions........................................................................................................695
Table 18-12. DES_KEY3_L Register Field Descriptions......................................................................................................... 696
Table 18-13. DES_KEY3_H Register Field Descriptions.........................................................................................................697
Table 18-14. DES_KEY2_L Register Field Descriptions......................................................................................................... 698
Table 18-15. DES_KEY2_H Register Field Descriptions.........................................................................................................699
Table 18-16. DES_KEY1_L Register Field Descriptions......................................................................................................... 700
Table 18-17. DES_KEY1_H Register Field Descriptions.........................................................................................................701
Table 18-18. DES_IV_L Register Field Descriptions............................................................................................................... 702
Table 18-19. DES_IV_H Register Field Descriptions...............................................................................................................703
Table 18-20. DES_CTRL Register Field Descriptions............................................................................................................. 704
Table 18-21. DES_LENGTH Register Field Descriptions........................................................................................................705
Table 18-22. DES_DATA_L Register Field Descriptions..........................................................................................................706
Table 18-23. DES_DATA_H Register Field Descriptions.........................................................................................................707
Table 18-24. DES_SYSCONFIG Register Field Descriptions................................................................................................. 708
Table 18-25. DES_IRQSTATUS Register Field Descriptions...................................................................................................709
Table 18-26. DES_IRQENABLE Register Field Descriptions..................................................................................................710
Table 19-1. Interrupts and Events............................................................................................................................................ 713
Table 19-2. SHA/MD5 Module Algorithm Selection................................................................................................................. 714
Table 19-3. Outer Digest Registers..........................................................................................................................................715
Table 19-4. Inner Digest Registers.......................................................................................................................................... 715
Table 19-5. SHA Digest Processed in Three Passes.............................................................................................................. 717
Table 19-6. SHA Digest Processed in One Pass.....................................................................................................................718
Table 19-7. Continuing a Prior HMAC......................................................................................................................................720
Table 19-8. SHA-1 Apply on the Key....................................................................................................................................... 720
Table 19-9. Interrupt Mode.......................................................................................................................................................721
Table 19-10. DMA Mode.......................................................................................................................................................... 721
Table 19-11. SHA-MD5 Registers............................................................................................................................................723
Table 19-12. SHAMD5_ODIGEST_A Register Field Descriptions.......................................................................................... 727
Table 19-13. SHAMD5_ODIGEST_B Register Field Descriptions.......................................................................................... 728
Table 19-14. SHAMD5_ODIGEST_C Register Field Descriptions.......................................................................................... 729
Table 19-15. SHAMD5_ODIGEST_D Register Field Descriptions.......................................................................................... 730
Table 19-16. SHAMD5_ODIGEST_E Register Field Descriptions.......................................................................................... 731
Table 19-17. SHAMD5_ODIGEST_F Register Field Descriptions...........................................................................................732
Table 19-18. SHAMD5_ODIGEST_G Register Field Descriptions..........................................................................................733
Table 19-19. SHAMD5_ODIGEST_H Register Field Descriptions.......................................................................................... 734
Table 19-20. SHAMD5_IDIGEST_A Register Field Descriptions............................................................................................ 736
Table 19-21. SHAMD5_IDIGEST_B Register Field Descriptions............................................................................................ 737
Table 19-22. SHAMD5_IDIGEST_C Register Field Descriptions............................................................................................738
Table 19-23. SHAMD5_IDIGEST_D Register Field Descriptions............................................................................................739
Table 19-24. SHAMD5_IDIGEST_E Register Field Descriptions............................................................................................ 740
Table 19-25. SHAMD5_IDIGEST_F Register Field Descriptions............................................................................................ 741
Table 19-26. SHAMD5_IDIGEST_G Register Field Descriptions............................................................................................742
Table 19-27. SHAMD5_IDIGEST_H Register Field Descriptions............................................................................................743
Table 19-28. SHAMD5_DIGEST_COUNT Register Field Descriptions...................................................................................744
Table 19-29. SHAMD5_MODE Register Field Descriptions.................................................................................................... 745
Table 19-30. SHAMD5_LENGTH Register Field Descriptions................................................................................................ 747
Table 19-31. SHAMD5_DATA0_IN Register Field Descriptions.............................................................................................. 749
Table 19-32. SHAMD5_DATA1_IN Register Field Descriptions.............................................................................................. 750
Table 19-33. SHAMD5_DATA2_IN Register Field Descriptions.............................................................................................. 751
Table 19-34. SHAMD5_DATA3_IN Register Field Descriptions.............................................................................................. 752
Table 19-35. SHAMD5_DATA4_IN Register Field Descriptions.............................................................................................. 753
Table 19-36. SHAMD5_DATA5_IN Register Field Descriptions.............................................................................................. 754
Table 19-37. SHAMD5_DATA6_IN Register Field Descriptions.............................................................................................. 755
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Table 19-38. SHAMD5_DATA7_IN Register Field Descriptions.............................................................................................. 756
Table 19-39. SHAMD5_DATA8_IN Register Field Descriptions.............................................................................................. 757
Table 19-40. SHAMD5_DATA9_IN Register Field Descriptions.............................................................................................. 758
Table 19-41. SHAMD5_DATA10_IN Register Field Descriptions............................................................................................ 759
Table 19-42. SHAMD5_DATA11_IN Register Field Descriptions.............................................................................................760
Table 19-43. SHAMD5_DATA12_IN Register Field Descriptions............................................................................................ 761
Table 19-44. SHAMD5_DATA13_IN Register Field Descriptions............................................................................................ 762
Table 19-45. SHAMD5_DATA14_IN Register Field Descriptions............................................................................................ 763
Table 19-46. SHAMD5_DATA15_IN Register Field Descriptions............................................................................................ 764
Table 19-47. SHAMD5_SYSCONFIG Register Field Descriptions..........................................................................................765
Table 19-48. SHAMD5_IRQSTATUS Register Field Descriptions...........................................................................................766
Table 19-49. SHAMD5_IRQENABLE Register Field Descriptions.......................................................................................... 767
Table 19-50. DTHE_SHA_IM Register Field Descriptions.......................................................................................................768
Table 19-51. DTHE_SHA_RIS Register Field Descriptions.....................................................................................................769
Table 19-52. DTHE_SHA_MIS Register Field Descriptions.................................................................................................... 770
Table 19-53. DTHE_SHA_IC Register Field Descriptions....................................................................................................... 771
Table 20-1. Endian Configuration............................................................................................................................................ 775
Table 20-2. Endian Configuration With Bit Reversal................................................................................................................775
Table 20-3. CRC Registers......................................................................................................................................................777
Table 20-4. CRCCTRL Register Field Descriptions.................................................................................................................778
Table 20-5. CRCSEED Register Field Descriptions................................................................................................................ 780
Table 20-6. CRCDIN Register Field Descriptions....................................................................................................................781
Table 20-7. CRCRSLTPP Register Field Descriptions.............................................................................................................782
Table 21-1. Flash Registers..................................................................................................................................................... 786
Table 21-2. FMA Register Field Descriptions.......................................................................................................................... 787
Table 21-3. FMD Register Field Descriptions.......................................................................................................................... 788
Table 21-4. FMC Register Field Descriptions.......................................................................................................................... 789
Table 21-5. FCRIS Register Field Descriptions....................................................................................................................... 791
Table 21-6. FCIM Register Field Descriptions......................................................................................................................... 793
Table 21-7. FCMISC Register Field Descriptions.................................................................................................................... 795
Table 21-8. FMC2 Register Field Descriptions........................................................................................................................ 797
Table 21-9. FWBVAL Register Field Descriptions....................................................................................................................798
Table 21-10. FWBn Register Field Descriptions......................................................................................................................799
Table A-1. Peripheral Samples................................................................................................................................................ 807
Table 23-1. CC323x Device Miscellaneous Register Summary.............................................................................................. 809
Table 23-2. DMA_IMR Register Field Descriptions................................................................................................................. 810
Table 23-3. DMA_IMS Register Field Descriptions..................................................................................................................812
Table 23-4. DMA_IMC Register Field Descriptions................................................................................................................. 814
Table 23-5. DMA_ICR Register Field Descriptions..................................................................................................................816
Table 23-6. DMA_MIS Register Field Descriptions..................................................................................................................818
Table 23-7. DMA_RIS Register Field Descriptions..................................................................................................................820
Table 23-8. GPTTRIGSEL Register Field Descriptions........................................................................................................... 822
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Preface

Read This First

This technical reference manual describes the modules and peripherals of the CC323x SimpleLink™ Wi-Fi
®
microcontroller (MCU). Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals may be present on all devices. Pin functions, internal signal connections, and operational parameters differ from device to device. The user should consult the device­specific data sheet for these details.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature; it explains the features and functionality of each module, and it also explains how to use them. For each feature, references are given to the documentation for the driver of the corresponding operating systems. This document does not contain performance characteristics of the device or modules, which are gathered in the corresponding device data sheets.

Register Bit Conventions

Table 1-1 lists each register with a key indicating the accessibility of the individual bit, and the initial condition.
Table 1-1. Register Bit Accessibility and Initial Condition
Key Bit Accessibility
rw Read/write
r Read only r0 Read as 0 r1 Read as 1
w Write only w0 Write as 0 w1 Write as 1 (w) No register bit implemented; writing 1 results in a pulse. The register bit is always read as 0. h0 Cleared by hardware h1 Set by hardware
-0, -1 Condition after PUC
-(0), -(1) Condition after POR
-[0], -[1] Condition after BOR
-{0},-{1} Condition after Brownout

Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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Related Documentation

The following related documents about the CC323x device can be accessed at these links from Texas Instruments™: http://www.ti.com/simplelinkwifi and http://www.ti.com/simplelinkwifi-wiki
1. SimpleLink™ Wi-Fi® CC3x3x Networking Subsystem Power Management
2. Cortex-M3/M4F Instruction Set Technical User's Manual
Note
This list of documents was current as of publication date. Check the website for additional documentation, application notes, and white papers.
Additional related documentation follows:
1. Arm® Cortex®-M4 Processor Technical Reference Manual (ARM 100166_0001_00).
2. Cortex-M4 Devices Generic User Guide (ARM DUI 0553A).
3. Armv7-M Architecture Reference Manual (ARM DDI 0403E.b).
4. Bluetooth® Special Interest Group (SIG) Bluetooth Core Specifications.
5. Texas Instruments Bluetooth® low energy (BLE) Wiki.
6. Arm® Debug Interface V5 Architecture Specification (see Arm.com).
7. The Institute of Electrical and Electronic Engineers, Inc., IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a 1993 and Supplement Std. 1149.1b 1994 (see IEEExplore.ieee.org).
8. The Institute of Electrical and Electronic Engineers, Inc., IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture (see IEEExplore.ieee.org).
9. National Institute of Standards and Technology, NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation Methods and Techniques (see NIST.gov).
10.National Institute of Standards and Technology, NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC (see NIST.gov).
11.National Institute of Standards and Technology, FIPS 197, Advanced Encryption Standard (AES) (see
NIST.gov).

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Support Forum TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki
TI Product Information Centers (PIC)
Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
All technical support is channeled through the TI Product Information Centers (PIC). To send an email request, enter your contact information and your request to PIC
request form.
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Trademarks

SimpleLink™, Texas Instruments™, TI E2E™, Internet-on-a chip™, and are trademarks of Texas Instruments. AMBA™ and CoreSight™ are trademarks of Arm Limited. Wi-Fi® and Wi-Fi Direct®, and are registered trademarks of Wi-Fi Alliance. Arm®, Cortex®, Thumb®, and are registered trademarks of Arm Limited. Bluetooth® are registered trademarks of Bluetooth SIG, Inc.. All other trademarks are the property of their respective owners.
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Chapter 1

Architecture Overview

1.1 Introduction.................................................................................................................................................................30
1.2 Architecture Overview............................................................................................................................................... 31
1.3 Functional Overview.................................................................................................................................................. 32
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1.1 Introduction

The CC323x device is part of the SimpleLink™ microcontroller (MCU) platform which consists of Wi-Fi®, Bluetooth® low energy, Sub-1 GHz and host MCUs, which all share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink™ platform lets you add any combination of the devices from the portfolio into your design. The ultimate goal of the SimpleLink™ platform is to achieve 100 percent code reuse when your design requirements change. For more information, visit www.ti.com/simplelink.
The applications MCU subsystem contains an industry-standard Arm Cortex-M4 processor core running at 80 MHz. The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD, UART, SPI, I2C, and 4-channel ADC. The CC32xx family of devices includes flexible embedded RAM for code and data, and ROM with external serial flash bootloader and peripheral drivers.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a chip™, and contains an additional dedicated Arm MCU that completely offloads the applications MCU. This subsystem includes an 802.11 a/b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit encryption. The CC32xx device supports Station, Access Point, and Wi-Fi Direct® modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a chip™ includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols.
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Pin
Mux
Flash SPI
Apps SPI
I2C
Audio Serial Port
Camera Interface
(8-bit Parallel)
SD Card I/F
(host)
GPIO A0
GPIO A1
GPIO A2
GPIO A3
UART A0
UART A1
ADC
Timer A
Timer B
GPT A0
Timer A
Timer B
GPT A1
Timer A
Timer B
GPT A2
Timer A
Timer B
GPT A3
APB
Bus
Bus Matrix Multi-Layer
AHB
SRAM
Zero Wait State
4-Way Interleaved
Upto 256 Kb Code + Data
ROM
64 Kb
Device Initialization
Bootloader
Driver Lib
ARM Cortex M4
80 MHz
ITM
SWJ-DP
SYSTICK
NVIC
AES DES/3DES SHA/MD5 CRC
HW Cryptography Accelerator
µDMA
ARCM
Apps Subsystem
Power-Reset-Clock
Controller
BridgeBridge
Top Level Bus
Pad Config Reg
ADC Control Reg
Device Config
GPRCM
Power-Reset-Clock
Global Controller
Always-ON Core Domain
Hibernate Controller
RTC counter + alarm
Pad Monitor
Wake Up Sequencer
DCDC Control
32 KHx XOSC DIG DCDC ANA DCDC PA DCDC
Supply Monitor32 KHz RC OSC
Low Phase Noise
Oscillator (40MHz)
IcePick
Pin Mux
DFT TAP
SoC TAP
MCU PLL WLAN PLL
802.11bgn Radio
802.11bgn Baseband
802.11bgn MAC
Application Protocols
TLS/SSL
UDP/TCP
IP
Supplicant
WiFi-Driver
Peripheral Clocks & Resets
240 MHz, 80 MHz, 40 MHz
Always-ON
Core Domain
1.8 V Analog Domain
Always-ON VBAT Domain
Level Shifters
DIG_PORZ
(Digital Power-On Reset)
32 KHz
SYS
ICODE DCODE
2-W
4-W
SimpleLink Subsystem
2-wire/4-wire pinout select
SOP [2:0]
240 MHz
80 MHz 40 MHz
480 MHz
XTAL
40MHz
Supply Input
2.1V ± 3.6 V /
1.85 V Regulated
XTAL
32.765 KHz
nRESET
Complete Chip Reset
CC3220 MCU + WiFi System-On-Chip
TM
TM
TM
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1.2 Architecture Overview

Figure 1-1 shows the Internet-on-a chip.
Architecture Overview
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Figure 1-1. CC32xx MCU and Wi-Fi® System-on-Chip
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1.3 Functional Overview

The following sections provide an overview of the main components of the CC32xx system on chip (SoC) from a microcontroller point of view.

1.3.1 Processor Core

1.3.1.1 Arm® Cortex®-M4 Processor Core
The CC32xx application MCU subsystem is built around an Arm Cortex-M4 processor core, which provides outstanding computational performance and exceptional system response to interrupts at low power consumption, while optimizing memory footprint—making the MCU subsystem an ideal fit for embedded applications.
Key features of an Arm Cortex-M4 processor core are:
• Thumb®-2 mixed 16-bit and 32-bit instruction set delivers the high performance expected of a 32-bit Arm core in a compact memory size – enabling richer applications within a given device memory size.
• Single-cycle multiply instruction and hardware divide
• Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control
• Unaligned data access, enabling data to be efficiently packed into memory
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Configurable 4-pin JTAG and 2-pin (SWJ-DP) debug access
• Ultra-low-power sleep modes
• Low active power consumption
• 80-MHz operation
1.3.1.2 System Timer (SysTick)
The Arm® Cortex®-M4 processor core includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter is clocked on the system clock.
SysTick makes OS porting between Cortex®-M4 devices much easier because there is no need to change the OS system timer code. The SysTick timer integrates with the NVIC and can generate a SysTick exception (exception type 15). In many OSs, a hardware timer generates interrupts so that the OS can perform task management (for example, to allow multiple tasks to run at different time slots and to ensure that no single task can lock up the entire system). To perform this function, the timer must be able to generate interrupts and, if possible, be protected from user tasks so that user applications cannot change the timer behavior.
The counter can be used in several different ways:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine
• A high-speed alarm timer using the system clock
• A simple counter used to measure time to completion and time used
• An internal clock-source control based on missing or meeting durations
1.3.1.3 Nested Vector Interrupt Controller (NVIC)
The CC32xx device includes the Arm® NVIC. The NVIC and Cortex®-M4 prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to the state saving, thus enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. The NVIC and Cortex®-M4 processor prioritize and handle all exceptions in handler mode. The NVIC and the processor core interface are closely coupled to enable low-latency interrupt processing and efficient processing of late-arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts.
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Key features follow:
• Exceptional interrupt handling through hardware implementation of required register manipulations
• Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
• Programmable priority level for each interrupt
• Low-latency interrupt and exception handling
• Level and pulse detection of interrupt signals
• Grouping of interrupts into group priority and subpriority interrupts
1.3.1.4 System Control Block
The system control block (SCB) provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

1.3.2 Memory

1.3.2.1 On-Chip SRAM
The CC32xx device has up to 256KB of zero wait state, on-chip SRAM, to which application programs are downloaded and executed. The SRAM is used for both code and data, and is connected to the Multilayer-AHB bus-matrix of the chip. There is no restriction on relative size or partitioning of code and data on the micro-direct memory access (μDMA) controller except the lower 16KBs of SRAM.
The micro-direct memory access (µDMA) controller can transfer data to and from SRAM and various peripherals. The SRAM banks implement an advanced 4-way interleaved architecture, which almost eliminates the performance penalty when DMA and processor simultaneously access the SRAM.
Internal RAM has selective retention capability during low-power deep-sleep (LPDS) mode. Based on need, during LPDS mode the application can choose to retain 256KB, 192KB, 128KB, or 64KB. Retaining the memory during low-power mode provides a faster wakeup. TI provides an easy-to-use power-management framework for processor and peripheral context save and restore mechanism based on SRAM retention.
1.3.2.2 ROM
CC32xx comes with factory programmed zero-wait-state ROM with the following firmware components:
• Device initialization
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
When the CC32xx powers up, or the chip reset is released or returns from hibernate mode, the device initialization procedure is executed first. After the chip hardware has been correctly configured, the bootloader is executed, which loads the application code from nonvolatile memory into on-chip SRAM and makes a jump to the application code entry point.
The CC32xx DriverLib is a software library that controls on-chip peripherals. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support.
The ROM DriverLib provides a rich set of drivers for peripheral and chip. The DriverLib is aimed at reducing application development time and improving solution robustness. TI recommends that applications make extensive use of the DriverLib APIs to optimize memory and MIPS requirement of end applications.
1.3.2.3 Flash Memory
The CC323xSF device comes with an on-chip flash memory of 1024KB, allowing application code to execute in­place while freeing up SRAM to be used exclusively for read-write data. The flash memory is used for code and constant data sections, and is directly attached to the ICODE/DCODE bus of the Cortex®-M4 core. A 128-bit­wide instruction prefetch buffer allows maintaining maximum performance for linear code, or loops that fit inside the buffer.
The flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can be performed at word (32-bit) level.
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1.3.3 Micro-Direct Memory Access Controller (µDMA)

The CC32xx MCU includes a micro-direct memory access (μDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the Cortex®-M4 processor, allowing more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfers between memory and peripherals; it has dedicated channels for each supported on-chip module. The µDMA controller can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The µDMA controller provides the following features:
• 32 configurable channels
• 80-MHz operation
• Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic and simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
• Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable bus arbitration scheme – Software-initiated requests for any channel
• Two levels of priority
• Design optimizations for improved bus access performance between the µDMA controller and the processor core
– µDMA controller access subordinate to core access – Simultaneous concurrent access
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, halfword, word, or no increment
• Maskable peripheral requests
• Interrupt on transfer completion, with a separate interrupt per channel

1.3.4 General-Purpose Timer (GPT)

The CC32xx includes 4 instances of 32-bit user-programmable general-purpose timers (GPTs). GPTs count or time external events that drive the timer input pins. Each GPT module (GPTM) block provides two 16-bit timers or counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer. The GPTM contains GPTM blocks with the following functional options:
• Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit GPT with an 8-bit prescaler – 16-bit input-edge count or time-capture modes – 16-bit pulse-width modulation (PWM) mode with software-programmable output inversion of the PWM
signal
• Count up or down
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the ISR
• Can trigger efficient transfers using the µDMA. – Dedicated channel for each timer
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– Burst request generated on timer interrupt

1.3.5 Watchdog Timer (WDT)

The watchdog timer (WDT) in the CC32xx restarts the system when it gets stuck due to an error and does not respond as expected. The WDT can be configured to generate an interrupt to the MCU on its first time-out, and to generate a reset signal on its second time-out. Once the WDT is configured, the lock register can be written to prevent the timer configuration from being inadvertently altered.
The WDT provides the following features:
• 32-bit down-counter with a programmable load register
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic

1.3.6 Multichannel Audio Serial Port (McASP)

The CC32xx includes a configurable multichannel audio serial port (McASP) for glue-less interfacing to audio codec and DAC (speaker drivers). The audio port has two serializers or deserializers that can be individually enabled to either transmit or receive and operate synchronously. Key features follow:
• Two stereo I2S channels – One stereo receive and one stereo transmit lines – Two stereo transmit lines
• Programmable clock and frame-sync polarity (rising or falling edge)
• Programmable word length (bits per word): 16 and 24 bits
• Programmable fractional divider for bit-clock generation, up to 9 MHz
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1.3.7 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a 4-wire bidirectional communications interface that converts data between parallel and serial. The SPI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SPI allows a duplex serial communication between a local host and SPI-compliant external devices.
The CC32xx includes one SPI port dedicated to the application. Key features are:
• Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces master and slave modes
• 3-pin and 4-pin mode
• Full duplex and half duplex
• Serial clock with programmable frequency, polarity, and phase
• Up to 20-MHz operation
• Programmable chip select polarity
• Programmable delay before the first SPI word is transmitted
• Programmable timing control between chip select and external clock generation
• No dead cycle between two successive words in slave mode
• SPI word lengths of 8, 16, and 32 bits
• Efficient transfers using the µDMA controller

1.3.8 Inter-Integrated Circuit (I2C) Interface

The inter-integrated circuit (I2C) bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to a wide variety of external I2C devices such as sensors, serial memory, control ports of image sensors, and audio codecs. Multiple slave devices can be connected to the same I2C bus. The CC32xx microcontroller includes one I2C module with the following features:
• Master and slave modes of operation
• Master with arbitration and clock synchronization
• Multimaster support
• 7-bit addressing mode
• Standard (100 kbps) and fast (400 kbps) modes

1.3.9 Universal Asynchronous Receiver/Transmitter (UART)

A universal asynchronous receivers/transmitter (UART) is an integrated circuit used for RS-232 serial communications. UARTs contain a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately.
The CC32xx device includes two fully programmable UARTs. The UART can generate individually-masked interrupts from the RX, TX, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and unmasked.
The UARTs include the following features:
• Programmable baud-rate generator, allowing speeds up to 3 Mbps
• Separate 16 × 8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte-deep operation providing conventional double-buffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
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• Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation and detection – 1 or 2 stop-bit generation
• RTS and CTS modem handshake support
• Standard FIFO-level and end-of-transmission interrupts
• Efficient transfers using µDMA – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level

1.3.10 General-Purpose Input/Output (GPIO)

All digital pins of the CC32xx device and some of the analog pins can be used as a general-purpose input/output (GPIO). The GPIOs are grouped as four instance GPIO modules, each 8-bit. Supported features include:
• Up to 28 GPIOs, depending on the functional pin configuration
• Interrupt capability for all GPIO pins: – Level or edge sensitive – Rising or falling edge – Selective interrupt masking
• Can trigger DMA operation
• Selectable wakeup source (one out of six pins)
• Programmable pad configuration: – Internal 5-µA pullup and pulldown – Configurable drive strength of 2 mA, 4 mA, and 6 mA – Open-drain mode
• GPIO register readable through the high-speed internal bus matrix

1.3.11 Analog-to-Digital Converter (ADC)

The analog-to-digital converter (ADC) peripheral converts a continuous analog voltage into a discrete digital number. The CC32xx device includes ADC modules with four input channels. Each ADC module features 12-bit conversion resolution for the four input channels. Features include:
• Number of bits: 12-bit
• Effective nominal accuracy: 10 bits
• Four analog input channels
• Automatic round-robin sampling
• Fixed sampling interval of 16 µs per channel
• Automatic 16-bit time-stamping of every ADC samples based on the system clock
• Dedicated DMA channel to transfer ADC channel data to the application RAM.

1.3.12 SD Card Host

The CC32xx includes an SD-Host interface for applications that require mass storage. The SD-Host interface support is currently limited to 1-bit mode.
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1.3.13 Parallel Camera Interface

The CC32xx includes an 8-bit parallel camera port to enable image sensor-based applications.

1.3.14 Debug Interface

The CC32xx supports both IEEE Standard 1149.1 JTAG (4-wire) and the low-pin-count Arm® SWD (2-wire) debug interfaces. Depending on the board-level configuration of the sense-on-power pull resistors, by default the chip powers up with either the 4-wire JTAG or the 2-wire SWD interface.
As shown in Figure 1-1, the 4-wire JTAG signals from the chip pins are routed through an IcePick module. TAPs other than the application MCU are reserved for TI production testing. A sequence that selects the TAP must be sent to the device to connect to the Arm® Cortex®-M4 JTAG TAP. The 2-wire mode, however, directly routes the Arm® SWD-TMS and SWD-TCK pins directly to the respective chip pins.

1.3.15 Hardware Cryptography Accelerator

The secure variant of the CC32xx includes a suite of high-throughput, state-of-the-art hardware accelerators for fast computation of ciphers (AES, DES, 3-DES), hashing (SHA, MD5), and CRC algorithms by the application. It is also referred to as the data hashing and transform engine (DTHE).

1.3.16 Clock, Reset, and Power Management

The CC32xx system-on-chip includes the necessary clock and power management functionalities to build a stand-alone, battery-operated low-power solution. Key features follow:
• Primary clocks – Slow clock: 32.768 kHz (±250 ppm)
• Used in RTC, Wi-Fi® beacon listen timing in low-power idle mode and some of the chip internal sequencing
• On-chip, low-power 32-kHz crystal oscillator
• Support for externally-fed 32.768-kHz clock
• On-chip 32-kHz RC oscillator for initial wakeup
– Fast clock: 40 MHz (±20 ppm)
• Used in Wi-Fi® radio and MCU
• On-chip low phase-noise 40-MHz crystal oscillator
• Support for externally fed, clean 40-MHz clock (such as TCXO)
• System and peripheral clocks are derived from internal PLL producing 240 MHz
• Flexible reset scheme – The following resets are supported in CC32xx:
• External chip reset pin: the entire chip, including power management, is reset when the nRESET pin is held low
• Reset on hibernate: the entire core is reset when the chip goes through a hibernate cycle
• Reset on watchdog: the application MCU is reset when the WDT expires
• Soft-reset: the application MCU is reset by software
– Complete system recovery from any scenario at which the scenario is stuck can be achieved by using a
combination of WDT reset and hibernate sleep.
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• On-chip power management – Wide voltage mode: 2.1 V to 3.6 V
• Powered by battery (2×1.5 V) or a regulated 3.3-V supply
– A set of three on-chip high-efficiency DC/DC converters produce the internal module supply voltages
when needed. These switching converters and their frequency plan are optimized to minimize interference to WLAN radio.
• DIG-DCDC: Produces 0.9 V to 1.2 V for the core digital logic
• ANA1-DCDC: Produces low-ripple 1.8-V supply for the analog and RF
• PA-DCDC: Produces regulated 1.8 V with extremely fast transient regulation for the WLAN RF transmit power amplifier
– A set of low-dropout regulators (LDOs) is used in the radio subsystem to further regulate and filter the
ANA1-DCDC output before being fed to the analog circuits
– On-chip factory-trimmed accurate band-gap voltage reference ensures the regulator outputs are stable
across process and temperature

1.3.17 SimpleLink™ Subsystem

The SimpleLink™ subsystem provides fast, secured WLAN and Internet connections with 256-bit encryption. The CC32xx device supports station, AP, and Wi-Fi Direct® modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi® network processor includes an embedded IPv6 TCP/IP stack.
This multiprocessor subsystem consists of:
• IPv6 network processor and Wi-Fi® driver
• 802.11 b/g/n/a MAC
• 802.11 b/g/n/a PHY
• 802.11 b/g/n/a radio The SimpleLink™ subsystem is accessible from the application MCU over an asynchronous link, and can be
controlled through a complete set of SimpleLink™ host driver APIs provided as part of the ROM driver library. The mode of usage is similar to that of an external MCU using the CC3120 device.
The co-location of the Wi-Fi® subsystem on the same die imposes a few restrictions on the application MCU. These are covered in Chapter 15.

1.3.18 I/O Pads and Pin Multiplexing

The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at device reset) and register control.
The I/O pad and pin multiplexing sections feature flexible wide-voltage I/Os. Supported features include:
• Programmable drive strength of 2 mA, 4 mA, and 6 mA
• Open-drain mode
• Output buffer isolation
• Automatic output isolation during reset and hibernate
• Configurable pullup and pulldown (10 µA nominal)
• Software-configurable pad state retention during LPDS
• All digital I/Os are nonfail-safe
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Chapter 2

Cortex®-M4 Processor

2.1 Overview......................................................................................................................................................................42
2.2 Functional Description...............................................................................................................................................45
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2.1 Overview

The CC32xx device incorporates a dedicated instance of the Arm Cortex-M4 CPU core for executing application code with or without real-time operating system (RTOS). This processor core is not used in any manner for running any networking or device management task.
This dedicated Arm Cortex-M4 core, along with large on-chip SRAM, a rich set of peripherals, and advanced DC-DC-based power management, provides a robust, contention-free, high-performance application platform at much lower power, lower cost, and smaller solution size when compared to solutions based on discrete MCUs.
Features include:
• 32-bit Arm Cortex-M4 architecture optimized for small-footprint embedded applications
• 80-MHz operation
• Fast interrupt handling
• Thumb®-2 mixed 16-bit and 32-bit instruction set delivers the high performance expected of a 32-bit Arm core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications.
– Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory
• 16-bit SIMD vector processing unit
• 3-stage pipeline Harvard architecture
• Hardware division and fast digital signal processing-orientated multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoints
• Serial-wire debug and serial-wire trace reduce the number of pins required for debugging and tracing
• Low power consumption with multiple sleep modes
The Arm Cortex-M4 application processor core in the CC32xx does not include the floating point unit (FPU) and memory protection unit (MPU).
This chapter provides information on the implementation of the Cortex-M4 application processor in the CC32xx, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the Arm Cortex-M4 CPU core, see the Arm® Cortex®-M4 Processor Technical Reference Manual (ARM 100166_0001_00).
For technical details on the instruction set, see the Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
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ARM® Cortex® M4
Instrumentation
Trace Macrocell
Data
Watchpoint
and Trace
CM4 Core
Instructions Data
Flash
Patch and
Breakpoint
Nested
Vectored
Interrupt
Controller
Adv. Peripheral
Bus
Bus
Matrix
Debug
Access Port
ROM Table
Serial Wire JTAG
Debug Port
Trace
Port
Interface
Unit
Serial Wire
Output Trace
Port (SWO)
I-code bus
d-code bus system bus
Private Peripheral Bus
(internal)
Interrupts
Sleep
Debug
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2.1.1 Block Diagram

Figure 2-1 shows the block diagram.
Cortex®-M4 Processor
Figure 2-1. Application CPU Block Diagram

2.1.2 System-Level Interface

The Cortex-M4 application processor in the CC32xx provides multiple interfaces using AMBA™ technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling.

2.1.3 Integrated Configurable Debug

The Cortex-M4 application processor implements an Arm CoreSight™-compliant serial wire JTAG-debug port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the Arm Debug Interface V5 Architecture Specification for details on SWJ-DP.
The 4-bit trace interface from embedded trace macrocell (ETM) is not supported in the CC32xx due to pin limitations. Instead, the processor integrates an instrumentation trace macrocell (ITM) alongside data watchpoints and a profiling unit. A serial-wire viewer (SWV) can export a stream of software-generated messages (printf style debug), data trace, and profiling information through a single pin to enable simple and cost-effective profiling of the system trace events.
The flash patch and breakpoint unit (FPB) provides up to eight hardware breakpoint comparators for debugging. The comparators in the FPB also provide remap functions for up to eight words of program code in the code memory region. FPB also provides code patching capability; however, as the CC32xx application processor implements and executes from SRAM architecture, this type of patching is no longer required.
For more information on the Cortex-M4 debug capabilities, see the Arm Debug Interface V5 Architecture Specification.
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Debug
ATB
Slave
Port
ARM® Trace
Bus (ATB)
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
APB
Sla
ve
Port
Advance Peripheral Bus (APB)
Interface
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2.1.4 Trace Port Interface Unit (TPIU)

The TPIU acts as a bridge between the Cortex®-M4 trace data from the ITM, and an off-chip trace port analyzer, as shown in Figure 2-2.
Figure 2-2. TPIU Block Diagram

2.1.5 Cortex®-M4 System Component Details

The Cortex®-M4 application processor core includes the following system components:
• SysTck: A 24-bit count-down timer used as an RTOS tick timer or as a simple counter (see Section 3.2.1).
• Nested Vectored Interrupt Controller (NVIC): An embedded interrupt controller that supports low-latency interrupt processing (see Nested Vectored Interrupt Controller [NVIC] in Section 3.2.2).
• System Control Block (SCB): The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see System Control Block [SCB] in Section 3.2.3).
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2.2 Functional Description

2.2.1 Programming Model

This section describes the Cortex®-M4 programming model and includes the individual core register descriptions, information about the processor modes, and privilege levels for software execution and stacks.
2.2.1.1 Processor Mode and Privilege Levels for Software Execution
The Cortex®-M4 has two modes of operation:
• Thread mode to execute application software. The processor enters thread mode when it comes out of reset.
• Handler mode to handle exceptions. When the processor has finished exception processing, it returns to thread mode.
In addition, the Cortex®-M4 has two privilege levels:
• Unprivileged: In this mode, the software has the following restrictions: – Limited access to the MSR and MRS instructions, and no use of the CPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals
• Privileged: In this mode, the software can use all instructions and has access to all resources
In thread mode, the CONTROL register controls whether software execution is privileged or unprivileged. In handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software execution in thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software.
2.2.1.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer, then writes the item to the new memory location. The processor implements two stacks: the main stack and the process stack, with a pointer for each held in independent registers (see the SP register).
In thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack. In handler mode, the processor always uses the main stack. Table 2-1 lists the options for processor operations.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode Use Privilege Level Stack Used
Thread Applications Privileged or unprivileged
Handler Exception handlers Always privileged Main stack
(1) See the CONTROL register in Section 2.2.2.2.8.
(1)
Main stack or process stack
(1)
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R0 R1 R2 R3 R4 R5
R6 R7 R8
R9 R10 R11
R12
SP (R13) LR (R14) PC (R15)
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
Low registers
General-purpose registers
High registers
Stack Pointer
Link Register
Program Counter
PSP
‡
MSP
‡
‡
Program status register
Exception mask registers
CONTROL register
Special registers
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2.2.2 Register Description

2.2.2.1 Register Map
Figure 2-2 shows the Cortex®-M4 register set. Table 2-2 lists the core registers. The core registers are not
memory-mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex®-M4 Register Set
Table 2-2. Processor Register Map
Offset Name Type Reset Description
– R0 R/W – Cortex General-Purpose register 0 – R1 R/W – Cortex General-Purpose register 1 – R2 R/W – Cortex General-Purpose register 2 – R3 R/W – Cortex General-Purpose register 3 – R4 R/W – Cortex General-Purpose register 4 – R5 R/W – Cortex General-Purpose register 5 – R6 R/W – Cortex General-Purpose register 6 – R7 R/W – Cortex General-Purpose register 7 – R8 R/W – Cortex General-Purpose register 8 – R9 R/W – Cortex General-Purpose register 9 – R10 R/W – Cortex General-Purpose register 10 – R11 R/W – Cortex General-Purpose register 11 – R12 R/W – Cortex General-Purpose register 12 – SP R/W – Stack pointer – LR R/W 0xFFFF.FFFF Link register – PC R/W – Program counter – PSR R/W 0x0100.0000 Program Status register – PRIMASK R/W 0x0000.0000 Priority Mask register – FAULTMASK R/W 0x0000.0000 Fault Mask register
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Table 2-2. Processor Register Map (continued)
Offset Name Type Reset Description
– BASEPRI R/W 0x0000.0000 Base Priority Mask register – CONTROL R/W 0x0000.0000 Control register – FPSC R/W – Floating-Point Status Control (N/A for CC32xx)
2.2.2.2 Register Descriptions
This section lists and describes the Cortex®-M4 registers. The core registers are not memory-mapped, and are accessed by register name rather than offset.
Note
The register type shown in the register descriptions refers to type during program execution in thread mode and handler mode. Debug access may differ.
The R0–R12 registers are 32-bit general-purpose registers for data operations, and can be accessed from either privileged or unprivileged mode.
2.2.2.2.1 Stack Pointer (SP)
In thread mode, the function of this register changes depending on the ASP bit in the Control (CONTROL) register. When the ASP bit is clear, this register is the main stack pointer (MSP). When the ASP bit is set, this register is the process stack pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000 0000. The MSP can be accessed only in privileged mode; the PSP can be accessed in either privileged or unprivileged mode.
2.2.2.2.2 Link Register (LR)
The Link register (LR) stores the return information for subroutines, function calls, and exceptions. The Link register can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into the LR on exception entry.
2.2.2.2.3 Program Counter (PC)
The program counter (PC) register contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000 0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode.
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2.2.2.2.4 Program Status Register (PSR)
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Note
This register is also referred to as xPSR.
The Program Status register (PSR) has three functions, and the register bits are assigned to the different functions:
• Application Program Status register (APSR), bits 31:27, bits 19:16
• Execution Program Status register (EPSR), bits 26:24, bits 15:10
• Interrupt Program Status register (IPSR), bits 7:0 The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be
accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the
Thumb state bit and the execution state bits for the if-then (IT) instruction or the interruptible-continuable instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted.
IPSR contains the exception type number of the current interrupt service routine (ISR). These registers can be accessed individually, or as a combination of any two or all three registers, using the
register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. Table
2-3 shows the possible register combinations for the PSR. See the descriptions of the MRS and MSR
instructions in the Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A) for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register Type Combination
(1)
(2)
(1) (2)
APSR, EPSR, and IPSR
APSR and IPSR
APSR and EPSR
PSR PSR R/W IEPSR RO EPSR and IPSR IAPSR R/W
EAPSR R/W
(1) The processor ignores writes to the IPSR bits. (2) Reads of the EPSR bits return zero, and the processor ignores writes to these bits
2.2.2.2.5 Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is accessible only in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A) for more information on these instructions.
2.2.2.2.6 Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the NMI. Exceptions should be disabled when they might impact the timing of critical tasks. This register is accessible only in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex®-M4 Devices Generic User Guide (ARM
DUI 0553A) for more information on these instructions.
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2.2.2.2.7 Base Priority Mask Register (BASEPRI)
Cortex®-M4 Processor
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is accessible only in privileged mode.
2.2.2.2.8 Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode, and indicates whether the FPU state is active. This register is accessible only in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value. In an OS environment, threads running in thread mode should use the process stack, and the kernel and exception handlers should use the main stack. By default, thread mode uses the MSP. To switch the stack pointer used in thread mode to the PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A), or perform an exception return to thread mode with the appropriate EXC_RETURN value.
Note
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).
2.2.2.3 Exceptions and Interrupts
The Cortex®-M4 application processor in the CC32xx supports interrupts and system exceptions. The processor and the NVIC prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See Section 2.2.4.7 for more information.
The NVIC registers control interrupt handling. See Section 3.2.2 for more information.
2.2.2.4 Data Types
The Cortex®-M4 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian.

2.2.3 Memory Model

This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory.
Table 2-4 provides the memory map of the CC32xx microcontroller subsystem. In this manual, register
addresses are given as a hexadecimal increment, relative to the base address of the module, as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see Section 2.2.3.1).
The processor reserves regions of the private peripheral bus (PPB) address range for core peripheral registers (see Chapter 3).
Note
Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault.
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Table 2-4. Memory Map
Start Address End Address Description Comment
0x0000.0000 0x0007.FFFF On-chip ROM (Bootloader + DriverLib) 0x0100.0000 0x010F.FFFF Flash 0x2000.0000 0x2003.FFFF Bit-banded on-chip SRAM 0x2200.0000 0x23FF.FFFF Bit-band alias of 0x2000.0000 to 0x200F.FFFF 0x4000.0000 0x4000.0FFF Watchdog timer A0 0x4000.4000 0x4000.4FFF GPIO port A0 0x4000.5000 0x4000.5FFF GPIO port A1 0x4000.6000 0x4000.6FFF GPIO port A2 0x4000.7000 0x4000.7FFF GPIO port A3 0x4000.C000 0x4000.CFFF UART A0 0x4000.D000 0x4000.DFFF UART A1 0x4002.0000 0x4002.07FF I2C A0 (master) 0x4002.0800 0x4002.0FFF I2C A0 (slave) 0x4002.4000 0x4002.4FFF GPIO port A4 0x4003.0000 0x4003.0FFF General-purpose timer A0 0x4003.1000 0x4003.1FFF General-purpose timer A1 0x4003.2000 0x4003.2FFF General-purpose timer A2 0x4003.3000 0x4003.3FFF General-purpose timer A3 0x400F.7000 0x400F.7FFF Configuration registers 0x400F.E000 0x400F.EFFF System control 0x400F.F000 0x400F.FFFF µDMA 0x4200.0000 0x43FF.FFFF Bit-band alias of 0x4000.0000 to 0x400F.FFFF 0x4401.0000 0x4401.0FFF SD Host (master) 0x4401.8000 0x4401.8FFF Camera Interface 0x4401.C000 0x4401.EFFF I2S (also called McASP)
0x4402.0000 0x4402.0FFF FlashSPI
0x4402.1000 0x4402.1FFF GSPI (also called APSPI)
0x4402.2000 0x4402.2FFF Link SPI (APPS to NWP SPI) 0x4402.5000 0x4402.5FFF MCU reset clock manager 0x4402.6000 0x4402.6FFF MCU configuration space 0x4402.E800 0x4402.E8B8 ADC 0xE000.0000 0xE000.0FFF Instrumentation trace macrocell (ITM) 0xE000.1000 0xE000.1FFF Data watchpoint and trace (DWT)
0xE000.2000 0xE000.2FFF Flash patch and breakpoint (FPB) 0xE000.E000 0xE000.EFFF Cortex-M4 peripherals (NVIC, SysTick,SCB) 0xE004.0000 0xE004.0FFF Trace port interface unit (TPIU) 0xE004.1000 0xE004.1FFF Reserved for embedded trace macrocell (ETM)
Used for external serial
flash
Used by application
processor
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2.2.3.1 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. In Arm
®
Cortex®-M4 architecture, the bit-band regions occupy the lowest 1MB of the SRAM. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-5.
Note
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region.
A word access to a bit-band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit-band accesses to match the access requirements of the underlying peripheral.
The CC32xx family of Wi-Fi microcontrollers support up to 256KB of on-chip SRAM for code and data. The SRAM starts from address 0x2000 0000.
Bit-banding for peripherals is not supported in the CC32xx.
Table 2-5. SRAM Memory Bit-Banding Regions
Address Range Memory Region Instruction and Data Accesses
Start End
0x2000.0000 0x2003.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM
0x2200.0000 0x23FF.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band
memory accesses, but this region is also bit addressable through bit-band alias.
region. A write operation is performed as read-modify-write. Instruction accesses are not remapped.
2.2.3.1.1 Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-
band region. Writing a value with bit 0 set writes 1 to the bit-band bit, and writing a value with bit 0 clear writes 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000 0000 indicates that the targeted bit in the bit-band region is clear, and 0x0000 0001 indicates that the targeted bit in the bit-band region is set.
2.2.3.1.2 Directly Accessing a Bit-Band Region
Behavior of memory accesses describes the behavior of direct byte, halfword, or word accesses to the bit-band regions.
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7 0
B0
B1
B2
B3
31 24 23 16 15 8 7 0
B3 B2 B1 B0
Memory Register
Address A
A+1
l
sbyte
A+2
A+3
msbyte
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2.2.3.2 Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0 to 3 hold the first stored word, and bytes 4 to 7 hold the second stored word. Data is stored in little-endian format, with the least significant byte (LSByte) of a word stored at the lowest-numbered byte, and the most significant byte (MSByte) stored at the highest-numbered byte. Figure 2-4 shows how data is stored.
Figure 2-4. Data Storage
2.2.3.3 Synchronization Primitives
The Cortex®-M4 instruction set includes pairs of synchronization primitives which provide a nonblocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform an ensured read-modify-write memory update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
• A load-exclusive instruction, to read the value of a memory location and request exclusive access to that location.
• A store-exclusive instruction, to try to write to the same memory location and return a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed.
The pairs of load-exclusive and store-exclusive instructions are:
• The word instructions LDREX and STREX
• The halfword instructions LDREXH and STREXH
• The byte instructions LDREXB and STREXB
Software must use a load-exclusive instruction with the corresponding store-exclusive instruction. To perform an exclusive read-modify-write of a memory location, software must:
1. Use a load-exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a store-exclusive instruction to try to write the new value back to the memory location.
4. Test the returned status bit. If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at Step 1 might be out of date. The software must retry the entire read-modify-write sequence.
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Software can use the synchronization primitives to implement a semaphore as follows:
1. Use a load-exclusive instruction to read from the semaphore address, to check whether the semaphore is free.
2. If the semaphore is free, use a store-exclusive instruction to write the claim value to the semaphore address.
3. If the returned status bit from Step 2 indicates that the store-exclusive succeeded, then the software has claimed the semaphore. However, if the store-exclusive failed, another process might have claimed the semaphore after the software performed Step 1.
The Cortex®-M4 includes an exclusive access monitor that tags the fact that the processor has executed a load­exclusive instruction. The processor removes its exclusive access tag if one of the following occurs:
• It executes a CLREX instruction.
• It executes a store-exclusive instruction, regardless of whether the write succeeds.
• An exception occurs, which means the processor can resolve semaphore conflicts between different threads.
For more information about the synchronization primitive instructions, see the Cortex®-M4 instruction set chapter in the Arm® Cortex®-M4 Devices Generic User Guide (ARM DUI 0553A).

2.2.4 Exception Model

The Arm® Cortex®-M4 application processor in the CC32xx and the NVIC prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables performing of back-to-back interrupts without the overhead of state saving and restoration.
Table 2-6 lists all exception types. Software can set eight priority levels on seven of these exceptions (system
handlers) as well as on 70 interrupts (listed in Table 2-6). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
Section 3.2.2.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a reset, nonmaskable interrupt (NMI), and a hard fault, in that order. Note that 0 is the default priority for all the programmable priorities.
Note
After a write to clear an interrupt source, several processor cycles may pass before deassertion of the interrupt source is acknowledged by the NVIC. Thus, if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC recognizes the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer).
See Section 3.2.2 for more information on exceptions and interrupts.
2.2.4.1 Exception States
Each exception is in one of the following states:
• Inactive: The exception is neither active nor pending.
• Pending: The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
• Active: An exception is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state.
• Active and Pending: The exception is being serviced by the processor, and there is a pending exception from the same source.
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2.2.4.2 Exception Types
The exception types follow:
• Reset: Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in thread mode.
• NMI: A nonmaskable interrupt (NMI) can be signaled using the NMI signal, or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of –2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. NMI in the CC32xx is reserved for the internal system, and is not available for application usage.
• Hard Fault: A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of –1, meaning they have higher priority than any exception with configurable priority.
• Memory Management Fault: A memory-management fault is an exception that occurs because of a memory­protection-related fault, including access violation and no match. The MPU or the fixed-memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.
• Bus Fault: A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled.
• Usage Fault: A usage fault is an exception that occurs because of a fault related to instruction execution, such as:
– An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return. An unaligned address on a word or halfword memory access or division by
zero can cause a usage fault when the core is properly configured.
• SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.
• Debug Monitor: This exception is caused by the debug monitor (when not halting). This exception is active only when enabled. This exception does not activate if it is a lower priority than the current activation.
• PendSV: PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the INTCTRL register.
• SysTick: A SysTick exception is an exception that the system timer generates when it reaches zero when enabled to generate an interrupt. Software can also generate a SysTick exception using the INTCTRL register. In an OS environment, the processor can use this exception as system tick.
• Interrupt (IRQ): An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-7 lists the interrupts on the CC32xx application processor
For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-6 lists as having configurable priority (see the SYSHNDCTRL register and the DIS0 register).
For more information about hard faults, memory management faults, bus faults, and usage faults, see Section
2.2.5.
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Table 2-6. Exception Types
Exception Type Vector Number Priority
– 0 – 0x0000.0000 Stack top is loaded from
Reset 1 –3 (highest) 0x0000.0004 Asynchronous Nonmaskable Interrupt
2 –2 0x0000.0008 Asynchronous
(NMI) Hard Fault 3 –1 0x0000.000C – Memory Management 4 Programmable Bus Fault 5 Programmable
Usage Fault 6 Programmable
- 10 – – Reserved SVCall 11 Programmable Debug Monitor 12 Programmable – 13 – – Reserved PendSV 14 Programmable SysTick 15 Programmable Interrupts 16 and above Programmable
(1) 0 is the default priority for all the programmable priorities. (2) See Figure 2-5. (3) See SYSPRI1 in Section 3.3.1.17 . (4) See PRIn registers.
(1)
Vector Address or Offset
(2)
Activation
the first entry of the vector table on reset.
(3)
(3)
0x0000.0010 Synchronous 0x0000.0014 Synchronous when
precise and asynchronous when imprecise
(3)
(3)
(3)
(3)
(3)
(4)
0x0000.0018 Synchronous
0x0000.002C Synchronous 0x0000.0030 Synchronous
0x0000.0038 Asynchronous 0x0000.003C Asynchronous
0x0000.0040 and above Asynchronous
Interrupt Number
(Bit in Interrupt
Registers)
0 0x0000.0040 GPIO Port 0 (GPIO 0-7) 1 0x0000.0044 GPIO Port A1 (GPIO 8-15) 2 0x0000.0048 GPIO Port A2 (GPIO 16-23) 3 0x0000.004C GPIO Port A3 (GPIO 24-31) 4 0x0000.0050 GPIO port A4 (GPIO 32) 5 0x0000.0054 UART0 6 0x0000.0058 UART1
8 0x0000.0060 I2C 14 0x0000.0078 ADC Channel-0 15 0x0000.007C ADC Channel-1 16 0x0000.0080 ADC Channel-2 17 0x0000.0084 ADC Channel-3 18 0x0000.0088 WDT 19 0x0000.008C 16- or 32-Bit Timer A0A 20 0x0000.0090 16- or 32-Bit Timer A0B 21 0x0000.0094 16- or 32-Bit Timer A1A 22 0x0000.0098 16- or 32-Bit Timer A1B 23 0x0000.009C 16- or 32-Bit Timer A2A
Table 2-7. CC32xx Application Processor Interrupts
Vector Address or Offset Description Type
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Table 2-7. CC32xx Application Processor Interrupts (continued)
Interrupt Number
(Bit in Interrupt
Registers)
24 0x0000.00A0 16- or 32-Bit Timer A2B 35 0x0000.00CC 16- or 32-Bit Timer A3A 36 0x0000.00D0 16- or 32-Bit Timer A3B 46 0x0000.00F8 uDMA Software Intr 47 0x0000.00FC uDMA Error Intr
161 0x0000.02C4 I2S 163 0x0000.02CC Camera 168 0x0000.02E0 RAM WR Error 171 0x0000.02EC Network Intr 175 0x0000.02FC Shared SPI interrupt (for SFLASH) 176 0x0000.0300 SPI 177 0x0000.0304 Link SPI (APPS to NWP)
Vector Address or Offset Description Type
2.2.4.3 Exception Handlers
The processor handles exceptions using:
• Interrupt service routines (ISRs): Interrupts (IRQx) are the exceptions handled by ISRs.
• Fault handlers: Hard fault, memory-management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers.
• System handlers: NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions handled by system handlers.
2.2.4.4 Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in
Table 2-6. Figure 2-5 shows the order of the exception vectors in the vector table. The least significant bit of
each vector must be 1, indicating that the exception handler is thumb code. On system reset, the vector table is fixed at address 0x0000 0000. Privileged software can write to the Vector
Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000 0400 to 0x3FFF FC00. When configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary.
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Exception number
(N+16)
. . .
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
RQ number
(N)
2
1
0
-1
-2
-5
-10
-11
-12
-13
-14
Offset
0x040
+ 0x(N*4)
. . .
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
0x002C
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Vector
IRQ N
. . .
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserve
d
Reserved for Debug
SVCall
Reserved
Usage
fault Bus
fault
Memory management
fault Hard fault
NMI
Reset
Initial SP value
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2.2.4.5 Exception Priorities
As shown in Table 2-6, all exceptions have an associated priority, with a lower assigned priority value indicating an actual higher priority and configurable priorities for all exceptions except reset, hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
Configurable priority values for the CC32xx implementation are in the range from 0 to 7. This means that the reset, hard fault, and NMI exceptions (NMI is reserved for use by the system) with fixed negative priority values always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1]
Figure 2-5. Vector Table
Note
has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number
takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is
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not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.
2.2.4.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields:
• An upper field that defines the group priority
• A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first.
2.2.4.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
• Preemption: When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See Section 2.2.4.6 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions.
• Return: Return occurs when the exception handler is completed, there is no pending exception with sufficient priority to be serviced, and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
• Tail-chaining: This mechanism speeds up exception servicing. On completion of an exception handler, if a pending exception meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.
• Late-arriving: This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State-saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state-saving continues uninterrupted. The processor can accept a late-arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. When the late-arriving exception returns from the exception handler, the normal tail-chaining rules apply.
2.2.4.7.1 Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in thread mode or the new exception has a higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers (see the PRIMASK, FAULTMASK, and BASEPRI registers). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking, and the structure of eight data words is referred to as stack frame.
Figure 2-6 shows the Cortex®-M4 stack frame layout, which is similar to that of Armv7-M implementations
without an FPU.
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Figure 2-6. Exception Stack Frame
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted
program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel with the stacking operation, the processor performs a vector fetch that reads the exception handler
start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and which operation mode the processor was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception

2.2.5 Fault Handling

Faults are a subset of the exceptions (see Section 2.2.4). The following conditions generate a fault:
• A bus error on an instruction fetch, vector table load, or a data access
• An internally detected error, such as an undefined instruction or an attempt to change state with a BX instruction
• Attempting to execute an instruction from a memory region marked as nonexecutable (XN)
2.2.5.1 Fault Types
Table 2-8 lists the types of fault, the handler used for the fault, the corresponding fault status register, and the
name of the register bit that indicates the fault has occurred.
Table 2-8. Faults
Fault Handler Fault Status Register Bit Name
Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED Default memory mismatch on
instruction access Default memory mismatch on data
access Default memory mismatch on
exception stacking Default memory mismatch on
exception unstacking Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE
Memory management fault Memory Management Fault Status
(MFAULTSTAT)
Memory management fault Memory Management Fault Status
(MFAULTSTAT)
Memory management fault Memory Management Fault Status
(MFAULTSTAT)
Memory management fault Memory Management Fault Status
(MFAULTSTAT)
(1)
IERR
DERR
MSTKE
MUSTKE
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Table 2-8. Faults (continued)
Fault Handler Fault Status Register Bit Name
Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction
set state Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0
(1) Occurs on an access to an XN region. (2) Attempting to use an instruction set other than the Thumb instruction set, or returning to a nonload-store-multiple instruction with ICI
(2)
continuation.
Usage fault Usage Fault Status (UFAULTSTAT) INVSTAT
2.2.5.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 in Section 3.3.1.17 ). Software can disable execution of the handlers for these faults (see SYSHNDCTRL).
Usually the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in
Section 2.2.4.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself, because it must have the same priority as the current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the fault handler that is currently executing.
• An exception handler causes a fault for which the priority is the same as or lower than the exception that is currently executing.
• A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus, if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted.
Note
Only reset and NMI can preempt the fixed-priority hard fault. A hard fault can preempt any exception other than reset, NMI, or another hard fault.
2.2.5.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory-management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-9.
Table 2-9. Fault Status and Fault Address Registers
Handler Status Register Name Address Register Name Register Description
Hard fault Hard Fault Status (HFAULTSTAT) – Section 3.3.1.22 Memory-management fault Memory Management Fault
Status (MFAULTSTAT)
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Table 2-9. Fault Status and Fault Address Registers (continued)
Handler Status Register Name Address Register Name Register Description
Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address (FAULTADDR) Section 3.3.1.23 Usage fault Usage Fault Status
(UFAULTSTAT)
– Section 3.3.1.23
2.2.5.4 Lockup State
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
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2.2.6 Power Management

The CC32xx Wi-Fi microcontroller is a multiprocessor system-on-chip. An advanced power-management scheme has been implemented at chip level that delivers the best-in-class energy efficiency across a wide class of application profiles, while handling the asynchronous sleep-wake requirements of multiple high-performance processors and Wi-Fi radio subsystems. The Cortex®-M4 application processor subsystem (consisting of the CM4 core and application peripherals) is a subset of this.
In the chip-level power-management scheme, the application program is unaware of the power state transitions of the other subsystems. This approach insulates the user from the complexities of a multiprocessor system and simplifies the application development process.
From the standpoint of the Cortex®-M4 application processor, CC32xx supports the SLEEP mode similar to those in discrete microcontrollers. In addition to SLEEP mode, additional modes are offered that consume much less power:
• Low-Power Deep-Sleep (LPDS) mode: – Recommended for ultra-low power always-connected cloud and Wi-Fi applications – Up to 256KB of SRAM retention and fast wakeup (<5 mS) – When networking and Wi-Fi subsystems are disabled, the MCU draws less than 100 µA with 256KB of
SRAM retained (code and data). Total system current (including Wi-Fi and network periodic wakeup) as low as 700 µA
– Processor and peripheral registers are not retained. Global always ON configurations at SoC level are
retained
• Hibernate (HIB) Mode: – Recommended for ultra-low power infrequently connected cloud and Wi-Fi applications – Ultra low current of 4 µA, including RTC – Wake on RTC or selected GPIO – No SRAM or logic retention. 2 × 32-bit register retention
• Shutdown Mode (choose this mode when periodic activity is required and the period between cycles is long): – Lowest power mode of about 1 µA – System including RTC and memories are off – Cold boot initialization is required
LPDS and HIB modes are discussed in more detail in the Power Clock and Reset Management chapter.
Figure 2-7 shows the architecture of the CC32xx SoC level power management, especially from the application
point of view. The Cortex®-M4 processor implementation inside the CC32xx multiprocessor SoC has a few differences when
compared to a discrete MCU. While SLEEP mode is supported, in the CC32xx this mode is limited in energy consumption savings.
Ultra-low power applications should be architected such that time spent in LPDS or hibernate mode is maximized. The Cortex®-M4 application processor can be configured wake up on selected events, for example network events such as an incoming data packet, timer, or I/O pad toggle. The time spent in RUN (or ACTIVE) state should then be minimized. The dedicated Cortex®-M4 application processor in CC32xx is particularly suited for this mode of operation due to its advanced power management, DMA, zero wait-state multi-layer AHB interconnect, fast execution and retention over the entire range of zero wait-state SRAM.
• SLEEP: Sleep mode stops the processor clock (clock gating).
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I/O Mux
Cortex-M4
Dedicated Application Processor
ROM
(Boot, Drivers)
SRAM
(Code, Data)
Watchdog
Timer
PeripheralNPeripheral
1
clk
rst
clk
rst
clk
rst
ARCM
Application Reset & Clock Control
FCLK
HCLK
External
SPI Flash
Network Processor
HWA
Cortex-M3 DMA ROM RAM
HWA
HWA
802.11bgna MAC
HWA
Cortex-M3 DMA ROM RAM
HWA
HWA
802.11bgna MAC
Cortex-M3 DMA
Cortex-M3 DMA
802.11 bgna Radio
Global Power Reset-Clock Controller
(GPRCM)
SYSRESETn
SYSTRESETREQ
Clocks
SW Register I/F
Sleep Status
Sleeping, Deepslieep
App Reset
On-Chip PMU
(Power Management Unit)
Hibernate Controller
RTC
Counter
Pad
Wakeup
32.768 KHz LF-XOSC
40 MHz
HF-XOSC
PLL
240 MHz
I/O Pads
Interconnect
Interconnect
6LPSOH/LQNŒ6XEV\VWHP
6LPSOH/LQNŒ
API Call I/F
IRQ IRQ IRQ
Internal Supply Rails
Application Microcontroller Subsystem
SW Register I/F
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Figure 2-7. Power-Management Architecture in CC32xx SoC
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2.2.7 Instruction Set Summary

The processor implements a version of the Thumb instruction set. Table 2-10 lists the supported instructions.
• < > Angle brackets, enclose alternative forms of the operand.
• { } Braces, enclose optional operands.
• The Operands column is not exhaustive.
• Op2 is a flexible second operand that can be either a register or a constant.
• Most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions in the ARM® Cortex®-
M4 Processor Technical Reference Manual.
Table 2-10. Cortex®-M4 Instruction Summary
Mnemonic Operands Brief Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn , #imm12 Add – ADR Rd, label Load PC-related address – AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N,Z,C B label Branch – BFC Rd, #lsb, #width Bit field clear – BFI Rd, Rn, #lsb, #width Bit field insert – BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C BKPT #imm Breakpoint – BL label Branch with link – BLX Rm Branch indirect with link – BX Rm Branch indirect – CBNZ Rn, label Compare and branch if nonzero – CBZ Rn, label Compare and branch if zero – CLREX – Clear exclusive – CLZ Rd, Rm Count leading zeros – CMN Rn, Op2 Compare negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change processor state, disable interrupts – CPSIE i Change processor state, enable interrupts – DMB – Data memory barrier – DSB – Data synchronization barrier – EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB – Instruction synchronization barrier – IT – If-Then condition block – LDM Rn{!}, reglist Load multiple registers, increment after – LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement before – LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after – LDR Rt, [Rn, #offset] Load register with word – LDRB, LDRBT Rt, [Rn, #offset] Load register with byte – LDRD Rt, Rt2, [Rn, #offset] Load register with 2 bytes – LDREX Rt, [Rn, #offset] Load register exclusive – LDREXB Rt, [Rn] Load register exclusive with byte –
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Table 2-10. Cortex®-M4 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
LDREXH Rt, [Rn] Load register exclusive with halfword – LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword – LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte – LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword – LDRT Rt, [Rn, #offset] Load register with word – LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N,Z,C LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result – MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result – MOV, MOVS Rd, Op2 Move N,Z,C MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C MOVT Rd, #imm16 Move top – MRS Rd, spec_reg Move from special register to general register – MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP – No operation – ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack halfword – POP reglist Pop registers from stack – PUSH reglist Push registers onto stack – QADD {Rd,} Rn, Rm Saturating add Q QADD16 {Rd,} Rn, Rm Saturating add 16 – QADD8 {Rd,} Rn, Rm Saturating add 8 – QASX {Rd,} Rn, Rm Saturating add and subtract with exchange – QDADD {Rd,} Rn, Rm Saturating double and add Q QDSUB {Rd,} Rn, Rm Saturating double and subtract Q QSAX {Rd,} Rn, Rm Saturating subtract and add with exchange – QSUB {Rd,} Rn, Rm Saturating subtract Q QSUB16 {Rd,} Rn, Rm Saturating subtract 16 – QSUB8 {Rd,} Rn, Rm Saturating subtract 8 – RBIT Rd, Rn Reverse bits – REV Rd, Rn Reverse byte order in a word – REV16 Rd, Rn Reverse byte order in each halfword – REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend – ROR, RORS Rd, Rm, <Rs|#n> Rotate right N,Z,C RRX, RRXS Rd, Rm Rotate right with extend N,Z,C RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V SADD16 {Rd,} Rn, Rm Signed add 16 GE SADD8 {Rd,} Rn, Rm Signed add 8 GE SASX {Rd,} Rn, Rm Signed add and subtract with exchange GE SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed bit field extract – SDIV {Rd,} Rn, Rm Signed divide –
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Table 2-10. Cortex®-M4 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
SEL {Rd,} Rn, Rm Select bytes – SEV – Send event – SHADD16 {Rd,} Rn, Rm Signed halving add 16 – SHADD8 {Rd,} Rn, Rm Signed halving add 8 – SHASX {Rd,} Rn, Rm Signed halving add and subtract with exchange – SHSAX {Rd,} Rn, Rm Signed halving add and subtract with exchange – SHSUB16 {Rd,} Rn, Rm Signed halving subtract 16 – SHSUB8 {Rd,} Rn, Rm Signed halving subtract 8 – SMLABB, SMLABT,
SMLATB, SMLATT SMLAD, SMLADX Rd, Rn, Rm, Ra Signed multiply accumulate dual Q SMLAL RdLo, RdHi, Rn, Rm Signed long multiply with accumulate (32×32+64), 64-bit
SMLALBB, SMLALBT, SMLALTB, SMLALTT
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed multiply accumulate long dual – SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed multiply accumulate, word by halfword Q SMLSD, SMLSDX Rd, Rn, Rm, Ra Signed multiply subtract dual Q SMLSLD, SMLSLDX RdLo, RdHi, Rn, Rm Signed multiply subtract long dual Q SMMLA Rd, Rn, Rm, Ra Signed most significant word multiply accumulate – SMMLS, SMMLR Rd, Rn, Rm, Ra Signed most significant word multiply subtract – SMMUL, SMMULR {Rd,} Rn, Rm Signed most significant word multiply – SMUAD SMUADX {Rd,} Rn, Rm Signed dual multiply add Q SMULBB, SMULBT,
SMULTB, SMULTT SMULL RdLo, RdHi, Rn, Rm Signed long multiply (32×32), 64-bit result – SMULWB, SMULWT {Rd,} Rn, Rm Signed multiply by halfword – SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual multiply subtract – SSAT Rd, #n, Rm {,shift #s} Signed saturate Q SSAT16 Rd, #n, Rm Signed saturate 16 Q SSAX {Rd,} Rn, Rm Saturating subtract and add with exchange GE SSUB16 {Rd,} Rn, Rm Signed subtract 16 – SSUB8 {Rd,} Rn, Rm Signed subtract 8 – STM Rn{!}, reglist Store multiple registers, increment after – STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement before – STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after – STR Rt, [Rn {, #offset}] Store register word – STRB, STRBT Rt, [Rn {, #offset}] Store register byte – STRD Rt, Rt2, [Rn {, #offset}] Store register two words – STREX Rt, Rt, [Rn {, #offset}] Store register exclusive – STREXB Rd, Rt, [Rn] Store register exclusive byte – STREXH Rd, Rt, [Rn] Store register exclusive halfword – STRH, STRHT Rt, [Rn {, #offset}] Store register halfword – STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte – STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword – STRT Rt, [Rn {, #offset}] Store register word –
Rd, Rn, Rm, Ra Signed multiply accumulate long (halfwords) Q
–
result
RdLo, RdHi, Rn, Rm Signed multiply accumulate long (halfwords) –
{Rd,} Rn, Rm Signed multiply halfwords –
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Table 2-10. Cortex®-M4 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V SVC #imm Supervisor call – SXTAB {Rd,} Rn, Rm, {,ROR #} Extend 8 bits to 32 and add – SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add – SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add – SXTB16 {Rd,} Rm {,ROR #n} Signed extend byte 16 – SXTB {Rd,} Rm {,ROR #n} Sign extend a byte – SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword – TBB [Rn, Rm] Table branch byte – TBH [Rn, Rm, LSL #1] Table branch halfword – TEQ Rn, Op2 Test equivalence N,Z,C TST Rn, Op2 Test N,Z,C UADD16 {Rd,} Rn, Rm Unsigned add 16 GE UADD8 {Rd,} Rn, Rm Unsigned add 8 GE UASX {Rd,} Rn, Rm Unsigned add and subtract with exchange GE UHADD16 {Rd,} Rn, Rm Unsigned halving add 16 – UHADD8 {Rd,} Rn, Rm Unsigned halving add 8 – UHASX {Rd,} Rn, Rm Unsigned halving add and subtract with exchange – UHSAX {Rd,} Rn, Rm Unsigned halving subtract and add with exchange – UHSUB16 {Rd,} Rn, Rm Unsigned halving subtract 16 – UHSUB8 {Rd,} Rn, Rm Unsigned halving subtract 8 – UBFX Rd, Rn, #lsb, #width Unsigned bit field extract – UDIV {Rd,} Rn, Rm Unsigned divide – UMAAL RdLo, RdHi, Rn, Rm Unsigned long multiply with accumulate accumulate
(32×32+32+32), 64-bit result
UMLAL RdLo, RdHi, Rn, Rm Unsigned long multiply with accumulate (32×32+64), 64-bit
result UMULL RdLo, RdHi, Rn, Rm Unsigned long multiply (32×32), 64-bit result – UQADD16 {Rd,} Rn, Rm Unsigned saturating add 16 – UQADD8 {Rd,} Rn, Rm Unsigned saturating add 8 – UQASX {Rd,} Rn, Rm Unsigned saturating add and subtract with exchange – UQSAX {Rd,} Rn, Rm Unsigned saturating subtract and add with exchange – UQSUB16 {Rd,} Rn, Rm Unsigned saturating subtract 16 – UQSUB8 {Rd,} Rn, Rm Unsigned saturating subtract 8 – USAD8 {Rd,} Rn, Rm Unsigned sum of absolute differences – USADA8 {Rd,} Rn, Rm, Ra Unsigned sum of absolute differences and accumulate – USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q USAT16 Rd, #n, Rm Unsigned saturate 16 Q USAX {Rd,} Rn, Rm Unsigned subtract and add with exchange GE USUB16 {Rd,} Rn, Rm Unsigned subtract 16 GE USUB8 {Rd,} Rn, Rm Unsigned subtract 8 GE UXTAB {Rd,} Rn, Rm, {,ROR #} Rotate, extend 8 bits to 32 and add – UXTAB16 {Rd,} Rn, Rm, {,ROR #} Rotate, dual extend 8 bits to 16 and add – UXTAH {Rd,} Rn, Rm, {,ROR #} Rotate, unsigned extend and add halfword –
–
–
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Table 2-10. Cortex®-M4 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
UXTB {Rd,} Rm, {,ROR #n} Zero extend a byte – UXTB16 {Rd,} Rm, {,ROR #n} Unsigned extend byte 16 – UXTH {Rd,} Rm, {,ROR #n} Zero extend a halfword – WFE – Wait for event – WFI – Wait for interrupt –
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Chapter 3

Cortex®-M4 Peripherals

3.1 Overview......................................................................................................................................................................70
3.2 Functional Description...............................................................................................................................................70
3.3 Register Map...............................................................................................................................................................72
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3.1 Overview

This chapter provides information on the CC32xx implementation of the Cortex®-M4 application processor in CC32xx peripherals, including:
• SysTick (see Section 3.2.1) – Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism.
• Nested Vectored Interrupt Controller (NVIC) (see Section 3.2.2) – Facilitates low-latency exception and interrupt handling, controls power management, and implements system control registers.
• System Control Block (SCB) (see Section 3.2.3) – Provides system implementation information and system control, including configuration, control, and reporting of system exceptions.
Table 3-1 shows the address map of the private peripheral bus (PPB). Some peripheral register regions are split
into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address Core Peripheral
0xE000.E010 to 0xE000.E01F System timer 0xE000.E100 to 0xE000.E4EF Nested vectored interrupt controller 0xE000.EF00 to 0xE000.EF03 0xE000.E008 to 0xE000.E00F
0xE000.ED00 to 0xE000.ED3F
System control block

3.2 Functional Description

This chapter provides information on the CC32xx implementation of the Cortex®-M4 application processor in CC32xx peripherals: SysTick, NVIC, and SCB.

3.2.1 System Timer (SysTick)

SysTick is an integrated system timer which provides a simple, 24-bit clear-on-write, decrementing, wrap-on­zero counter with a flexible control mechanism. The counter can be used in several different ways:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine
• A high-speed alarm timer using the system clock
• A variable rate alarm or signal timer – The duration is range-dependent on the reference clock used and the dynamic range of the counter.
• A simple counter measuring time to completion and time used
• An internal clock source control based on missing or meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop.
When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches 0, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers.
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The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick counter follows:
1. Program the value in the STRELOAD register.
2. Clear the STCURRENT register by writing any value to it.
3. Configure the STCTRL register for the required operation.
Note
When the processor is halted for debugging, the counter does not decrement.

3.2.2 Nested Vectored Interrupt Controller (NVIC)

This section describes the NVIC and the registers it uses. The NVIC supports:
• A programmable priority level of 0 to 7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
• Low-latency exception and interrupt handling
• Level and pulse detection of interrupt signals
• Dynamic reprioritization of interrupts
• Grouping of priority values into group priority and subpriority fields
• Interrupt tail-chaining
• An external nonmaskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low-latency exception handling.
3.2.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge­triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically, this happens because the interrupt service routine (ISR) accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see Section
3.2.2.2 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor
returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.2.2.2 Hardware and Software Control of Interrupts
The Cortex®-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
• The NVIC detects that the interrupt signal is high and the interrupt is not active.
• The NVIC detects a rising edge on the interrupt signal.
• Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a software-generated interrupt pending. See the INT bit in the PEND0 register or SWTRIG register.
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A pending interrupt remains pending until one of the following conditions occurs:
• The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt
signal. If the signal is asserted, the state of the interrupt changes to PENDING, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to INACTIVE.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed, the state of
the interrupt changes to PENDING and ACTIVE. In this case, when the processor returns from the ISR the state of the interrupt changes to PENDING, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to INACTIVE.
• Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not
change. Otherwise, the state of the interrupt changes to INACTIVE.
– For a pulse interrupt, the state of the interrupt changes to INACTIVE if the state was PENDING, or to
ACTIVE if the state was ACTIVE and PENDING.

3.2.3 System Control Block (SCB)

The SCB provides system implementation information and system control, including configuration, control, and reporting of the system exceptions.

3.3 Register Map

Table 3-2 lists the Cortex®-M4 Peripheral SysTick, NVIC, and SCB registers. The offset listed is a hexadecimal
increment to the address of the register, relative to the core peripherals base address of 0xE000 E000.
Note
Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address.
Table 3-2. Peripherals Register Map
Offset Name Type Reset Description
System Timer (SysTick) Registers
0x010 STCTRL R/W 0x0000.0000 SysTick Control and Status Register 0x014 STRELOAD R/W – SysTick Reload Value Register 0x018 STCURRENT R/WC – SysTick Current Value Register
Nested Vectored Interrupt Controller (NVIC) Registers
0x100 EN0 R/W 0x0000.0000 Interrupt 0 to 31 Set Enable 0x104 EN1 R/W 0x0000.0000 Interrupt 32 to 63 Set Enable 0x108 EN2 R/W 0x0000.0000 Interrupt 64 to 95 Set Enable 0x10C EN3 R/W 0x0000.0000 Interrupt 96 to 127 Set Enable 0x110 EN4 R/W 0x0000.0000 Interrupt 128 to 159 Set Enable 0x114 EN5 R/W 0x0000.0000 Interrupt 160 to 191 Set Enable 0x118 EN6 R/W 0x0000.0000 Interrupt 192 to 199 Set Enable 0x180 DIS0 R/W 0x0000.0000 Interrupt 0 to 31 Clear Enable 0x184 DIS1 R/W 0x0000.0000 Interrupt 32 to 63 Clear Enable 0x188 DIS2 R/W 0x0000.0000 Interrupt 64 to 95 Clear Enable 0x18C DIS3 R/W 0x0000.0000 Interrupt 96 to 127 Clear Enable 0x190 DIS4 R/W 0x0000.0000 Interrupt 128 to 159 Clear Enable 0x194 DIS5 R/W 0x0000.0000 Interrupt 160 to 191 Clear Enable
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Table 3-2. Peripherals Register Map (continued)
Offset Name Type Reset Description
0x198 DIS6 R/W 0x0000.0000 Interrupt 192 to 199 Clear Enable 0x200 PEND0 R/W 0x0000.0000 Interrupt 0 to 31 Set Pending 0x204 PEND1 R/W 0x0000.0000 Interrupt 32 to 63 Set Pending 0x208 PEND2 R/W 0x0000.0000 Interrupt 64 to 95 Set Pending 0x20C PEND3 R/W 0x0000.0000 Interrupt 96 to 127 Set Pending 0x210 PEND4 R/W 0x0000.0000 Interrupt 128 to 159 Set Pending 0x214 PEND5 R/W 0x0000.0000 Interrupt 160 to 191 Set Pending 0x218 PEND6 R/W 0x0000.0000 Interrupt 192 to 199 Set Pending 0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0 to 31 Clear Pending 0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32 to 63 Clear Pending 0x288 UNPEND2 R/W 0x0000.0000 Interrupt 64 to 95 Clear Pending 0x28C UNPEND3 R/W 0x0000.0000 Interrupt 96 to 127 Clear Pending 0x290 UNPEND4 R/W 0x0000.0000 Interrupt 128 to 159 Clear Pending 0x294 UNPEND5 R/W 0x0000.0000 Interrupt 160 to 191 Clear Pending 0x298 UNPEND6 R/W 0x0000.0000 Interrupt 192 to 199 Clear Pending 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0 to 31 Active Bit 0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32 to 63 Active Bit 0x308 ACTIVE2 RO 0x0000.0000 Interrupt 64 to 95 Active Bit 0x30C ACTIVE3 RO 0x0000.0000 Interrupt 96 to 127 Active Bit 0x310 ACTIVE4 RO 0x0000.0000 Interrupt 128 to 159 Active Bit 0x314 ACTIVE5 RO 0x0000.0000 Interrupt 160 to 191 Active Bit 0x318 ACTIVE6 RO 0x0000.0000 Interrupt 192 to 199 Active Bit 0x400 PRI0 R/W 0x0000.0000 Interrupt 0 to 3 Priority 0x404 PRI1 R/W 0x0000.0000 Interrupt 4 to 7 Priority 0x408 PRI2 R/W 0x0000.0000 Interrupt 8 to 11 Priority 0x40C PRI3 R/W 0x0000.0000 Interrupt 12 to 15 Priority 0x410 PRI4 R/W 0x0000.0000 Interrupt 16 to 19 Priority 0x414 PRI5 R/W 0x0000.0000 Interrupt 20 to 23 Priority 0x418 PRI6 R/W 0x0000.0000 Interrupt 24 to 27 Priority 0x41C PRI7 R/W 0x0000.0000 Interrupt 28 to 31 Priority 0x420 PRI8 R/W 0x0000.0000 Interrupt 32 to 35 Priority 0x424 PRI9 R/W 0x0000.0000 Interrupt 36 to 39 Priority 0x428 PRI10 R/W 0x0000.0000 Interrupt 40 to 43 Priority 0x42C PRI11 R/W 0x0000.0000 Interrupt 44 to 47 Priority 0x430 PRI12 R/W 0x0000.0000 Interrupt 48 to 51 Priority 0x434 PRI13 R/W 0x0000.0000 Interrupt 52 to 55 Priority 0x438 PRI14 R/W 0x0000.0000 Interrupt 56 to 59 Priority 0x43C PRI15 R/W 0x0000.0000 Interrupt 60 to 63 Priority 0x440 PRI16 R/W 0x0000.0000 Interrupt 64 to 67 Priority 0x444 PRI17 R/W 0x0000.0000 Interrupt 68 to 71 Priority 0x448 PRI18 R/W 0x0000.0000 Interrupt 72 to 75 Priority 0x44C PRI19 R/W 0x0000.0000 Interrupt 76 to 79 Priority 0x450 PRI20 R/W 0x0000.0000 Interrupt 80 to 83 Priority 0x454 PRI21 R/W 0x0000.0000 Interrupt 84 to 87 Priority 0x458 PRI22 R/W 0x0000.0000 Interrupt 88 to 91 Priority
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Table 3-2. Peripherals Register Map (continued)
Offset Name Type Reset Description
0x45C PRI23 R/W 0x0000.0000 Interrupt 92 to 95 Priority 0x460 PRI24 R/W 0x0000.0000 Interrupt 96 to 99 Priority 0x464 PRI25 R/W 0x0000.0000 Interrupt 100 to 103 Priority 0x468 PRI26 R/W 0x0000.0000 Interrupt 104 to 107 Priority 0x46C PRI27 R/W 0x0000.0000 Interrupt 108 to 111 Priority 0x470 PRI28 R/W 0x0000.0000 Interrupt 112 to 115 Priority 0x474 PRI29 R/W 0x0000.0000 Interrupt 116 to 119 Priority 0x478 PRI30 R/W 0x0000.0000 Interrupt 120 to 123 Priority 0x47C PRI31 R/W 0x0000.0000 Interrupt 124 to 127 Priority 0x480 PRI32 R/W 0x0000.0000 Interrupt 128 to 131 Priority 0x484 PRI33 R/W 0x0000.0000 Interrupt 132 to 135 Priority 0x488 PRI34 R/W 0x0000.0000 Interrupt 136 to 139 Priority 0x48C PRI35 R/W 0x0000.0000 Interrupt 140 to 143 Priority 0x490 PRI36 R/W 0x0000.0000 Interrupt 144 to 147 Priority 0x494 PRI37 R/W 0x0000.0000 Interrupt 148 to 151 Priority 0x498 PRI38 R/W 0x0000.0000 Interrupt 152 to 155 Priority 0x49C PRI39 R/W 0x0000.0000 Interrupt 156 to 159 Priority 0x4A0 PRI40 R/W 0x0000.0000 Interrupt 160 to 163 Priority 0x4A4 PRI41 R/W 0x0000.0000 Interrupt 164 to 167 Priority 0x4A8 PRI42 R/W 0x0000.0000 Interrupt 168 to 171 Priority 0x4AC PRI43 R/W 0x0000.0000 Interrupt 172 to 175 Priority 0x4B0 PRI44 R/W 0x0000.0000 Interrupt 176 to 179 Priority 0x4B4 PRI45 R/W 0x0000.0000 Interrupt 180 to 183 Priority 0x4B8 PRI46 R/W 0x0000.0000 Interrupt 184 to 187 Priority 0x4BC PRI47 R/W 0x0000.0000 Interrupt 188 to 191 Priority 0x4C0 PRI48 R/W 0x0000.0000 Interrupt 192 to 195 Priority 0x4C4 PRI49 R/W 0x0000.0000 Interrupt 196 to 199 Priority 0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt
System Control Block (SCB) Registers
0x008 ACTLR R/W 0x0000.0000 Auxiliary Control 0xD00 CPUID RO 0x410F.C241 CPU ID Base 0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 0xD10 SYSCTRL R/W 0x0000.0000 System Control 0xD14 CFGCTRL R/W 0x0000.0200 Configuration and Control 0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 0xD34 MMADDR R/W – Memory Management Fault Address 0xD38 FAULTADDR R/W – Bus Fault Address
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3.3.1 Cortex Registers

Table 3-3 lists the memory-mapped Cortex registers. All register offset addresses not listed in Table 3-3 should
be considered as reserved locations and the register contents should not be modified. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base
address of 0xE000.E000.
Note
Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address.
Table 3-3. Cortex Registers
Offset Acronym Register Name Section
8h ACTLR Auxiliary Control Section 3.3.1.1 10h STCTRL SysTick Control and Status Register Section 3.3.1.2 14h STRELOAD SysTick Reload Value Register Section 3.3.1.3 18h STCURRENT SysTick Current Value Register Section 3.3.1.4
100h to 118h EN_0 to EN_6 Interrupt Set Enable Section 3.3.1.5 180h to 198h DIS_0 to DIS_6 Interrupt Clear Enable Section 3.3.1.6 200h to 218h PEND_0 to PEND_6 Interrupt Set Pending Section 3.3.1.7 280h to 298h UNPEND_0 to UNPEND_6 Interrupt Clear Pending Section 3.3.1.8 300h to 318h ACTIVE_0 to ACTIVE_6 Interrupt Active Bit Section 3.3.1.9
400h to 4C4h PRI_0 to PRI_49 Interrupt Priority Section 3.3.1.10
D00h CPUID CPU ID Base Section 3.3.1.11 D04h INTCTRL Interrupt Control and State Section 3.3.1.12 D08h VTABLE Vector Table Offset Section 3.3.1.13 D0Ch APINT Application Interrupt and Reset Control Section 3.3.1.14 D10h SYSCTRL System Control Section 3.3.1.15 D14h CFGCTRL Configuration Control Section 3.3.1.16 D18h SYSPRI1 System Handler Priority 1 Section 3.3.1.17 D1Ch SYSPRI2 System Handler Priority 2 Section 3.3.1.18 D20h SYSPRI3 System Handler Priority 3 Section 3.3.1.19 D24h SYSHNDCTRL System Handler Control and State Section 3.3.1.20 D28h FAULTSTAT Configurable Fault Status Section 3.3.1.21 D2Ch HFAULTSTAT Hard Fault Status Section 3.3.1.22 D38h FAULTDDR Bus Fault Address Section 3.3.1.23 F00h SWTRIG Software Trigger Interrupt Section 3.3.1.24
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3.3.1.1 ACTLR Register (Offset = 8h) [reset = 0h]
ACTLR is shown in Figure 3-1 and described in Table 3-4. Return to Table 3-3. The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map,
and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 application processor in the CC32xx, and does not normally require modification.
Note
This register can only be accessed from privileged mode.
Figure 3-1. ACTLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DISOOFP DISFPCA
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DISFOLD DISWBUF DISMCYC
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-4. ACTLR Register Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R 0h
9 DISOOFP R/W 0h
8 DISFPCA R/W 0h
7-3 RESERVED R 0h
2 DISFOLD R/W 0h
Disable out-of-order floating point N/A for the CC32xx.
Disable IT Folding In some situations, the processor can start executing the first
instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding.
0h = No effect. 1h = Disables IT folding.
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Table 3-4. ACTLR Register Field Descriptions (continued)
Bit Field Type Reset Description
1 DISWBUF R/W 0h
0 DISMCYC R/W 0h
Disable IT Folding In some situations, the processor can start executing the first
instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance. However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding.
0h = No effect. 1h = Disables IT folding.
Disable Interrupts of Multiple Cycle Instructions In this situation, the interrupt latency of the processor is increased
because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler.
0h = No effect. 1h = Disables interruption of load multiple and store multiple
instructions.
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3.3.1.2 STCTRL Register (Offset = 10h) [reset = 0h]
STCTRL is shown in Figure 3-2 and described in Table 3-5. Return to Table 3-3. The SysTick (STCTRL) register enables the SysTick features.
Note
This register can only be accessed from privileged mode.
Figure 3-2. STCTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED COUNT
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLK_SRC INTEN ENABLE
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-5. STCTRL Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 COUNT R 0h
15-3 RESERVED R 0h
2 CLK_SRC R/W 0h
1 INTEN R/W 0h
Count Flag This bit is cleared by a read of the register or if the STCURRENT
register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM Debug Interface V5 Architecture Specification for more information on MasterType.
0h = The SysTick timer has not counted to 0 since the last time this bit was read.
1h = The SysTick timer has counted to 0 since the last time this bit was read.
Clock Source 0h = Precision internal oscillator (PIOSC) divided by 4 1h = System clock
Interrupt Enable 0h = Interrupt generation is disabled. Software can use the COUNT
bit to determine if the counter has ever reached 0. 1h = An interrupt is generated to the NVIC when SysTick counts to 0.
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Table 3-5. STCTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
0 ENABLE R/W 0h
Enable 0h = The counter is disabled. 1h = Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting.
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3.3.1.3 STRELOAD Register (Offset = 14h) [reset = 0h]
STRELOAD is shown in Figure 3-3 and described in Table 3-6. Return to Table 3-3. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. To access this register correctly, the system clock must be faster than 8 MHz.
Note
This register can only be accessed from privileged mode.
Figure 3-3. STRELOAD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RELOAD
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-6. STRELOAD Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-0 RELOAD R/W 0h
Reload Value Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
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3.3.1.4 STCURRENT Register (Offset = 18h) [reset = 0h]
STCURRENT is shown in Figure 3-4 and described in Table 3-7. Return to Table 3-3. The STCURRENT register contains the current value of the SysTick counter.
Note
This register can only be accessed from privileged mode.
Figure 3-4. STCURRENT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CURRENT
R-0h R/WC-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-7. STCURRENT Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-0 CURRENT R/WC 0h
Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register.
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3.3.1.5 EN_0 to EN_6 Register (offset = 100h to 118h) [reset = 0h]
EN_0 to EN_6 is shown in Figure 3-5 and described in Table 3-8. The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of EN4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of EN5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of EN6 corresponds to interrupt 192; bit 7 corresponds to interrupt 199. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
Note
This register can only be accessed from privileged mode.
Figure 3-5. EN_0 to EN_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-8. EN_0 to EN_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Enable A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, enables the interrupt. 1h (R) = On a read, indicates the interrupt is enabled.
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3.3.1.6 DIS_0 to DIS_6 Register (offset = 180h to 198h) [reset = 0h]
DIS_0 to DIS_6 is shown in Figure 3-6 and described in Table 3-9. The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31.
Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of DIS5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of DIS6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199.
Note
This register can only be accessed from privileged mode.
Figure 3-6. DIS_0 to DIS_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-9. DIS_0 to DIS_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Disable EN5 (for DIS5) register; EN6 (for DIS6) register 0h (R) = On a read, indicates the interrupt is disabled. 1h (W) = On a write, no effect. 1h (R) = On a read, indicates the interrupt is enabled.
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3.3.1.7 PEND_0 to PEND_6 Register (offset = 200h to 218h) [reset = 0h]
PEND_0 to PEND_6 is shown in Figure 3-7 and described in Table 3-10. The PENDn registers force interrupts into the pending state and show which interrupts are pending. Bit 0 of
PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt
95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of PEND4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of PEND5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of PEND6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199.
Note
This register can only be accessed from privileged mode.
Figure 3-7. PEND_0 to PEND_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-10. PEND_0 to PEND_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Set Pending If the corresponding interrupt is already pending, setting a bit has no
effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 (for PEND0 to PEND3) register.
UNPEND4 (for PEND4) register UNPEND5 (for PEND5) register UNPEND6 (for PEND6) register 0h (W) = On a write, no effect. 0h (R) = On a read, indicates that the interrupt is not pending. 1h (W) = On a write, the corresponding interrupt is set to pending
even if it is disabled. 1h (R) = On a read, indicates that the interrupt is pending.
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3.3.1.8 UNPEND_0 to UNPEND_6 Register (offset = 280h to 298h) [reset = 0h]
UNPEND_0 to UNPEND_6 is shown in Figure 3-8 and described in Table 3-11. The UNPENDn registers show which interrupts are pending and remove the pending state from interrupts. Bit 0
of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of UNPEND4 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 159. Bit 0 of UNPEND5 corresponds to Interrupt 160; bit 31 corresponds to interrupt 191. Bit 0 of UNPEND6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199.
Note
This register can only be accessed from privileged mode.
Figure 3-8. UNPEND_0 to UNPEND_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Clear Pending Setting a bit does not affect the active state of the corresponding
interrupt. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates that the interrupt is not pending. 1h (W) = On a write, clears the corresponding INT[n] bit in the
PEND0 (for UNPEND0 to UNPEND3) register; PEND4 (for UNPEND4) register; PEND5 (for UNPEND5) register; PEND6 (for UNPEND6) register; so that interrupt [n] is no longer pending.
1h (R) = On a read, indicates that the interrupt is pending.
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3.3.1.9 ACTIVE_0 to ACTIVE_6 Register (offset = 300h to 318h) [reset = 0h]
ACTIVE_0 to ACTIVE_6 is shown in Figure 3-9 and described in Table 3-12. The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to Interrupt 0; bit 31
corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of ACTIVE4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of ACTIVE5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of ACTIVE6 corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199.
CAUTION
Do not manually set or clear the bits in this register.
Figure 3-9. ACTIVE_0 to ACTIVE_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-12. ACTIVE_0 to ACTIVE_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R 0h
Interrupt Active 0h = The corresponding interrupt is not active. 1h = The corresponding interrupt is active, or active and pending.
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3.3.1.10 PRI_0 to PRI_49 Register (offset = 400h to 4C4h) [reset = 0h]
PRI_0 to PRI_49 is shown in Figure 3-10 and described in Table 3-13. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each
register holds four priority fields that are assigned to interrupts as follows: bits 31 to 29 have interrupt [4n+3], bits 23 to 21 have interrupt [4n+2], bits 15 to 13 have interrupt [4n+1], and bits 7 to have interrupt [4n]. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register indicates the position of the binary point that splits the priority and subpriority fields.
Note
This register can only be accessed from privileged mode.
Figure 3-10. PRI_0 to PRI_49 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTD RESERVED INTC RESERVED
R/W-0h R-0h R/W-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTB RESERVED INTA RESERVED
R/W-0h R-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-13. PRI_0 to PRI_49 Register Field Descriptions
Bit Field Type Reset Description
31-29 INTD R/W 0h
28-24 RESERVED R 0h 23-21 INTC R/W 0h
20-16 RESERVED R 0h 15-13 INTB R/W 0h
12-8 RESERVED R 0h
7-5 INTA R/W 0h
4-0 RESERVED R 0h
Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt.
Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt.
Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt.
Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt.
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3.3.1.11 CPUID Register (Offset = D00h) [reset = 410FC241h]
CPUID is shown in Figure 3-11 and described in Table 3-14. Return to Table 3-3. The CPUID register contains the ARM Cortex-M4 processor part number, version, and implementation
information.
Note
This register can only be accessed from privileged mode.
Figure 3-11. CPUID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMP VAR CON PARTNO REV
R-41h R-0h R-Fh R-C24h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-14. CPUID Register Field Descriptions
Bit Field Type Reset Description
31-24 IMP R 41h
23-20 VAR R 0h
19-16 CON R Fh
15-4 PARTNO R C24h
3-0 REV R 1h
Implementer Code 41h = ARM
Variant Number 0h = The rn value in the rnpn product revision identifier, for example,
the 0 in r0p0.
Constant Value Description 0xF Always reads as 0xF.
Part Number C24h = Cortex-M4 application processor in CC32xx.
Revision Number 1h = The pn value in the rnpn product revision identifier; for example,
the 1 in r0p1.
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3.3.1.12 INTCTRL Register (Offset = D04h) [reset = 0h]
INTCTRL is shown in Figure 3-12 and described in Table 3-15. Return to Table 3-3.
Figure 3-12. INTCTRL Register
31 30 29 28 27 26 25 24
NMISET RESERVED PENDSV UNPENDSV PENDSTSET PENDSTCLR RESERVED
R/W-0h R-0h R/W-0h W-0h R/W-0h W-0h R-0h
23 22 21 20 19 18 17 16
ISRPRE ISRPEND RESERVED VECPEND
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
VECPEND RETBASE RESERVED
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
VECACT
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-15. INTCTRL Register Field Descriptions
Bit Field Type Reset Description
31 NMISET R/W 0h
30-29 RESERVED R 0h
28 PENDSV R/W 0h
27 UNPENDSV W 0h
NMI Set Pending Because NMI is the highest-priority exception, normally the
processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
0h (W) = On a write, no effect. 0h (R) = On a read, indicates an NMI exception is not pending. 1h (W) = On a write, changes the NMI exception state to pending. 1h (R) = On a read, indicates an NMI exception is pending.
PendSV Set Pending Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates a PendSV exception is not pending. 1h (W) = On a write, changes the PendSV exception state to
pending. 1h (R) = On a read, indicates a PendSV exception is pending.
PendSV Clear Pending This bit is write onl on a register read, its value is unknown. 0h = On a write, no effect. 1h = On a write, removes the pending state from the PendSV
exception.
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Table 3-15. INTCTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
26 PENDSTSET R/W 0h
25 PENDSTCLR W 0h
24 RESERVED R 0h 23 ISRPRE R 0h
22 ISRPEND R 0h
21-20 RESERVED R 0h
SysTick Set Pending This bit is cleared by writing a 1 to the PENDSTCLR bit. 0h (W) = On a write, no effect. 0h (R) = On a read, indicates a SysTick exception is not pending. 1h (W) = On a write, changes the SysTick exception state to
pending. 1h (R) = On a read, indicates a SysTick exception is pending.
SysTick Clear Pending This bit is write only on a register read, its value is unknown. 0h = On a write, no effect. 1h = On a write, removes the pending state from the SysTick
exception.
Debug Interrupt Handling This bit is only meaningful in debug mode, and reads as zero when
the processor is not in debug mode. 0h = The release from halt does not take an interrupt. 1h = The release from halt takes an interrupt.
Interrupt Pending This bit provides status for all interrupts excluding NMI and faults. 0h = No interrupt is pending. 1h = An interrupt is pending.
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Table 3-15. INTCTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
19-12 VECPEND R 0h
11
RETBASE R 0h
10-8 RESERVED R 0h
7-0 VECACT R 0h
Interrupt Pending Vector Number This field contains the exception number of the highest priority
pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
0h = No exceptions are pending 1h = Reserved 2h = NMI 3h = Hard fault 4h = Memory management fault 5h = Bus fault 6h = Usage fault 7h- Ah = Reserved Bh = SVCall Ch = Reserved for Debug Dh = Reserved Eh = PendSV Fh = SysTick 10h = Interrupt Vector 0 11h = Interrupt Vector 1 ... D9h = Interrupt Vector 199
Return to Base This bit provides status for all interrupts excluding NMI and faults.
This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero).
0h = There are preempted active exceptions to execute. 1h = There are no active exceptions, or the currently executing
exception is the only active exception.
Interrupt Pending Vector Number This field contains the active exception number. The exception
numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode.
This field contains the same value as the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers.
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3.3.1.13 VTABLE Register (Offset = D08h) [reset = 0h]
VTABLE is shown in Figure 3-13 and described in Table 3-16. Return to Table 3-3. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000.
Note
This register can only be accessed from privileged mode.
Figure 3-13. VTABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET RESERVED
R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-16. VTABLE Register Field Descriptions
Bit Field Type Reset Description
31-10 OFFSET R/W 0h
9-0 RESERVED R 0h
Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 199 interrupts, the offset must be aligned on a 1024-byte boundary.
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3.3.1.14 APINT Register (Offset = D0Ch) [reset = FA050000h]
APINT is shown in Figure 3-14 and described in Table 3-17. Return to Table 3-3. The APINT register provides priority grouping control for the exception model, endian status for data accesses,
and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note
This register can only be accessed from privileged mode.
Note
Determining preemption of an exception uses only the group priority field. PRIGROUP Bit Field = Binary Point = Group Priority Field = Subpriority Field = Group Priorities =
Subpriorities 0h-4h = bxxx = [7:5] = None = 8 = 1 5h = bxx.y = [7:6] = [5] = 4 = 2 6h = bx.yy = [7] = [6:5] = 2 = 4 7h = b.yyy = None = [7:5] = 1 = 8 INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a
subpriority field bit.
Figure 3-14. APINT Register
31 30 29 28 27 26 25 24
VECTKEY
R/W-FA05h
23 22 21 20 19 18 17 16
VECTKEY
R/W-FA05h
15 14 13 12 11 10 9 8
ENDIANESS RESERVED PRIGROUP
R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED SYSRESREQ VECTCLRACT VECTRESET
R-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-17. APINT Register Field Descriptions
Bit Field Type Reset Description
31-16 VECTKEY R/W FA05h
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Register Key This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned.
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Table 3-17. APINT Register Field Descriptions (continued)
Bit Field Type Reset Description
15 ENDIANESS R 0h
14-11 RESERVED R 0h
10-8 PRIGROUP R/W 0h
7-3 RESERVED R 0h
2 SYSRESREQ W 0h
1 VECTCLRACT W 0h
0 VECTRESET W 0h
Data Endianess The CC32xx implementation uses only little-endian mode, so this is
cleared to 0.
Interrupt Priority Grouping This field determines the split of group priority from subpriority
System Reset Request This bit is automatically cleared during the reset of the core and
reads as 0. 0h = No effect. 1h = Resets the core and all on-chip peripherals except the Debug
interface.
Clear Active NMI / Fault This bit is reserved for debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
System Reset This bit is reserved for debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
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3.3.1.15 SYSCTRL Register (Offset = D10h) [reset = 0h]
SYSCTRL is shown in Figure 3-15 and described in Table 3-18. Return to Table 3-3. The SYSCTRL register controls features of entry to and exit from low-power state.
Note
This register can only be accessed from privileged mode.
Figure 3-15. SYSCTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SEVONPEND RESERVED SLEEPDEEP SLEEPEXIT RESERVED
R-0h R/W-0h R-0h R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-18. SYSCTRL Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 SEVONPEND R/W 0h
3 RESERVED R 0h 2 SLEEPDEEP R/W 0h
1 SLEEPEXIT R/W 0h
0 RESERVED R 0h
Wake Up on Pending 0h = Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded. 1h = Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
Deep Sleep Enable 0h = Use Sleep mode as the low power mode. 1h = Use Deep-sleep mode as the low power mode.
Sleep on ISR Exit Setting this bit enables an interrupt-driven application to avoid
returning to an empty main application. 0h = When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode. 1h = When returning from Handler mode to Thread mode, enter
sleep or deep sleep on return from an ISR.
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3.3.1.16 CFGCTRL Register (Offset = D14h) [reset = 200h]
CFGCTRL is shown in Figure 3-16 and described in Table 3-19. Return to Table 3-3. The CFGCTRL register controls entry to Thread mode and enables:
• The handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults
• Trapping of divide by zero and unaligned accesses
• Access to the SWTRIG register by unprivileged software.
Note
This register can only be accessed from privileged mode.
Figure 3-16. CFGCTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED STKALIGN BFHFMIGN
R-0h R/W-1h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DIV0 UNALIGNED RESERVED MANIPEND BASETHR
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-19. CFGCTRL Register Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R 0h
9 STKALIGN R/W 1h
8 BFHFMIGN R/W 0h
7-5 RESERVED R 0h
Stack Alignment on Exception Entry On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment.
0h = The stack is 4-byte aligned. 1h = The stack is 8-byte aligned.
Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus
faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK-escalated handlers. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.
0h = Data bus faults caused by load and store instructions cause a lock-up.
1h = Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
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Table 3-19. CFGCTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
4 DIV0 R/W 0h
3 UNALIGNED R/W 0h
2 RESERVED R 0h 1 MANIPEND R/W 0h
0 BASETHR R/W 0h
Trap on Divide by 0 This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0. 0h = Do not trap on divide by 0. A divide by zero returns a quotient of
0. 1h = Trap on divide by 0.
Trap on Unaligned Access Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set. 0h = Do not trap on unaligned halfword and word accesses. 1h = Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
Allow Main Interrupt Trigger 0h = Disables unprivileged software access to the SWTRIG register. 1h = Enables unprivileged software access to the SWTRIG register.
Thread State Control 0h = The processor can enter Thread mode only when no exception
is active. 1h = The processor can enter Thread mode from any level under the
control of an EXC_RETURN value.
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3.3.1.17 SYSPRI1 Register (Offset = D18h) [reset = 0h]
SYSPRI1 is shown in Figure 3-17 and described in Table 3-20. Return to Table 3-3. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management
fault exception handlers. This register is byte-accessible.
Note
This register can only be accessed from privileged mode.
Figure 3-17. SYSPRI1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED USAGE RESERVED
R-0h R/W-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS RESERVED MEM RESERVED
R/W-0h R-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-20. SYSPRI1 Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h 23-21 USAGE R/W 0h
20-16 RESERVED R 0h 15-13 BUS R/W 0h
12-8 RESERVED R 0h
7-5 MEM R/W 0h
4-0 RESERVED R 0h
Usage Fault Priority This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher priority.
Bus Fault Priority This field configures the priority level of the bus fault. Configurable
priority values are in the range 0-7, with lower values having higher priority.
Memory Management Fault Priority This field configures the priority level of the memory management
fault. Configurable priority values are in the range 0-7, with lower values having higher priority.
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3.3.1.18 SYSPRI2 Register (Offset = D1Ch) [reset = 0h]
SYSPRI2 is shown in Figure 3-18 and described in Table 3-21. Return to Table 3-3. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible.
Note
This register can only be accessed from privileged mode.
Figure 3-18. SYSPRI2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVC RESERVED
R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-21. SYSPRI2 Register Field Descriptions
Bit Field Type Reset Description
31-29 SVC R/W 0h
28-0 RESERVED R 0h
SVCall Priority This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
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3.3.1.19 SYSPRI3 Register (Offset = D20h) [reset = 0h]
SYSPRI3 is shown in Figure 3-19 and described in Table 3-22. Return to Table 3-3. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This
register is byte-accessible.
Note
This register can only be accessed from privileged mode.
Figure 3-19. SYSPRI3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TICK RESERVED PENDSV RESERVED
R/W-0h R-0h R/W-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DEBUG RESERVED
R-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-22. SYSPRI3 Register Field Descriptions
Bit Field Type Reset Description
31-29 TICK R/W 0h
28-24 RESERVED R 0h 23-21 PENDSV R/W 0h
20-8 RESERVED R 0h
7-5 DEBUG R/W 0h
4-0 RESERVED R 0h
SysTick Exception Priority This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values having higher priority.
PendSV Priority This field configures the priority level of PendSV. Configurable
priority values are in the range 0-7, with lower values having higher priority.
Debug Priority This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
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