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Texas Instruments SimpleLink Wi-Fi CC323x Technical Reference Manual

SimpleLink™ Wi-Fi® CC323x
Technical Reference Manual
Literature Number: SWRU543A
JANUARY 2019 – REVISED SEPTEMBER 2020
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Table of Contents

Read This First.........................................................................................................................................................................25
Audience................................................................................................................................................................................ 25
About This Manual................................................................................................................................................................. 25
Register Bit Conventions........................................................................................................................................................25
Glossary.................................................................................................................................................................................25
Related Documentation..........................................................................................................................................................26
Community Resources...........................................................................................................................................................26
Trademarks............................................................................................................................................................................27
1.1 Introduction...................................................................................................................................................................... 30
1.2 Architecture Overview...................................................................................................................................................... 31
1.3 Functional Overview.........................................................................................................................................................32
1.3.1 Processor Core..........................................................................................................................................................32
1.3.2 Memory......................................................................................................................................................................33
1.3.3 Micro-Direct Memory Access Controller (µDMA).......................................................................................................34
1.3.4 General-Purpose Timer (GPT).................................................................................................................................. 34
1.3.5 Watchdog Timer (WDT).............................................................................................................................................35
1.3.6 Multichannel Audio Serial Port (McASP)................................................................................................................... 35
1.3.7 Serial Peripheral Interface (SPI)................................................................................................................................36
1.3.8 Inter-Integrated Circuit (I2C) Interface.......................................................................................................................36
1.3.9 Universal Asynchronous Receiver/Transmitter (UART)............................................................................................ 36
1.3.10 General-Purpose Input/Output (GPIO).................................................................................................................... 37
1.3.11 Analog-to-Digital Converter (ADC)...........................................................................................................................37
1.3.12 SD Card Host.......................................................................................................................................................... 37
1.3.13 Parallel Camera Interface........................................................................................................................................38
1.3.14 Debug Interface.......................................................................................................................................................38
1.3.15 Hardware Cryptography Accelerator....................................................................................................................... 38
1.3.16 Clock, Reset, and Power Management................................................................................................................... 38
1.3.17 SimpleLink™ Subsystem.........................................................................................................................................39
1.3.18 I/O Pads and Pin Multiplexing................................................................................................................................. 39
2 Cortex®-M4 Processor.........................................................................................................................................................41
2.1 Overview.......................................................................................................................................................................... 42
2.1.1 Block Diagram........................................................................................................................................................... 43
2.1.2 System-Level Interface..............................................................................................................................................43
2.1.3 Integrated Configurable Debug................................................................................................................................. 43
2.1.4 Trace Port Interface Unit (TPIU)................................................................................................................................44
2.1.5 Cortex®-M4 System Component Details................................................................................................................... 44
2.2 Functional Description......................................................................................................................................................45
2.2.1 Programming Model.................................................................................................................................................. 45
2.2.2 Register Description.................................................................................................................................................. 46
2.2.3 Memory Model...........................................................................................................................................................49
2.2.4 Exception Model........................................................................................................................................................53
2.2.5 Fault Handling........................................................................................................................................................... 59
2.2.6 Power Management.................................................................................................................................................. 62
2.2.7 Instruction Set Summary........................................................................................................................................... 64
3 Cortex®-M4 Peripherals.......................................................................................................................................................69
3.1 Overview.......................................................................................................................................................................... 70
3.2 Functional Description......................................................................................................................................................70
3.2.1 System Timer (SysTick).............................................................................................................................................70
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3.2.2 Nested Vectored Interrupt Controller (NVIC).............................................................................................................71
3.2.3 System Control Block (SCB)..................................................................................................................................... 72
3.3 Register Map....................................................................................................................................................................72
3.3.1 Cortex Registers........................................................................................................................................................75
4 Direct Memory Access (DMA)............................................................................................................................................113
4.1 Overview.........................................................................................................................................................................114
4.2 Functional Description....................................................................................................................................................114
4.2.1 Channel Assignment................................................................................................................................................115
4.2.2 Priority......................................................................................................................................................................115
4.2.3 Arbitration Size.........................................................................................................................................................116
4.2.4 Channel Configuration............................................................................................................................................. 116
4.2.5 Transfer Mode..........................................................................................................................................................118
4.2.6 Transfer Size and Increment................................................................................................................................... 121
4.2.7 Peripheral Interface................................................................................................................................................. 122
4.2.8 Interrupts and Errors................................................................................................................................................122
4.3 Register Description.......................................................................................................................................................123
4.3.1 DMA Register Map.................................................................................................................................................. 123
4.3.2 µDMA Channel Control Structure............................................................................................................................124
4.3.3 DMA Registers........................................................................................................................................................ 124
4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers................................................................................ 129
5 General-Purpose Input/Outputs (GPIOs)..........................................................................................................................153
5.1 Overview........................................................................................................................................................................ 154
5.2 Functional Description....................................................................................................................................................154
5.2.1 Data Control............................................................................................................................................................ 154
5.3 Interrupt Control............................................................................................................................................................. 155
5.3.1 µDMA Trigger Source..............................................................................................................................................156
5.4 Initialization and Configuration.......................................................................................................................................156
5.5 GPIO Registers..............................................................................................................................................................158
6 Universal Asynchronous Receivers/Transmitters (UARTs)............................................................................................171
6.1 Overview........................................................................................................................................................................ 172
6.1.1 Block Diagram......................................................................................................................................................... 172
6.2 Functional Description....................................................................................................................................................173
6.2.1 Transmit and Receive Logic.................................................................................................................................... 173
6.2.2 Baud-Rate Generation.............................................................................................................................................174
6.2.3 Data Transmission...................................................................................................................................................174
6.2.4 Initialization and Configuration................................................................................................................................ 177
6.3 UART Registers............................................................................................................................................................. 179
7 Inter-Integrated Circuit (I2C) Interface.............................................................................................................................. 203
7.1 Overview........................................................................................................................................................................ 204
7.1.1 Block Diagram......................................................................................................................................................... 204
7.1.2 Signal Description....................................................................................................................................................205
7.2 Functional Description....................................................................................................................................................206
7.2.1 I2C Bus Functional Overview.................................................................................................................................. 206
7.2.2 Supported Speed Modes.........................................................................................................................................209
7.2.3 Interrupts................................................................................................................................................................. 210
7.2.4 Loopback Operation.................................................................................................................................................211
7.2.5 FIFO and µDMA Operation......................................................................................................................................211
7.2.6 Command Sequence Flow Charts...........................................................................................................................213
7.2.7 Initialization and Configuration................................................................................................................................ 220
7.3 I2C Registers................................................................................................................................................................. 221
8 SPI (Serial Peripheral Interface)........................................................................................................................................ 267
8.1 Overview........................................................................................................................................................................ 268
8.1.1 Features.................................................................................................................................................................. 268
8.2 Functional Description....................................................................................................................................................269
8.2.1 SPI...........................................................................................................................................................................269
8.2.2 SPI Transmission.....................................................................................................................................................269
8.2.3 Master Mode............................................................................................................................................................273
8.2.4 Slave Mode..............................................................................................................................................................280
8.2.5 Interrupts................................................................................................................................................................. 282
8.2.6 DMA Requests........................................................................................................................................................ 283
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8.2.7 Reset....................................................................................................................................................................... 284
8.3 Initialization and Configuration.......................................................................................................................................284
8.3.1 Basic Initialization....................................................................................................................................................284
8.3.2 Master Mode Operation Without Interrupt (Polling)................................................................................................. 284
8.3.3 Slave Mode Operation With Interrupt...................................................................................................................... 284
8.3.4 Generic Interrupt Handler Implementation.............................................................................................................. 285
8.4 Access to Data Registers...............................................................................................................................................285
8.5 Module Initialization........................................................................................................................................................286
8.5.1 Common Transfer Sequence...................................................................................................................................286
8.5.2 End-of-Transfer Sequences.....................................................................................................................................287
8.5.3 FIFO Mode.............................................................................................................................................................. 288
8.6 SPI Registers................................................................................................................................................................. 292
9 General-Purpose Timers....................................................................................................................................................309
9.1 Overview........................................................................................................................................................................ 310
9.2 Block Diagram................................................................................................................................................................310
9.3 Functional Description....................................................................................................................................................311
9.3.1 GPTM Reset Conditions..........................................................................................................................................312
9.3.2 Timer Modes............................................................................................................................................................312
9.3.3 DMA Operation........................................................................................................................................................317
9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values....................................................................................317
9.4 Initialization and Configuration.......................................................................................................................................318
9.4.1 One-Shot and Periodic Timer Mode........................................................................................................................ 318
9.4.2 Input Edge-Count Mode.......................................................................................................................................... 318
9.4.3 Input Edge-Time Mode............................................................................................................................................319
9.4.4 PWM Mode..............................................................................................................................................................319
9.5 Timer Registers..............................................................................................................................................................321
10 Watchdog Timer................................................................................................................................................................351
10.1 Overview...................................................................................................................................................................... 352
10.1.1 Block Diagram....................................................................................................................................................... 352
10.2 Functional Description..................................................................................................................................................352
10.2.1 Initialization and Configuration.............................................................................................................................. 353
10.3 WATCHDOG Registers................................................................................................................................................ 354
10.4 MCU Watchdog Controller Usage Caveats..................................................................................................................362
10.4.1 System Watchdog..................................................................................................................................................362
10.4.2 System Watchdog Recovery Sequence................................................................................................................ 364
11 SD Host Controller Interface............................................................................................................................................365
11.1 Overview.......................................................................................................................................................................366
11.2 SD Host Features.........................................................................................................................................................366
11.3 1-Bit SD Interface.........................................................................................................................................................366
11.3.1 Clock and Reset Management...............................................................................................................................368
11.4 Initialization and Configuration Using Peripheral APIs.................................................................................................368
11.4.1 Basic Initialization and Configuration.....................................................................................................................368
11.4.2 Sending Command................................................................................................................................................369
11.4.3 Card Detection and Initialization............................................................................................................................370
11.4.4 Block Read.............................................................................................................................................................371
11.4.5 Block Write.............................................................................................................................................................372
11.5 Performance and Testing..............................................................................................................................................372
11.6 Peripheral Library APIs.................................................................................................................................................373
11.7 SD-HOST Registers.....................................................................................................................................................378
12 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port....................................................................................... 407
12.1 Overview...................................................................................................................................................................... 408
12.1.1 I2S Format.............................................................................................................................................................408
12.2 Functional Description..................................................................................................................................................409
12.3 Programming Model.....................................................................................................................................................409
12.3.1 Clock and Reset Management.............................................................................................................................. 409
12.3.2 I2S Data Port Interface..........................................................................................................................................410
12.3.3 Initialization and Configuration.............................................................................................................................. 410
12.4 Peripheral Library APIs for I2S Configuration.............................................................................................................. 412
12.4.1 Basic APIs for Enabling and Configuring the Interface..........................................................................................412
12.4.2 APIs for Data Access if DMA is Not Used............................................................................................................. 414
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12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral...................................................415
12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral......................................................................... 419
12.5 I2S Registers................................................................................................................................................................421
13 Analog-to-Digital Converter (ADC)..................................................................................................................................469
13.1 Overview...................................................................................................................................................................... 470
13.2 Key Features................................................................................................................................................................470
13.3 ADC Register Mapping................................................................................................................................................ 471
13.4 ADC_MODULE Registers............................................................................................................................................ 472
13.5 Initialization and Configuration.....................................................................................................................................491
13.6 Peripheral Library APIs for ADC Operation..................................................................................................................491
13.6.1 Overview................................................................................................................................................................491
13.6.2 Configuring the ADC Channels............................................................................................................................. 491
13.6.3 Basic APIs for Enabling and Configuring the Interface..........................................................................................492
13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup].......................................................................... 493
13.6.5 APIs for Interrupt Usage........................................................................................................................................494
13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples..........................................................................497
14 Parallel Camera Interface Module................................................................................................................................... 499
14.1 Overview...................................................................................................................................................................... 500
14.2 Image Sensor Interface................................................................................................................................................500
14.3 Functional Description..................................................................................................................................................501
14.3.1 Modes of Operation...............................................................................................................................................501
14.3.2 FIFO Buffer............................................................................................................................................................503
14.3.3 Reset..................................................................................................................................................................... 503
14.3.4 Clock Generation...................................................................................................................................................503
14.3.5 Interrupt Generation.............................................................................................................................................. 504
14.3.6 DMA Interface........................................................................................................................................................504
14.4 Programming Model.....................................................................................................................................................505
14.4.1 Camera Core Reset...............................................................................................................................................505
14.4.2 Enable the Picture Acquisition...............................................................................................................................505
14.4.3 Disable the Picture Acquisition.............................................................................................................................. 506
14.5 Interrupt Handling.........................................................................................................................................................506
14.5.1 FIFO_OF_IRQ (FIFO Overflow)............................................................................................................................ 506
14.5.2 FIFO_UF_IRQ (FIFO Underflow)...........................................................................................................................506
14.6 Camera Registers........................................................................................................................................................ 507
14.7 Peripheral Library APIs................................................................................................................................................ 521
14.8 Developer’s Guide........................................................................................................................................................524
14.8.1 Using Peripheral Driver APIs for Capturing an Image........................................................................................... 524
14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors................................................................ 527
15 Power, Reset, and Clock Management........................................................................................................................... 529
15.1 Overview...................................................................................................................................................................... 530
15.1.1 Power Management Unit (PMU)............................................................................................................................530
15.1.2 VBAT Wide-Voltage Connection............................................................................................................................ 531
15.1.3 Supply Brownout and Blackout..............................................................................................................................531
15.1.4 Application Processor Power Modes.....................................................................................................................532
15.2 Power Management Control Architecture.................................................................................................................... 533
15.2.1 Global Power-Reset-Clock Manager (GPRCM).................................................................................................... 534
15.2.2 Application Reset-Clock Manager (ARCM)........................................................................................................... 536
15.3 PRCM APIs..................................................................................................................................................................536
15.3.1 MCU Initialization...................................................................................................................................................536
15.3.2 Reset Control.........................................................................................................................................................536
15.3.3 Peripheral Reset....................................................................................................................................................536
15.3.4 Reset Cause..........................................................................................................................................................537
15.3.5 Clock Control.........................................................................................................................................................537
15.3.6 Low-Power Modes.................................................................................................................................................538
15.3.7 Sleep (SLEEP)...................................................................................................................................................... 538
15.3.8 Low-Power Deep Sleep (LPDS)............................................................................................................................ 539
15.3.9 Hibernate (HIB)......................................................................................................................................................540
15.3.10 Slow Clock Counter............................................................................................................................................. 542
15.4 Peripheral Macros........................................................................................................................................................543
15.5 Power Management Framework.................................................................................................................................. 543
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15.6 PRCM Registers.......................................................................................................................................................... 543
16 I/O Pads and Pin Multiplexing..........................................................................................................................................595
16.1 Overview...................................................................................................................................................................... 596
16.2 I/O Pad Electrical Specifications.................................................................................................................................. 597
16.3 Analog and Digital Pin Multiplexing..............................................................................................................................598
16.4 Special Analog/Digital Pins.......................................................................................................................................... 598
16.4.1 Pins 45 and 52.......................................................................................................................................................598
16.4.2 Pins 29 and 30.......................................................................................................................................................598
16.4.3 Pins 57, 58, 59, and 60..........................................................................................................................................598
16.5 Analog Mux Control Registers..................................................................................................................................... 601
16.6 Pins Available for Applications..................................................................................................................................... 603
16.7 Functional Pin Mux Configurations.............................................................................................................................. 607
16.8 Pin Mapping Recommendations.................................................................................................................................. 617
16.8.1 Pad Configuration Registers for Application Pins..................................................................................................618
16.8.2 PAD Behavior During Reset and Hibernate...........................................................................................................619
16.8.3 Control Architecture...............................................................................................................................................620
16.8.4 CC32xx Pin-mux Examples...................................................................................................................................621
16.8.5 Wake on Pad.........................................................................................................................................................625
16.8.6 Sense on Power.................................................................................................................................................... 626
17 Advance Encryption Standard Accelerator (AES).........................................................................................................627
17.1 AES Overview..............................................................................................................................................................628
17.2 AES Functional Description......................................................................................................................................... 628
17.2.1 AES Block Diagram............................................................................................................................................... 628
17.2.2 AES Algorithm....................................................................................................................................................... 631
17.2.3 AES Operating Modes...........................................................................................................................................632
17.2.4 Hardware Requests...............................................................................................................................................642
17.3 AES Module Programming Guide................................................................................................................................ 643
17.3.1 AES Low-Level Programming Models...................................................................................................................643
17.4 AES Registers..............................................................................................................................................................648
18 Data Encryption Standard Accelerator (DES)................................................................................................................ 681
18.1 DES Functional Description......................................................................................................................................... 682
18.2 DES Block Diagram..................................................................................................................................................... 682
18.2.1 µDMA Control........................................................................................................................................................683
18.2.2 Interrupt Control.....................................................................................................................................................683
18.2.3 Register Interface.................................................................................................................................................. 684
18.2.4 DES Enginer..........................................................................................................................................................684
18.3 DES-Supported Modes of Operation........................................................................................................................... 684
18.3.1 ECB Feedback Mode............................................................................................................................................ 684
18.4 DES Module Programming Guide – Low-Level Programming Models........................................................................ 686
18.4.1 Surrounding Modules Global Initialization............................................................................................................. 686
18.4.2 Operational Modes Configuration..........................................................................................................................687
18.4.3 DES Events Servicing........................................................................................................................................... 689
18.5 DES Registers..............................................................................................................................................................691
19 SHA/MD5 Accelerator....................................................................................................................................................... 711
19.1 SHA/MD5 Functional Description.................................................................................................................................712
19.1.1 SHA/MD5 Block Diagram...................................................................................................................................... 712
19.1.2 µDMA and Interrupt Requests...............................................................................................................................713
19.1.3 Operation Description............................................................................................................................................713
19.1.4 SHA/MD5 Programming Guide............................................................................................................................. 719
19.2 SHA-MD5 Registers.....................................................................................................................................................723
20 Cyclical Redundancy Check (CRC).................................................................................................................................773
20.1 Functional Description..................................................................................................................................................774
20.1.1 CRC Support......................................................................................................................................................... 774
20.2 Initialization and Configuration.....................................................................................................................................776
20.2.1 CRC Initialization and Configuration......................................................................................................................776
20.3 CRC Registers............................................................................................................................................................. 777
21 On-Chip Parallel Flash..................................................................................................................................................... 783
21.1 Flash Memory Configuration........................................................................................................................................ 784
21.2 Interrupts......................................................................................................................................................................784
21.3 Flash Memory Programming........................................................................................................................................784
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21.4 32-Word Flash Memory Write Buffer............................................................................................................................785
21.5 Flash Registers............................................................................................................................................................ 786
21.6 CC323xSF Boot Flow...................................................................................................................................................799
21.7 Flash User Application and Memory Partition.............................................................................................................. 800
21.8 Programming, Bootstrapping, and Updating the Flash User Application..................................................................... 802
21.9 Image Authentication and Integrity Check................................................................................................................... 803
21.10 Debugging Flash User Application Using JTAG.........................................................................................................805
A Software Development Kit Examples...............................................................................................................................807
B CC323x Device Miscellaneous Registers........................................................................................................................ 809
23.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]......................................................................................................810
23.2 DMA_IMS Register (offset = 90h) [reset = 0h]............................................................................................................. 812
23.3 DMA_IMC Register (offset = 94h) [reset = 0h].............................................................................................................814
23.4 DMA_ICR Register (offset = 9Ch) [reset = 0h].............................................................................................................816
23.5 DMA_MIS Register (offset = A0h) [reset = 0h].............................................................................................................818
23.6 DMA_RIS Register (offset = A4h) [reset = 0h]............................................................................................................. 820
23.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]...................................................................................................... 822
Revision History.................................................................................................................................................................... 823
List of Figures
Figure 1-1. CC32xx MCU and Wi-Fi® System-on-Chip.............................................................................................................31
Figure 2-1. Application CPU Block Diagram..............................................................................................................................43
Figure 2-2. TPIU Block Diagram................................................................................................................................................44
Figure 2-3. Cortex®-M4 Register Set........................................................................................................................................ 46
Figure 2-4. Data Storage........................................................................................................................................................... 52
Figure 2-5. Vector Table.............................................................................................................................................................57
Figure 2-6. Exception Stack Frame........................................................................................................................................... 59
Figure 2-7. Power-Management Architecture in CC32xx SoC.................................................................................................. 63
Figure 3-1. ACTLR Register...................................................................................................................................................... 76
Figure 3-2. STCTRL Register.................................................................................................................................................... 78
Figure 3-3. STRELOAD Register...............................................................................................................................................80
Figure 3-4. STCURRENT Register............................................................................................................................................81
Figure 3-5. EN_0 to EN_6 Register........................................................................................................................................... 82
Figure 3-6. DIS_0 to DIS_6 Register......................................................................................................................................... 83
Figure 3-7. PEND_0 to PEND_6 Register................................................................................................................................. 84
Figure 3-8. UNPEND_0 to UNPEND_6 Register.......................................................................................................................85
Figure 3-9. ACTIVE_0 to ACTIVE_6 Register........................................................................................................................... 86
Figure 3-10. PRI_0 to PRI_49 Register..................................................................................................................................... 87
Figure 3-11. CPUID Register..................................................................................................................................................... 88
Figure 3-12. INTCTRL Register.................................................................................................................................................89
Figure 3-13. VTABLE Register...................................................................................................................................................92
Figure 3-14. APINT Register..................................................................................................................................................... 93
Figure 3-15. SYSCTRL Register............................................................................................................................................... 95
Figure 3-16. CFGCTRL Register............................................................................................................................................... 96
Figure 3-17. SYSPRI1 Register.................................................................................................................................................98
Figure 3-18. SYSPRI2 Register.................................................................................................................................................99
Figure 3-19. SYSPRI3 Register...............................................................................................................................................100
Figure 3-20. SYSHNDCTRL Register......................................................................................................................................101
Figure 3-22. HFAULTSTAT Register........................................................................................................................................109
Figure 3-23. FAULTDDR Register............................................................................................................................................110
Figure 3-24. SWTRIG Register................................................................................................................................................ 111
Figure 4-1. Ping-Pong Mode....................................................................................................................................................119
Figure 4-2. Memory Scatter-Gather Mode...............................................................................................................................120
Figure 4-3. Peripheral Scatter-Gather Mode........................................................................................................................... 121
Figure 4-5. DMA_DSTENDP Register.....................................................................................................................................125
Figure 4-6. DMA_CHCTL Register.......................................................................................................................................... 126
Figure 4-7. DMA_STAT Register............................................................................................................................................. 130
Figure 4-8. DMA_CFG Register.............................................................................................................................................. 131
Figure 4-9. DMA_CTLBASE Register......................................................................................................................................132
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Figure 4-10. DMA_ALTBASE Register....................................................................................................................................133
Figure 4-11. DMA_WAITSTAT Register...................................................................................................................................134
Figure 4-12. DMA_SWREQ Register...................................................................................................................................... 135
Figure 4-13. DMA_USEBURSTSET Register......................................................................................................................... 136
Figure 4-14. DMA_USEBURSTCLR Register......................................................................................................................... 137
Figure 4-15. DMA_REQMASKSET Register........................................................................................................................... 138
Figure 4-16. DMA_REQMASKCLR Register...........................................................................................................................139
Figure 4-17. DMA_ENASET Register......................................................................................................................................140
Figure 4-18. DMA_ENACLR Register..................................................................................................................................... 141
Figure 4-19. DMA_ALTSET Register.......................................................................................................................................142
Figure 4-20. DMA_ALTCLR Register.......................................................................................................................................143
Figure 4-23. DMA_ERRCLR Register..................................................................................................................................... 146
Figure 4-24. DMA_CHASGN Register.....................................................................................................................................147
Figure 4-25. DMA_CHMAP0 Register..................................................................................................................................... 148
Figure 4-26. DMA_CHMAP1 Register..................................................................................................................................... 149
Figure 4-27. DMA_CHMAP2 Register..................................................................................................................................... 150
Figure 4-28. DMA_CHMAP3 Register..................................................................................................................................... 151
Figure 5-1. Digital I/O Pads..................................................................................................................................................... 154
Figure 5-2. GPIODATA Write Example.................................................................................................................................... 155
Figure 5-3. GPIODATA Read Example....................................................................................................................................155
Figure 5-4. GPIODATA Register.............................................................................................................................................. 159
Figure 5-5. GPIODIR Register.................................................................................................................................................160
Figure 5-6. GPIOIS Register....................................................................................................................................................161
Figure 5-7. GPIOIBE Register................................................................................................................................................. 162
Figure 5-8. GPIOIEV Register................................................................................................................................................. 163
Figure 5-9. GPIOIM Register................................................................................................................................................... 164
Figure 5-11. GPIOMIS Register...............................................................................................................................................166
Figure 5-13. GPIO_TRIG_EN Register................................................................................................................................... 168
Figure 6-1. UART Module Block Diagram................................................................................................................................173
Figure 6-2. UART Character Frame.........................................................................................................................................173
Figure 6-3. UARTDR Register................................................................................................................................................. 180
Figure 6-4. UARTRSR_UARTECR Register........................................................................................................................... 182
Figure 6-5. UARTFR Register..................................................................................................................................................184
Figure 6-6. UARTIBRD Register..............................................................................................................................................186
Figure 6-7. UARTFBRD Register.............................................................................................................................................187
Figure 6-8. UARTLCRH Register.............................................................................................................................................188
Figure 6-9. UARTCTL Register................................................................................................................................................190
Figure 6-10. UARTIFLS Register.............................................................................................................................................192
Figure 6-11. UARTIM Register.................................................................................................................................................193
Figure 6-12. UARTRIS Register.............................................................................................................................................. 195
Figure 6-13. UARTMIS Register..............................................................................................................................................197
Figure 6-14. UARTICR Register.............................................................................................................................................. 200
Figure 6-15. UARTDMACTL Register......................................................................................................................................202
Figure 7-1. I2C Block Diagram................................................................................................................................................ 205
Figure 7-2. I2C Bus Configuration........................................................................................................................................... 206
Figure 7-3. START and STOP Conditions............................................................................................................................... 206
Figure 7-4. Complete Data Transfer With a 7-Bit Address...................................................................................................... 207
Figure 7-5. R/S Bit in First Byte............................................................................................................................................... 207
Figure 7-6. Data Validity During Bit Transfer on the I2C Bus...................................................................................................207
Figure 7-7. Master Single TRANSMIT..................................................................................................................................... 214
Figure 7-8. Master Single RECEIVE........................................................................................................................................215
Figure 7-9. Master TRANSMIT of Multiple Data Bytes............................................................................................................ 216
Figure 7-10. Master RECEIVE of Multiple Data Bytes.............................................................................................................217
Figure 7-11. Master RECEIVE with Repeated START after Master TRANSMIT.....................................................................218
Figure 7-12. Master TRANSMIT with Repeated START after Master RECEIVE.....................................................................218
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Figure 7-13. Slave Command Sequence.................................................................................................................................219
Figure 7-14. I2CMSA Register.................................................................................................................................................222
Figure 7-15. I2CMCS Register................................................................................................................................................ 223
Figure 7-16. I2CMDR Register................................................................................................................................................ 228
Figure 7-17. I2CMTPR Register.............................................................................................................................................. 229
Figure 7-18. I2CMIMR Register...............................................................................................................................................230
Figure 7-19. I2CMRIS Register............................................................................................................................................... 232
Figure 7-20. I2CMMIS Register............................................................................................................................................... 235
Figure 7-21. I2CMICR Register............................................................................................................................................... 238
Figure 7-22. I2CMCR Register................................................................................................................................................ 240
Figure 7-23. I2CMCLKOCNT Register.................................................................................................................................... 241
Figure 7-24. I2CMBMON Register...........................................................................................................................................242
Figure 7-25. I2CMBLEN Register............................................................................................................................................ 243
Figure 7-26. I2CMBCNT Register............................................................................................................................................244
Figure 7-27. I2CSOAR Register.............................................................................................................................................. 245
Figure 7-28. I2CSCSR Register.............................................................................................................................................. 246
Figure 7-29. I2CSDR Register.................................................................................................................................................248
Figure 7-30. I2CSIMR Register............................................................................................................................................... 249
Figure 7-31. I2CSRIS Register................................................................................................................................................ 251
Figure 7-32. I2CSMIS Register................................................................................................................................................253
Figure 7-33. I2CSICR Register................................................................................................................................................255
Figure 7-34. I2CSOAR2 Register............................................................................................................................................ 257
Figure 7-35. I2CSACKCTL Register........................................................................................................................................258
Figure 7-36. I2CFIFODATA Register....................................................................................................................................... 259
Figure 7-37. I2CFIFOCTL Register......................................................................................................................................... 260
Figure 7-38. I2CFIFOSTATUS Register...................................................................................................................................262
Figure 7-39. I2CPP Register....................................................................................................................................................264
Figure 7-40. I2CPC Register................................................................................................................................................... 265
Figure 8-1. SPI Block Diagram................................................................................................................................................ 268
Figure 8-2. SPI Full-Duplex Transmission (Example)..............................................................................................................270
Figure 8-3. Phase and Polarity Combinations......................................................................................................................... 271
Figure 8-4. Full-Duplex Single Transfer Format With PHA = 0................................................................................................272
Figure 8-5. Full-Duplex Single Transfer Format With PHA = 1................................................................................................273
Figure 8-6. Contiguous Transfers With SPIEN Kept Active (Two Data Pins Interface Mode)................................................. 275
Figure 8-7. Transmit/Receive Mode With No FIFO Used........................................................................................................ 277
Figure 8-8. Transmit/Receive Mode With Only Receive FIFO Enabled...................................................................................277
Figure 8-11. Buffer Almost Full Level (AFL).............................................................................................................................279
Figure 8-12. Buffer Almost Empty Level (AEL)........................................................................................................................279
Figure 8-13. 3-Pin Mode System Overview............................................................................................................................. 280
Figure 8-14. Flow Chart – Module Initialization....................................................................................................................... 286
Figure 8-15. Flow Chart – Common Transfer Sequence.........................................................................................................287
Figure 8-16. Flow Chart – Transmit and Receive (Master and Slave).....................................................................................288
Figure 8-17. Flow Chart – FIFO Mode Common Sequence (Master)......................................................................................289
Figure 8-20. SPI_SYSCONFIG Register................................................................................................................................. 293
Figure 8-21. SPI_SYSSTATUS Register................................................................................................................................. 294
Figure 8-22. SPI_IRQSTATUS Register.................................................................................................................................. 295
Figure 8-23. SPI_IRQENABLE Register..................................................................................................................................297
Figure 8-24. SPI_MODULCTRL Register................................................................................................................................299
Figure 8-25. SPI_CHCONF Register.......................................................................................................................................300
Figure 8-26. SPI_CHSTAT Register........................................................................................................................................ 303
Figure 8-27. SPI_CHCTRL Register........................................................................................................................................305
Figure 8-28. SPI_TX Register..................................................................................................................................................306
Figure 8-29. SPI_RX Register................................................................................................................................................. 307
Figure 8-30. SPI_XFERLEVEL Register................................................................................................................................. 308
Figure 9-1. GPTM Module Block Diagram...............................................................................................................................310
Figure 9-2. Input Edge-Count Mode Example, Counting Down...............................................................................................315
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Figure 9-3. 16-Bit Input Edge-Time Mode Example.................................................................................................................316
Figure 9-4. 16-Bit PWM Mode Example.................................................................................................................................. 317
Figure 9-5. GPTMCFG Register.............................................................................................................................................. 322
Figure 9-6. GPTMTAMR Register............................................................................................................................................323
Figure 9-7. GPTMTBMR Register............................................................................................................................................325
Figure 9-8. GPTMCTL Register...............................................................................................................................................327
Figure 9-9. GPTMIMR Register............................................................................................................................................... 329
Figure 9-10. GPTMRIS Register..............................................................................................................................................331
Figure 9-11. GPTMMIS Register..............................................................................................................................................333
Figure 9-13. GPTMTAILR Register..........................................................................................................................................337
Figure 9-14. GPTMTBILR Register......................................................................................................................................... 338
Figure 9-16. GPTMTBMATCHR Register................................................................................................................................340
Figure 9-17. GPTMTAPR Register.......................................................................................................................................... 341
Figure 9-18. GPTMTBPR Register.......................................................................................................................................... 342
Figure 9-19. GPTMTAPMR Register....................................................................................................................................... 343
Figure 9-20. GPTMTBPMR Register....................................................................................................................................... 344
Figure 9-22. GPTMTBR Register............................................................................................................................................ 346
Figure 9-23. GPTMTAV Register............................................................................................................................................. 347
Figure 9-24. GPTMTBV Register.............................................................................................................................................348
Figure 9-25. GPTMDMAEV Register.......................................................................................................................................349
Figure 10-1. WDT Module Block Diagram............................................................................................................................... 352
Figure 10-2. WDTLOAD Register............................................................................................................................................ 355
Figure 10-3. WDTVALUE Register.......................................................................................................................................... 356
Figure 10-5. WDTICR Register................................................................................................................................................358
Figure 10-6. WDTRIS Register................................................................................................................................................359
Figure 10-7. WDTTEST Register.............................................................................................................................................360
Figure 10-8. WDTLOCK Register............................................................................................................................................ 361
Figure 10-9. Watchdog Flow Chart..........................................................................................................................................363
Figure 10-10. System Watchdog Recovery Sequence............................................................................................................364
Figure 11-2. MMCHS_CSRE Register.....................................................................................................................................379
Figure 11-3. MMCHS_CON Register.......................................................................................................................................380
Figure 11-4. MMCHS_BLK Register........................................................................................................................................382
Figure 11-5. MMCHS_ARG Register.......................................................................................................................................384
Figure 11-6. MMCHS_CMD Register.......................................................................................................................................385
Figure 11-7. MMCHS_RSP10 Register................................................................................................................................... 388
Figure 11-8. MMCHS_RSP32 Register................................................................................................................................... 389
Figure 11-9. MMCHS_RSP54 Register................................................................................................................................... 390
Figure 11-10. MMCHS_RSP76 Register................................................................................................................................. 391
Figure 11-11. MMCHS_DATA Register.................................................................................................................................... 392
Figure 11-12. MMCHS_PSTATE Register............................................................................................................................... 393
Figure 11-13. MMCHS_HCTL Register................................................................................................................................... 395
Figure 11-15. MMCHS_STAT Register....................................................................................................................................399
Figure 11-16. MMCHS_IE Register......................................................................................................................................... 403
Figure 11-17. MMCHS_ISE Register.......................................................................................................................................405
Figure 12-1. I2S Protocol.........................................................................................................................................................408
Figure 12-2. I2S Module.......................................................................................................................................................... 409
Figure 12-4. AFIFOREV Register............................................................................................................................................ 423
Figure 12-5. WFIFOCTL Register............................................................................................................................................424
Figure 12-6. PDIR Register..................................................................................................................................................... 426
Figure 12-7. RFIFOCTL Register............................................................................................................................................ 428
Figure 12-8. RFIFOSTS Register............................................................................................................................................ 430
Figure 12-9. GBLCTL Register................................................................................................................................................ 431
Figure 12-10. RGBLCTL Register........................................................................................................................................... 433
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Figure 12-11. RMASK Register................................................................................................................................................435
Figure 12-12. RFMT Register.................................................................................................................................................. 436
Figure 12-13. AFSRCTL Register............................................................................................................................................438
Figure 12-14. RTDM Register..................................................................................................................................................440
Figure 12-15. RINTCTL Register.............................................................................................................................................441
Figure 12-16. RSTAT Register.................................................................................................................................................443
Figure 12-17. RSLOT Register................................................................................................................................................ 445
Figure 12-18. REVTCTL Register............................................................................................................................................446
Figure 12-19. XGBLCTL Register............................................................................................................................................447
Figure 12-20. XMASK Register............................................................................................................................................... 449
Figure 12-21. XFMT Register.................................................................................................................................................. 450
Figure 12-22. AFSXCTL Register............................................................................................................................................452
Figure 12-23. ACLKXCTL Register......................................................................................................................................... 454
Figure 12-24. AHCLKXCTL Register.......................................................................................................................................456
Figure 12-25. XTDM Register..................................................................................................................................................457
Figure 12-27. XSTAT Register................................................................................................................................................. 460
Figure 12-28. XSLOT Register................................................................................................................................................ 462
Figure 12-29. XEVTCTL Register............................................................................................................................................463
Figure 12-30. SRCTLn Registers............................................................................................................................................ 464
Figure 12-31. XBUFn Registers...............................................................................................................................................466
Figure 12-32. RBUFn Registers.............................................................................................................................................. 467
Figure 13-1. Architecture of the ADC Module in CC32xx........................................................................................................ 470
Figure 13-2. Operation of the ADC..........................................................................................................................................471
Figure 13-4. ADC_CH0_IRQ_EN Register..............................................................................................................................474
Figure 13-5. ADC_CH2_IRQ_EN Register..............................................................................................................................475
Figure 13-6. ADC_CH4_IRQ_EN Register..............................................................................................................................476
Figure 13-7. ADC_CH6_IRQ_EN Register..............................................................................................................................477
Figure 13-8. ADC_CH0_IRQ_STATUS Register..................................................................................................................... 478
Figure 13-9. ADC_CH2_IRQ_STATUS Register..................................................................................................................... 479
Figure 13-10. ADC_CH4_IRQ_STATUS Register................................................................................................................... 480
Figure 13-11. ADC_CH6_IRQ_STATUS Register................................................................................................................... 481
Figure 13-12. ADC_DMA_MODE_EN Register.......................................................................................................................482
Figure 13-13. ADC_TIMER_CONFIGURATION Register....................................................................................................... 483
Figure 13-14. ADC_TIMER_CURRENT_COUNT Register.....................................................................................................483
Figure 13-15. CHANNEL0FIFODATA Register........................................................................................................................484
Figure 13-16. CHANNEL2FIFODATA Register........................................................................................................................484
Figure 13-17. CHANNEL4FIFODATA Register........................................................................................................................485
Figure 13-18. CHANNEL6FIFODATA Register........................................................................................................................485
Figure 13-21. ADC_CH4_FIFO_LVL Register.........................................................................................................................488
Figure 13-22. ADC_CH6_FIFO_LVL Register.........................................................................................................................489
Figure 13-23. ADC_CH_ENABLE Register............................................................................................................................. 490
Figure 14-1. Camera Module Interfaces.................................................................................................................................. 500
Figure 14-2. Synchronization Signals and Frame Timing........................................................................................................501
Figure 14-3. Synchronization Signals and Data Timing...........................................................................................................501
Figure 14-4. Different Scenarios of CAM_P_HS and CAM_P_VS.......................................................................................... 502
Figure 14-5. CAM_P_HS Toggles Between Pixels in Decimation........................................................................................... 502
Figure 14-6. Parallel Camera Interface State Machine............................................................................................................502
Figure 14-7. FIFO Image Data Format.................................................................................................................................... 503
Figure 14-8. Assertion and Deassertion of the DMA Request Signal......................................................................................505
Figure 14-9. CC_SYSCONFIG Register..................................................................................................................................508
Figure 14-10. CC_SYSSTATUS Register................................................................................................................................ 509
Figure 14-11. CC_IRQSTATUS Register.................................................................................................................................510
Figure 14-12. CC_IRQENABLE Register................................................................................................................................ 513
Figure 14-13. CC_CTRL Register........................................................................................................................................... 515
Figure 14-14. CC_CTRL_DMA Register................................................................................................................................. 518
Figure 14-15. CC_CTRL_XCLK Register................................................................................................................................ 519
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Figure 14-16. CC_FIFODATA Register....................................................................................................................................520
Figure 15-1. Power Management Unit Configuration.............................................................................................................. 531
Figure 15-2. Sleep Modes....................................................................................................................................................... 533
Figure 15-3. Power Management Control Architecture in CC32xx..........................................................................................535
Figure 15-4. CAMCLKCFG Register....................................................................................................................................... 545
Figure 15-5. CAMCLKEN Register.......................................................................................................................................... 546
Figure 15-6. CAMSWRST Register......................................................................................................................................... 547
Figure 15-7. MCASPCLKEN Register..................................................................................................................................... 548
Figure 15-8. MCASPSWRST Register.................................................................................................................................... 549
Figure 15-9. SDIOMCLKCFG Register....................................................................................................................................550
Figure 15-11. SDIOMSWRST Register....................................................................................................................................552
Figure 15-12. APSPICLKCFG Register...................................................................................................................................553
Figure 15-13. APSPICLKEN Register..................................................................................................................................... 554
Figure 15-14. APSPISWRST Register.................................................................................................................................... 555
Figure 15-15. DMACLKEN Register........................................................................................................................................ 556
Figure 15-16. DMASWRST Register....................................................................................................................................... 557
Figure 15-17. GPIO0CLKEN Register..................................................................................................................................... 558
Figure 15-19. GPIO1CLKEN Register..................................................................................................................................... 560
Figure 15-21. GPIO2CLKEN Register..................................................................................................................................... 562
Figure 15-22. GPIO2SWRST Register.................................................................................................................................... 563
Figure 15-23. GPIO3CLKEN Register..................................................................................................................................... 564
Figure 15-24. GPIO3SWRST Register.................................................................................................................................... 565
Figure 15-25. GPIO4CLKEN Register..................................................................................................................................... 566
Figure 15-26. GPIO4SWRST Register.................................................................................................................................... 567
Figure 15-27. WDTCLKEN Register........................................................................................................................................568
Figure 15-28. WDTSWRST Register.......................................................................................................................................569
Figure 15-29. UART0CLKEN Register.................................................................................................................................... 570
Figure 15-30. UART0SWRST Register................................................................................................................................... 571
Figure 15-31. UART1CLKEN Register.................................................................................................................................... 572
Figure 15-32. UART1SWRST Register................................................................................................................................... 573
Figure 15-33. GPT0CLKCFG Register.................................................................................................................................... 574
Figure 15-34. GPT0SWRST Register......................................................................................................................................575
Figure 15-35. GPT1CLKEN Register.......................................................................................................................................576
Figure 15-36. GPT1SWRST Register......................................................................................................................................577
Figure 15-37. GPT2CLKEN Register.......................................................................................................................................578
Figure 15-38. GPT2SWRST Register......................................................................................................................................579
Figure 15-39. GPT3CLKEN Register.......................................................................................................................................580
Figure 15-40. GPT3SWRST Register......................................................................................................................................581
Figure 15-41. MCASPCLKCFG0 Register...............................................................................................................................582
Figure 15-42. MCASPCLKCFG1 Register...............................................................................................................................583
Figure 15-43. I2CLCKEN Register.......................................................................................................................................... 584
Figure 15-44. I2CSWRST Register......................................................................................................................................... 585
Figure 15-45. LPDSREQ Register...........................................................................................................................................586
Figure 15-46. TURBOREQ Register........................................................................................................................................587
Figure 15-47. DSLPWAKECFG Register.................................................................................................................................588
Figure 15-48. DSLPTIMRCFG Register.................................................................................................................................. 589
Figure 15-49. SLPWAKEEN Register......................................................................................................................................590
Figure 15-50. SLPTMRCFG Register......................................................................................................................................591
Figure 15-51. WAKENWP Register......................................................................................................................................... 592
Figure 15-52. RCM_IS Register.............................................................................................................................................. 593
Figure 15-53. RCM_IEN Register............................................................................................................................................594
Figure 16-1. Board Configuration to Use Pins 45 and 52........................................................................................................ 599
Figure 16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals........................................................................... 600
Figure 16-3. I/O Pad Data and Control Path Architecture in CC32xx......................................................................................620
Figure 16-4. Wake on Pad for Hibernate Mode....................................................................................................................... 625
Figure 17-1. AES Block Diagram.............................................................................................................................................629
Figure 17-2. AES - ECB Feedback Mode................................................................................................................................632
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Figure 17-3. AES - CBC Feedback Mode................................................................................................................................633
Figure 17-4. AES Encryption With CTR/ICM Mode................................................................................................................. 634
Figure 17-5. AES - CFB Feedback Mode................................................................................................................................ 635
Figure 17-6. AES - F8 Mode....................................................................................................................................................636
Figure 17-7. AES - XTS Operation.......................................................................................................................................... 637
Figure 17-8. AES - F9 Operation.............................................................................................................................................638
Figure 17-9. AES - CBC-MAC Authentication Mode............................................................................................................... 639
Figure 17-10. AES - GCM Operation.......................................................................................................................................640
Figure 17-11. AES - CCM Operation....................................................................................................................................... 641
Figure 17-12. AES Polling Mode............................................................................................................................................. 645
Figure 17-13. AES Interrupt Service........................................................................................................................................647
Figure 17-14. AES_KEY2_6 Register......................................................................................................................................650
Figure 17-15. AES_KEY2_7 Register......................................................................................................................................650
Figure 17-16. AES_KEY2_4 Register......................................................................................................................................651
Figure 17-17. AES_KEY2_5 Register......................................................................................................................................651
Figure 17-18. AES_KEY2_2 Register......................................................................................................................................652
Figure 17-19. AES_KEY2_3 Register......................................................................................................................................652
Figure 17-20. AES_KEY2_0 Register......................................................................................................................................653
Figure 17-21. AES_KEY2_1 Register......................................................................................................................................653
Figure 17-22. AES_KEY1_6 Register......................................................................................................................................654
Figure 17-23. AES_KEY1_7 Register......................................................................................................................................654
Figure 17-24. AES_KEY1_4 Register......................................................................................................................................655
Figure 17-25. AES_KEY1_5 Register......................................................................................................................................655
Figure 17-26. AES_KEY1_2 Register......................................................................................................................................656
Figure 17-27. AES_KEY1_3 Register......................................................................................................................................656
Figure 17-28. AES_KEY1_0 Register......................................................................................................................................657
Figure 17-29. AES_KEY1_1 Register......................................................................................................................................657
Figure 17-30. AES_IV_IN_0 Register......................................................................................................................................658
Figure 17-31. AES_IV_IN_1 Register......................................................................................................................................658
Figure 17-32. AES_IV_IN_2 Register......................................................................................................................................659
Figure 17-33. AES_IV_IN_3 Register......................................................................................................................................659
Figure 17-34. AES_CTRL Register......................................................................................................................................... 660
Figure 17-35. AES_C_LENGTH_0 Register............................................................................................................................663
Figure 17-36. AES_C_LENGTH_1 Register............................................................................................................................664
Figure 17-37. AES_AUTH_LENGTH Register........................................................................................................................ 665
Figure 17-38. AES_DATA_IN_0 Register................................................................................................................................ 666
Figure 17-39. AES_DATA_IN_1 Register................................................................................................................................ 666
Figure 17-40. AES_DATA_IN_2 Register................................................................................................................................ 667
Figure 17-41. AES_DATA_IN_3 Register................................................................................................................................ 667
Figure 17-44. AES_TAG_OUT_2 Register..............................................................................................................................669
Figure 17-45. AES_TAG_OUT_3 Register..............................................................................................................................669
Figure 17-46. AES_REVISION Register..................................................................................................................................670
Figure 17-47. AES_SYSCONFIG Register..............................................................................................................................672
Figure 17-48. AES_IRQSTATUS Register...............................................................................................................................673
Figure 17-49. AES_IRQENABLE Register.............................................................................................................................. 674
Figure 17-50. CRYPTOCLKEN Register................................................................................................................................. 675
Figure 17-51. DTHE_AES_IM Register................................................................................................................................... 676
Figure 17-52. DTHE_AES_RIS Register................................................................................................................................. 677
Figure 17-53. DTHE_AES_MIS Register.................................................................................................................................678
Figure 17-54. DTHE_AES_IC Register................................................................................................................................... 679
Figure 18-1. DES Block Diagram.............................................................................................................................................683
Figure 18-2. DES – ECB Feedback Mode...............................................................................................................................685
Figure 18-3. DES3DES – CBC Feedback Mode..................................................................................................................... 685
Figure 18-4. DES3DES – CFB Feedback Mode......................................................................................................................686
Figure 18-5. DES Polling Mode............................................................................................................................................... 688
Figure 18-6. DES Interrupt Service..........................................................................................................................................689
Figure 18-7. DES Context Input Event Service....................................................................................................................... 690
Figure 18-8. DTHE_DES_IM Register.....................................................................................................................................692
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Figure 18-9. DTHE_DES_RIS Register...................................................................................................................................693
Figure 18-10. DTHE_DES_MIS Register................................................................................................................................ 694
Figure 18-11. DTHE_DES_IC Register....................................................................................................................................695
Figure 18-12. DES_KEY3_L Register..................................................................................................................................... 696
Figure 18-13. DES_KEY3_H Register.....................................................................................................................................697
Figure 18-14. DES_KEY2_L Register..................................................................................................................................... 698
Figure 18-15. DES_KEY2_H Register.....................................................................................................................................699
Figure 18-16. DES_KEY1_L Register..................................................................................................................................... 700
Figure 18-17. DES_KEY1_H Register.....................................................................................................................................701
Figure 18-18. DES_IV_L Register........................................................................................................................................... 702
Figure 18-19. DES_IV_H Register...........................................................................................................................................703
Figure 18-20. DES_CTRL Register......................................................................................................................................... 704
Figure 18-22. DES_DATA_L Register......................................................................................................................................706
Figure 18-23. DES_DATA_H Register..................................................................................................................................... 707
Figure 18-24. DES_SYSCONFIG Register............................................................................................................................. 708
Figure 18-25. DES_IRQSTATUS Register...............................................................................................................................709
Figure 19-1. SHA/MD5 Module Block Diagram....................................................................................................................... 712
Figure 19-2. SHA/MD5 Polling Mode.......................................................................................................................................721
Figure 19-3. SHA/MD5 Interrupt Subroutine............................................................................................................................722
Figure 19-5. SHAMD5_ODIGEST_A Register........................................................................................................................ 727
Figure 19-6. SHAMD5_ODIGEST_B Register........................................................................................................................ 728
Figure 19-7. SHAMD5_ODIGEST_C Register........................................................................................................................ 729
Figure 19-8. SHAMD5_ODIGEST_D Register........................................................................................................................ 730
Figure 19-9. SHAMD5_ODIGEST_E Register........................................................................................................................ 731
Figure 19-10. SHAMD5_ODIGEST_F Register.......................................................................................................................732
Figure 19-11. SHAMD5_ODIGEST_G Register...................................................................................................................... 733
Figure 19-12. SHAMD5_ODIGEST_H Register...................................................................................................................... 734
Figure 19-13. SHAMD5_IDIGEST_A Register........................................................................................................................ 736
Figure 19-14. SHAMD5_IDIGEST_B Register........................................................................................................................ 737
Figure 19-15. SHAMD5_IDIGEST_C Register........................................................................................................................ 738
Figure 19-16. SHAMD5_IDIGEST_D Register........................................................................................................................ 739
Figure 19-17. SHAMD5_IDIGEST_E Register........................................................................................................................ 740
Figure 19-18. SHAMD5_IDIGEST_F Register........................................................................................................................ 741
Figure 19-19. SHAMD5_IDIGEST_G Register........................................................................................................................742
Figure 19-20. SHAMD5_IDIGEST_H Register........................................................................................................................ 743
Figure 19-21. SHAMD5_DIGEST_COUNT Register...............................................................................................................744
Figure 19-23. SHAMD5_LENGTH Register............................................................................................................................ 747
Figure 19-24. SHAMD5_DATA0_IN Register.......................................................................................................................... 749
Figure 19-25. SHAMD5_DATA1_IN Register.......................................................................................................................... 750
Figure 19-26. SHAMD5_DATA2_IN Register.......................................................................................................................... 751
Figure 19-27. SHAMD5_DATA3_IN Register.......................................................................................................................... 752
Figure 19-28. SHAMD5_DATA4_IN Register.......................................................................................................................... 753
Figure 19-29. SHAMD5_DATA5_IN Register.......................................................................................................................... 754
Figure 19-30. SHAMD5_DATA6_IN Register.......................................................................................................................... 755
Figure 19-31. SHAMD5_DATA7_IN Register.......................................................................................................................... 756
Figure 19-32. SHAMD5_DATA8_IN Register.......................................................................................................................... 757
Figure 19-33. SHAMD5_DATA9_IN Register.......................................................................................................................... 758
Figure 19-34. SHAMD5_DATA10_IN Register........................................................................................................................ 759
Figure 19-35. SHAMD5_DATA11_IN Register.........................................................................................................................760
Figure 19-36. SHAMD5_DATA12_IN Register........................................................................................................................ 761
Figure 19-37. SHAMD5_DATA13_IN Register........................................................................................................................ 762
Figure 19-38. SHAMD5_DATA14_IN Register........................................................................................................................ 763
Figure 19-39. SHAMD5_DATA15_IN Register........................................................................................................................ 764
Figure 19-40. SHAMD5_SYSCONFIG Register......................................................................................................................765
Figure 19-41. SHAMD5_IRQSTATUS Register....................................................................................................................... 766
Figure 19-42. SHAMD5_IRQENABLE Register...................................................................................................................... 767
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Figure 19-43. DTHE_SHA_IM Register...................................................................................................................................768
Figure 19-44. DTHE_SHA_RIS Register.................................................................................................................................769
Figure 19-45. DTHE_SHA_MIS Register................................................................................................................................ 770
Figure 19-46. DTHE_SHA_IC Register................................................................................................................................... 771
Figure 20-1. CRCCTRL Register.............................................................................................................................................778
Figure 20-2. CRCSEED Register............................................................................................................................................ 780
Figure 20-3. CRCDIN Register................................................................................................................................................ 781
Figure 20-4. CRCRSLTPP Register.........................................................................................................................................782
Figure 21-1. FMA Register...................................................................................................................................................... 787
Figure 21-2. FMD Register...................................................................................................................................................... 788
Figure 21-3. FMC Register...................................................................................................................................................... 789
Figure 21-4. FCRIS Register................................................................................................................................................... 791
Figure 21-5. FCIM Register..................................................................................................................................................... 793
Figure 21-6. FCMISC Register................................................................................................................................................ 795
Figure 21-7. FMC2 Register.................................................................................................................................................... 797
Figure 21-8. FWBVAL Register................................................................................................................................................798
Figure 21-9. FWBn Register.................................................................................................................................................... 799
Figure 21-10. CC323xSF Boot Flow........................................................................................................................................800
Figure 21-11. Flash Memory Partition......................................................................................................................................801
Figure 21-12. User Application Image Binary Structure on Serial Flash................................................................................. 802
Figure 21-13. On-Chip Flash Programming and Update......................................................................................................... 804
Figure 21-14. Flash Debug Image Layout............................................................................................................................... 805
Figure 23-2. DMA_IMS Register..............................................................................................................................................812
Figure 23-4. DMA_ICR Register..............................................................................................................................................816
Figure 23-5. DMA_MIS Register..............................................................................................................................................818
Figure 23-6. DMA_RIS Register.............................................................................................................................................. 820
Figure 23-7. GPTTRIGSEL Register....................................................................................................................................... 822
List of Tables
Table 1-1. Register Bit Accessibility and Initial Condition.......................................................................................................... 25
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use.................................................................................45
Table 2-2. Processor Register Map........................................................................................................................................... 46
Table 2-3. PSR Register Combinations..................................................................................................................................... 48
Table 2-4. Memory Map............................................................................................................................................................. 50
Table 2-5. SRAM Memory Bit-Banding Regions........................................................................................................................51
Table 2-6. Exception Types........................................................................................................................................................55
Table 2-7. CC32xx Application Processor Interrupts................................................................................................................. 55
Table 2-8. Faults........................................................................................................................................................................ 59
Table 2-9. Fault Status and Fault Address Registers................................................................................................................ 60
Table 2-10. Cortex®-M4 Instruction Summary...........................................................................................................................64
Table 3-1. Core Peripheral Register Regions............................................................................................................................ 70
Table 3-2. Peripherals Register Map......................................................................................................................................... 72
Table 3-3. Cortex Registers....................................................................................................................................................... 75
Table 3-4. ACTLR Register Field Descriptions.......................................................................................................................... 76
Table 3-5. STCTRL Register Field Descriptions........................................................................................................................78
Table 3-6. STRELOAD Register Field Descriptions...................................................................................................................80
Table 3-7. STCURRENT Register Field Descriptions................................................................................................................81
Table 3-8. EN_0 to EN_6 Register Field Descriptions...............................................................................................................82
Table 3-9. DIS_0 to DIS_6 Register Field Descriptions.............................................................................................................83
Table 3-10. PEND_0 to PEND_6 Register Field Descriptions...................................................................................................84
Table 3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions.........................................................................................85
Table 3-12. ACTIVE_0 to ACTIVE_6 Register Field Descriptions.............................................................................................86
Table 3-13. PRI_0 to PRI_49 Register Field Descriptions.........................................................................................................87
Table 3-14. CPUID Register Field Descriptions.........................................................................................................................88
Table 3-15. INTCTRL Register Field Descriptions.....................................................................................................................89
Table 3-16. VTABLE Register Field Descriptions.......................................................................................................................92
Table 3-17. APINT Register Field Descriptions......................................................................................................................... 93
Table 3-18. SYSCTRL Register Field Descriptions................................................................................................................... 95
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Table 3-19. CFGCTRL Register Field Descriptions...................................................................................................................96
Table 3-20. SYSPRI1 Register Field Descriptions.....................................................................................................................98
Table 3-21. SYSPRI2 Register Field Descriptions.....................................................................................................................99
Table 3-22. SYSPRI3 Register Field Descriptions...................................................................................................................100
Table 3-23. SYSHNDCTRL Register Field Descriptions..........................................................................................................101
Table 3-24. FAULTSTAT Register Field Descriptions.............................................................................................................. 105
Table 3-25. HFAULTSTAT Register Field Descriptions............................................................................................................109
Table 3-26. FAULTDDR Register Field Descriptions................................................................................................................110
Table 3-27. SWTRIG Register Field Descriptions.................................................................................................................... 111
Table 4-1. DMA Channel Assignment...................................................................................................................................... 115
Table 4-2. Channel Control Memory........................................................................................................................................ 116
Table 4-3. Individual Control Structure.....................................................................................................................................117
Table 4-4. 8-Bit Data Peripheral Configuration........................................................................................................................ 122
Table 4-5. µDMA Register Map................................................................................................................................................123
Table 4-6. DM Registers.......................................................................................................................................................... 124
Table 4-7. DMA_SRCENDP Register Field Descriptions........................................................................................................ 125
Table 4-8. DMA_DSTENDP Register Field Descriptions.........................................................................................................125
Table 4-9. DMA_CHCTL Register Field Descriptions..............................................................................................................126
Table 4-10. DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers..............................................................................129
Table 4-11. DMA_STAT Register Field Descriptions................................................................................................................130
Table 4-12. DMA_CFG Register Field Descriptions................................................................................................................ 131
Table 4-13. DMA_CTLBASE Register Field Descriptions........................................................................................................132
Table 4-14. DMA_ALTBASE Register Field Descriptions........................................................................................................ 133
Table 4-15. DMA_WAITSTAT Register Field Descriptions.......................................................................................................134
Table 4-16. DMA_SWREQ Register Field Descriptions.......................................................................................................... 135
Table 4-17. DMA_USEBURSTSET Register Field Descriptions............................................................................................. 136
Table 4-18. DMA_USEBURSTCLR Register Field Descriptions............................................................................................. 137
Table 4-19. DMA_REQMASKSET Register Field Descriptions...............................................................................................138
Table 4-20. DMA_REQMASKCLR Register Field Descriptions...............................................................................................139
Table 4-21. DMA_ENASET Register Field Descriptions..........................................................................................................140
Table 4-22. DMA_ENACLR Register Field Descriptions......................................................................................................... 141
Table 4-23. DMA_ALTSET Register Field Descriptions...........................................................................................................142
Table 4-24. DMA_ALTCLR Register Field Descriptions...........................................................................................................143
Table 4-25. DMA_PRIOSET Register Field Descriptions........................................................................................................ 144
Table 4-26. DMA_PRIOCLR Register Field Descriptions........................................................................................................145
Table 4-27. DMA_ERRCLR Register Field Descriptions......................................................................................................... 146
Table 4-28. DMA_CHASGN Register Field Descriptions.........................................................................................................147
Table 4-29. DMA_CHMAP0 Register Field Descriptions.........................................................................................................148
Table 4-30. DMA_CHMAP1 Register Field Descriptions.........................................................................................................149
Table 4-31. DMA_CHMAP2 Register Field Descriptions.........................................................................................................150
Table 4-32. DMA_CHMAP3 Register Field Descriptions.........................................................................................................151
Table 4-33. DMA_PV Register Field Descriptions................................................................................................................... 152
Table 5-1. GPIO Pad Configuration Examples........................................................................................................................ 157
Table 5-2. GPIO Interrupt Configuration Examples................................................................................................................. 157
Table 5-3. GPIO Registers....................................................................................................................................................... 158
Table 5-4. GPIODATA Register Field Descriptions..................................................................................................................159
Table 5-5. GPIODIR Register Field Descriptions.....................................................................................................................160
Table 5-6. GPIOIS Register Field Descriptions........................................................................................................................161
Table 5-7. GPIOIBE Register Field Descriptions..................................................................................................................... 162
Table 5-8. GPIOIEV Register Field Descriptions..................................................................................................................... 163
Table 5-9. GPIOIM Register Field Descriptions....................................................................................................................... 164
Table 5-10. GPIORIS Register Field Descriptions...................................................................................................................165
Table 5-11. GPIOMIS Register Field Descriptions...................................................................................................................166
Table 5-12. GPIOICR Register Field Descriptions...................................................................................................................167
Table 5-13. GPIO_TRIG_EN Register Field Descriptions....................................................................................................... 168
Table 5-14. GPIO Mapping...................................................................................................................................................... 168
Table 6-1. Flow Control Mode..................................................................................................................................................175
Table 6-2. UART Registers...................................................................................................................................................... 179
Table 6-3. UARTDR Register Field Descriptions..................................................................................................................... 180
Table 6-4. UARTRSR_UARTECR Register Field Descriptions............................................................................................... 182
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Table 6-5. UARTFR Register Field Descriptions......................................................................................................................184
Table 6-6. UARTIBRD Register Field Descriptions..................................................................................................................186
Table 6-7. UARTFBRD Register Field Descriptions.................................................................................................................187
Table 6-8. UARTLCRH Register Field Descriptions.................................................................................................................188
Table 6-9. UARTCTL Register Field Descriptions....................................................................................................................190
Table 6-10. UARTIFLS Register Field Descriptions.................................................................................................................192
Table 6-11. UARTIM Register Field Descriptions.....................................................................................................................193
Table 6-12. UARTRIS Register Field Descriptions.................................................................................................................. 195
Table 6-13. UARTMIS Register Field Descriptions.................................................................................................................. 197
Table 6-14. UARTICR Register Field Descriptions.................................................................................................................. 200
Table 6-15. UARTDMACTL Register Field Descriptions..........................................................................................................202
Table 7-1. I2C Signals (64QFN)...............................................................................................................................................205
Table 7-2. Timer Periods..........................................................................................................................................................210
Table 7-3. I2C Registers.......................................................................................................................................................... 221
Table 7-4. I2CMSA Register Field Descriptions.......................................................................................................................222
Table 7-5. I2CMCS Register Field Descriptions...................................................................................................................... 223
Table 7-6. Write Field Decoding for I2CMCS[6:0].................................................................................................................... 225
Table 7-7. I2CMDR Register Field Descriptions...................................................................................................................... 228
Table 7-8. I2CMTPR Register Field Descriptions.................................................................................................................... 229
Table 7-9. I2CMIMR Register Field Descriptions.....................................................................................................................230
Table 7-10. I2CMRIS Register Field Descriptions................................................................................................................... 232
Table 7-11. I2CMMIS Register Field Descriptions................................................................................................................... 235
Table 7-12. I2CMICR Register Field Descriptions................................................................................................................... 238
Table 7-13. I2CMCR Register Field Descriptions.................................................................................................................... 240
Table 7-14. I2CMCLKOCNT Register Field Descriptions........................................................................................................ 241
Table 7-15. I2CMBMON Register Field Descriptions...............................................................................................................242
Table 7-16. I2CMBLEN Register Field Descriptions................................................................................................................243
Table 7-17. I2CMBCNT Register Field Descriptions................................................................................................................244
Table 7-18. I2CSOAR Register Field Descriptions.................................................................................................................. 245
Table 7-19. I2CSCSR Register Field Descriptions.................................................................................................................. 246
Table 7-20. I2CSDR Register Field Descriptions.....................................................................................................................248
Table 7-21. I2CSIMR Register Field Descriptions................................................................................................................... 249
Table 7-22. I2CSRIS Register Field Descriptions....................................................................................................................251
Table 7-23. I2CSMIS Register Field Descriptions....................................................................................................................253
Table 7-24. I2CSICR Register Field Descriptions....................................................................................................................255
Table 7-25. I2CSOAR2 Register Field Descriptions................................................................................................................ 257
Table 7-26. I2CSACKCTL Register Field Descriptions............................................................................................................258
Table 7-27. I2CFIFODATA Register Field Descriptions........................................................................................................... 259
Table 7-28. I2CFIFOCTL Register Field Descriptions............................................................................................................. 260
Table 7-29. I2CFIFOSTATUS Register Field Descriptions.......................................................................................................262
Table 7-30. I2CPP Register Field Descriptions........................................................................................................................264
Table 7-31. I2CPC Register Field Descriptions....................................................................................................................... 265
Table 8-1. SPI.......................................................................................................................................................................... 269
Table 8-2. Phase and Polarity Combinations...........................................................................................................................271
Table 8-3. Clock Ratio Granularity...........................................................................................................................................275
Table 8-4. Granularity Examples..............................................................................................................................................276
Table 8-5. SPI Word Length WL.............................................................................................................................................. 276
Table 8-6. SPI Registers.......................................................................................................................................................... 292
Table 8-7. SPI_SYSCONFIG Register Field Descriptions.......................................................................................................293
Table 8-8. SPI_SYSSTATUS Register Field Descriptions....................................................................................................... 294
Table 8-9. SPI_IRQSTATUS Register Field Descriptions........................................................................................................ 295
Table 8-10. SPI_IRQENABLE Register Field Descriptions......................................................................................................297
Table 8-11. SPI_MODULCTRL Register Field Descriptions.................................................................................................... 299
Table 8-12. SPI_CHCONF Register Field Descriptions...........................................................................................................300
Table 8-13. SPI_CHSTAT Register Field Descriptions............................................................................................................ 303
Table 8-14. SPI_CHCTRL Register Field Descriptions............................................................................................................305
Table 8-15. SPI_TX Register Field Descriptions......................................................................................................................306
Table 8-16. SPI_RX Register Field Descriptions..................................................................................................................... 307
Table 8-17. SPI_XFERLEVEL Register Field Descriptions..................................................................................................... 308
Table 9-1. Available CCP Pins and PWM Outputs/Signals Pins.............................................................................................. 311
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Table 9-2. General-Purpose Timer Capabilities....................................................................................................................... 311
Table 9-4. 16-Bit Timer With Prescaler Configurations............................................................................................................ 313
Table 9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode................................................................ 314
Table 9-7. Counter Values When the Timer is Enabled in PWM Mode....................................................................................316
Table 9-8. Timer Registers.......................................................................................................................................................321
Table 9-9. GPTMCFG Register Field Descriptions.................................................................................................................. 322
Table 9-10. GPTMTAMR Register Field Descriptions..............................................................................................................323
Table 9-11. GPTMTBMR Register Field Descriptions..............................................................................................................325
Table 9-12. GPTMCTL Register Field Descriptions.................................................................................................................327
Table 9-13. GPTMIMR Register Field Descriptions.................................................................................................................329
Table 9-14. GPTMRIS Register Field Descriptions..................................................................................................................331
Table 9-15. GPTMMIS Register Field Descriptions................................................................................................................. 333
Table 9-16. GPTMICR Register Field Descriptions................................................................................................................. 335
Table 9-17. GPTMTAILR Register Field Descriptions..............................................................................................................337
Table 9-18. GPTMTBILR Register Field Descriptions............................................................................................................. 338
Table 9-21. GPTMTAPR Register Field Descriptions.............................................................................................................. 341
Table 9-22. GPTMTBPR Register Field Descriptions..............................................................................................................342
Table 9-23. GPTMTAPMR Register Field Descriptions........................................................................................................... 343
Table 9-24. GPTMTBPMR Register Field Descriptions...........................................................................................................344
Table 9-25. GPTMTAR Register Field Descriptions.................................................................................................................345
Table 9-26. GPTMTBR Register Field Descriptions................................................................................................................ 346
Table 9-27. GPTMTAV Register Field Descriptions................................................................................................................. 347
Table 9-28. GPTMTBV Register Field Descriptions.................................................................................................................348
Table 9-29. GPTMDMAEV Register Field Descriptions...........................................................................................................349
Table 10-1. WATCHDOG Registers.........................................................................................................................................354
Table 10-2. WDTLOAD Register Field Descriptions................................................................................................................355
Table 10-3. WDTVALUE Register Field Descriptions.............................................................................................................. 356
Table 10-4. WDTCTL Register Field Descriptions...................................................................................................................357
Table 10-5. WDTICR Register Field Descriptions....................................................................................................................358
Table 10-6. WDTRIS Register Field Descriptions....................................................................................................................359
Table 10-7. WDTTEST Register Field Descriptions.................................................................................................................360
Table 10-8. WDTLOCK Register Field Descriptions................................................................................................................361
Table 11-1. Card Types............................................................................................................................................................372
Table 11-2. Throughput Data................................................................................................................................................... 373
Table 11-4. SD-HOST Registers..............................................................................................................................................378
Table 11-5. MMCHS_CSRE Register Field Descriptions.........................................................................................................379
Table 11-6. MMCHS_CON Register Field Descriptions...........................................................................................................380
Table 11-8. MMCHS_ARG Register Field Descriptions...........................................................................................................384
Table 11-9. MMCHS_CMD Register Field Descriptions...........................................................................................................385
Table 11-10. MMCHS_RSP10 Register Field Descriptions..................................................................................................... 388
Table 11-11. MMCHS_RSP32 Register Field Descriptions......................................................................................................389
Table 11-12. MMCHS_RSP54 Register Field Descriptions..................................................................................................... 390
Table 11-13. MMCHS_RSP76 Register Field Descriptions..................................................................................................... 391
Table 11-15. MMCHS_PSTATE Register Field Descriptions...................................................................................................393
Table 11-16. MMCHS_HCTL Register Field Descriptions....................................................................................................... 395
Table 11-17. MMCHS_SYSCTL Register Field Descriptions...................................................................................................396
Table 11-18. MMCHS_STAT Register Field Descriptions........................................................................................................399
Table 11-19. MMCHS_IE Register Field Descriptions............................................................................................................. 403
Table 11-20. MMCHS_ISE Register Field Descriptions...........................................................................................................405
Table 12-1. ulIntFlags Parameter.............................................................................................................................................417
Table 12-2. ulStatFlags Parameter.......................................................................................................................................... 418
Table 12-3. I2S Registers Accessed Through Peripheral Configuration Port..........................................................................421
Table 12-4. I2S Registers Accessed Through DMA Port.........................................................................................................422
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Table 12-5. I2S AFIFO Registers Accessed Through Peripheral Configuration Port.............................................................. 422
Table 12-6. AFIFOREV Register Field Descriptions................................................................................................................423
Table 12-7. WFIFOCTL Register Field Descriptions................................................................................................................424
Table 12-8. PDIR Register Field Descriptions......................................................................................................................... 426
Table 12-9. RFIFOCTL Register Field Descriptions................................................................................................................ 428
Table 12-10. RFIFOSTS Register Field Descriptions.............................................................................................................. 430
Table 12-11. GBLCTL Register Field Descriptions.................................................................................................................. 431
Table 12-12. RGBLCTL Register Field Descriptions............................................................................................................... 433
Table 12-13. RMASK Register Field Descriptions................................................................................................................... 435
Table 12-14. RFMT Register Field Descriptions......................................................................................................................436
Table 12-15. AFSRCTL Register Field Descriptions................................................................................................................438
Table 12-16. RTDM Register Field Descriptions......................................................................................................................440
Table 12-17. RINTCTL Register Field Descriptions.................................................................................................................441
Table 12-18. RSTAT Register Field Descriptions.....................................................................................................................443
Table 12-19. RSLOT Register Field Descriptions....................................................................................................................445
Table 12-20. REVTCTL Register Field Descriptions................................................................................................................446
Table 12-21. XGBLCTL Register Field Descriptions................................................................................................................447
Table 12-22. XMASK Register Field Descriptions................................................................................................................... 449
Table 12-23. XFMT Register Field Descriptions...................................................................................................................... 450
Table 12-24. AFSXCTL Register Field Descriptions................................................................................................................452
Table 12-25. ACLKXCTL Register Field Descriptions............................................................................................................. 454
Table 12-26. AHCLKXCTL Register Field Descriptions...........................................................................................................456
Table 12-27. XTDM Register Field Descriptions......................................................................................................................457
Table 12-28. XINTCTL Register Field Descriptions.................................................................................................................458
Table 12-29. XSTAT Register Field Descriptions.....................................................................................................................460
Table 12-30. XSLOT Register Field Descriptions.................................................................................................................... 462
Table 12-31. XEVTCTL Register Field Descriptions................................................................................................................463
Table 12-32. SRCTLn Register Field Descriptions.................................................................................................................. 464
Table 12-33. XBUFn Register Field Descriptions.................................................................................................................... 466
Table 12-34. RBUFn Register Field Descriptions.................................................................................................................... 467
Table 13-1. ADC Registers...................................................................................................................................................... 471
Table 13-2. ADC_MODULE Registers.....................................................................................................................................472
Table 13-3. ADC_CTRL Register Field Descriptions...............................................................................................................473
Table 13-4. ADC_CH0_IRQ_EN Register Field Descriptions..................................................................................................474
Table 13-5. ADC_CH2_IRQ_EN Register Field Descriptions..................................................................................................475
Table 13-6. ADC_CH4_IRQ_EN Register Field Descriptions..................................................................................................476
Table 13-7. ADC_CH6_IRQ_EN Register Field Descriptions..................................................................................................477
Table 13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions......................................................................................... 478
Table 13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions......................................................................................... 479
Table 13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions....................................................................................... 480
Table 13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions....................................................................................... 481
Table 13-12. ADC_DMA_MODE_EN Register Field Descriptions...........................................................................................482
Table 13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions........................................................................... 483
Table 13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions.........................................................................483
Table 13-15. CHANNEL0FIFODATA Register Field Descriptions............................................................................................484
Table 13-16. CHANNEL2FIFODATA Register Field Descriptions............................................................................................484
Table 13-17. CHANNEL4FIFODATA Register Field Descriptions............................................................................................485
Table 13-18. CHANNEL6FIFODATA Register Field Descriptions............................................................................................485
Table 13-19. ADC_CH0_FIFO_LVL Register Field Descriptions.............................................................................................486
Table 13-20. ADC_CH2_FIFO_LVL Register Field Descriptions.............................................................................................487
Table 13-21. ADC_CH4_FIFO_LVL Register Field Descriptions.............................................................................................488
Table 13-22. ADC_CH6_FIFO_LVL Register Field Descriptions.............................................................................................489
Table 13-23. ADC_CH_ENABLE Register Field Descriptions.................................................................................................490
Table 13-24. ulChannel Tags................................................................................................................................................... 491
Table 13-25. ulIntFlags Tags....................................................................................................................................................492
Table 14-1. Image Sensor Interface Signals............................................................................................................................501
Table 14-2. Ratio of the XCLK Frequency Generator..............................................................................................................504
Table 14-3. Camera Registers.................................................................................................................................................507
Table 14-4. CC_SYSCONFIG Register Field Descriptions......................................................................................................508
Table 14-5. CC_SYSSTATUS Register Field Descriptions......................................................................................................509
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Table 14-6. CC_IRQSTATUS Register Field Descriptions.......................................................................................................510
Table 14-7. CC_IRQENABLE Register Field Descriptions...................................................................................................... 513
Table 14-8. CC_CTRL Register Field Descriptions................................................................................................................. 515
Table 14-9. CC_CTRL_DMA Register Field Descriptions....................................................................................................... 518
Table 14-10. CC_CTRL_XCLK Register Field Descriptions....................................................................................................519
Table 15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN)..................534
Table 15-2. Peripheral Macro Table.........................................................................................................................................543
Table 15-3. PRCM Registers................................................................................................................................................... 543
Table 15-4. CAMCLKCFG Register Field Descriptions........................................................................................................... 545
Table 15-5. CAMCLKEN Register Field Descriptions..............................................................................................................546
Table 15-6. CAMSWRST Register Field Descriptions.............................................................................................................547
Table 15-7. MCASPCLKEN Register Field Descriptions......................................................................................................... 548
Table 15-8. MCASPSWRST Register Field Descriptions........................................................................................................ 549
Table 15-9. SDIOMCLKCFG Register Field Descriptions........................................................................................................550
Table 15-10. SDIOMCLKEN Register Field Descriptions........................................................................................................ 551
Table 15-11. SDIOMSWRST Register Field Descriptions........................................................................................................552
Table 15-12. APSPICLKCFG Register Field Descriptions.......................................................................................................553
Table 15-13. APSPICLKEN Register Field Descriptions......................................................................................................... 554
Table 15-14. APSPISWRST Register Field Descriptions........................................................................................................ 555
Table 15-15. DMACLKEN Register Field Descriptions............................................................................................................556
Table 15-16. DMASWRST Register Field Descriptions...........................................................................................................557
Table 15-17. GPIO0CLKEN Register Field Descriptions.........................................................................................................558
Table 15-18. GPIO0SWRST Register Field Descriptions........................................................................................................559
Table 15-19. GPIO1CLKEN Register Field Descriptions.........................................................................................................560
Table 15-20. GPIO1SWRST Register Field Descriptions........................................................................................................561
Table 15-21. GPIO2CLKEN Register Field Descriptions.........................................................................................................562
Table 15-22. GPIO2SWRST Register Field Descriptions........................................................................................................563
Table 15-23. GPIO3CLKEN Register Field Descriptions.........................................................................................................564
Table 15-24. GPIO3SWRST Register Field Descriptions........................................................................................................565
Table 15-25. GPIO4CLKEN Register Field Descriptions.........................................................................................................566
Table 15-26. GPIO4SWRST Register Field Descriptions........................................................................................................567
Table 15-27. WDTCLKEN Register Field Descriptions............................................................................................................568
Table 15-28. WDTSWRST Register Field Descriptions...........................................................................................................569
Table 15-29. UART0CLKEN Register Field Descriptions........................................................................................................ 570
Table 15-30. UART0SWRST Register Field Descriptions....................................................................................................... 571
Table 15-31. UART1CLKEN Register Field Descriptions........................................................................................................ 572
Table 15-32. UART1SWRST Register Field Descriptions....................................................................................................... 573
Table 15-33. GPT0CLKCFG Register Field Descriptions........................................................................................................574
Table 15-34. GPT0SWRST Register Field Descriptions..........................................................................................................575
Table 15-35. GPT1CLKEN Register Field Descriptions...........................................................................................................576
Table 15-36. GPT1SWRST Register Field Descriptions..........................................................................................................577
Table 15-37. GPT2CLKEN Register Field Descriptions...........................................................................................................578
Table 15-38. GPT2SWRST Register Field Descriptions..........................................................................................................579
Table 15-39. GPT3CLKEN Register Field Descriptions...........................................................................................................580
Table 15-40. GPT3SWRST Register Field Descriptions..........................................................................................................581
Table 15-41. MCASPCLKCFG0 Register Field Descriptions...................................................................................................582
Table 15-42. MCASPCLKCFG1 Register Field Descriptions...................................................................................................583
Table 15-43. I2CLCKEN Register Field Descriptions.............................................................................................................. 584
Table 15-44. I2CSWRST Register Field Descriptions............................................................................................................. 585
Table 15-45. LPDSREQ Register Field Descriptions...............................................................................................................586
Table 15-46. TURBOREQ Register Field Descriptions............................................................................................................587
Table 15-47. DSLPWAKECFG Register Field Descriptions.....................................................................................................588
Table 15-48. DSLPTIMRCFG Register Field Descriptions...................................................................................................... 589
Table 15-49. SLPWAKEEN Register Field Descriptions..........................................................................................................590
Table 15-50. SLPTMRCFG Register Field Descriptions..........................................................................................................591
Table 15-51. WAKENWP Register Field Descriptions............................................................................................................. 592
Table 15-52. RCM_IS Register Field Descriptions.................................................................................................................. 593
Table 15-53. RCM_IEN Register Field Descriptions................................................................................................................594
Table 16-1. GPIO Pin Electrical Specifications (25°C) (Except Pins 29, 30, 45, 50, 52, 53)................................................... 597
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Table 16-2. GPIO Pin Electrical Specifications (25°C) For Pins 29, 30, 45, 50, 52, 53........................................................... 597
Table 16-3. Pin Internal Pullup and Pulldown Electrical Specifications (25°C)........................................................................597
Table 16-4. Analog Mux Control Registers and Bits................................................................................................................ 601
Table 16-5. Board-Level Behavior........................................................................................................................................... 602
Table 16-6. GPIO/Pins Available for Application......................................................................................................................603
Table 16-7. Pin Multiplexing.....................................................................................................................................................607
Table 16-8. Pin Groups for Audio Interface (I2S)..................................................................................................................... 617
Table 16-10. Pin Groups for SD-Card Interface....................................................................................................................... 617
Table 16-11. Pad Configuration Registers............................................................................................................................... 618
Table 16-12. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description....................................................... 619
Table 16-13. Recommended Pin Multiplexing Configurations................................................................................................. 621
Table 16-14. Sense-on-Power Configurations.........................................................................................................................626
Table 17-1. Key-Block-Round Combinations...........................................................................................................................631
Table 17-2. Interrupts and Events............................................................................................................................................ 642
Table 17-3. AES Registers.......................................................................................................................................................648
Table 17-4. AES_KEY2_6 Register Field Descriptions............................................................................................................650
Table 17-5. AES_KEY2_7 Register Field Descriptions............................................................................................................650
Table 17-6. AES_KEY2_4 Register Field Descriptions............................................................................................................651
Table 17-7. AES_KEY2_5 Register Field Descriptions............................................................................................................651
Table 17-8. AES_KEY2_2 Register Field Descriptions............................................................................................................652
Table 17-9. AES_KEY2_3 Register Field Descriptions............................................................................................................652
Table 17-10. AES_KEY2_0 Register Field Descriptions..........................................................................................................653
Table 17-11. AES_KEY2_1 Register Field Descriptions..........................................................................................................653
Table 17-12. AES_KEY1_6 Register Field Descriptions..........................................................................................................654
Table 17-13. AES_KEY1_7 Register Field Descriptions..........................................................................................................654
Table 17-14. AES_KEY1_4 Register Field Descriptions..........................................................................................................655
Table 17-15. AES_KEY1_5 Register Field Descriptions..........................................................................................................655
Table 17-16. AES_KEY1_2 Register Field Descriptions..........................................................................................................656
Table 17-17. AES_KEY1_3 Register Field Descriptions..........................................................................................................656
Table 17-18. AES_KEY1_0 Register Field Descriptions..........................................................................................................657
Table 17-19. AES_KEY1_1 Register Field Descriptions..........................................................................................................657
Table 17-20. AES_IV_IN_0 Register Field Descriptions..........................................................................................................658
Table 17-21. AES_IV_IN_1 Register Field Descriptions..........................................................................................................658
Table 17-22. AES_IV_IN_2 Register Field Descriptions..........................................................................................................659
Table 17-23. AES_IV_IN_3 Register Field Descriptions..........................................................................................................659
Table 17-24. AES_CTRL Register Field Descriptions............................................................................................................. 660
Table 17-25. AES_C_LENGTH_0 Register Field Descriptions................................................................................................663
Table 17-26. AES_C_LENGTH_1 Register Field Descriptions................................................................................................664
Table 17-27. AES_AUTH_LENGTH Register Field Descriptions............................................................................................ 665
Table 17-28. AES_DATA_IN_0 Register Field Descriptions.................................................................................................... 666
Table 17-29. AES_DATA_IN_1 Register Field Descriptions.................................................................................................... 666
Table 17-30. AES_DATA_IN_2 Register Field Descriptions.................................................................................................... 667
Table 17-31. AES_DATA_IN_3 Register Field Descriptions.................................................................................................... 667
Table 17-32. AES_TAG_OUT_0 Register Field Descriptions.................................................................................................. 668
Table 17-33. AES_TAG_OUT_1 Register Field Descriptions.................................................................................................. 668
Table 17-34. AES_TAG_OUT_2 Register Field Descriptions.................................................................................................. 669
Table 17-35. AES_TAG_OUT_3 Register Field Descriptions.................................................................................................. 669
Table 17-36. AES_REVISION Register Field Descriptions......................................................................................................670
Table 17-37. AES_SYSCONFIG Register Field Descriptions..................................................................................................672
Table 17-38. AES_IRQSTATUS Register Field Descriptions...................................................................................................673
Table 17-39. AES_IRQENABLE Register Field Descriptions.................................................................................................. 674
Table 17-40. CRYPTOCLKEN Register Field Descriptions..................................................................................................... 675
Table 17-41. DTHE_AES_IM Register Field Descriptions.......................................................................................................676
Table 17-42. DTHE_AES_RIS Register Field Descriptions.....................................................................................................677
Table 17-43. DTHE_AES_MIS Register Field Descriptions.....................................................................................................678
Table 17-44. DTHE_AES_IC Register Field Descriptions....................................................................................................... 679
Table 18-1. Key Repartition..................................................................................................................................................... 682
Table 18-2. DES Global Initialization....................................................................................................................................... 686
Table 18-3. DES Algorithm Type Configuration....................................................................................................................... 686
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Table 18-4. 3DES Algorithm Type Configuration..................................................................................................................... 687
Table 18-5. DES Interrupt Mode.............................................................................................................................................. 689
Table 18-6. DES DMA Mode....................................................................................................................................................689
Table 18-7. DES Register Map................................................................................................................................................ 691
Table 18-8. DTHE_DES_IM Register Field Descriptions.........................................................................................................692
Table 18-9. DTHE_DES_RIS Register Field Descriptions.......................................................................................................693
Table 18-10. DTHE_DES_MIS Register Field Descriptions.................................................................................................... 694
Table 18-11. DTHE_DES_IC Register Field Descriptions........................................................................................................695
Table 18-12. DES_KEY3_L Register Field Descriptions......................................................................................................... 696
Table 18-13. DES_KEY3_H Register Field Descriptions.........................................................................................................697
Table 18-14. DES_KEY2_L Register Field Descriptions......................................................................................................... 698
Table 18-15. DES_KEY2_H Register Field Descriptions.........................................................................................................699
Table 18-16. DES_KEY1_L Register Field Descriptions......................................................................................................... 700
Table 18-17. DES_KEY1_H Register Field Descriptions.........................................................................................................701
Table 18-18. DES_IV_L Register Field Descriptions............................................................................................................... 702
Table 18-19. DES_IV_H Register Field Descriptions...............................................................................................................703
Table 18-20. DES_CTRL Register Field Descriptions............................................................................................................. 704
Table 18-21. DES_LENGTH Register Field Descriptions........................................................................................................705
Table 18-22. DES_DATA_L Register Field Descriptions..........................................................................................................706
Table 18-23. DES_DATA_H Register Field Descriptions.........................................................................................................707
Table 18-24. DES_SYSCONFIG Register Field Descriptions................................................................................................. 708
Table 18-25. DES_IRQSTATUS Register Field Descriptions...................................................................................................709
Table 18-26. DES_IRQENABLE Register Field Descriptions..................................................................................................710
Table 19-1. Interrupts and Events............................................................................................................................................ 713
Table 19-2. SHA/MD5 Module Algorithm Selection................................................................................................................. 714
Table 19-3. Outer Digest Registers..........................................................................................................................................715
Table 19-4. Inner Digest Registers.......................................................................................................................................... 715
Table 19-5. SHA Digest Processed in Three Passes.............................................................................................................. 717
Table 19-6. SHA Digest Processed in One Pass.....................................................................................................................718
Table 19-7. Continuing a Prior HMAC......................................................................................................................................720
Table 19-8. SHA-1 Apply on the Key....................................................................................................................................... 720
Table 19-9. Interrupt Mode.......................................................................................................................................................721
Table 19-10. DMA Mode.......................................................................................................................................................... 721
Table 19-11. SHA-MD5 Registers............................................................................................................................................723
Table 19-12. SHAMD5_ODIGEST_A Register Field Descriptions.......................................................................................... 727
Table 19-13. SHAMD5_ODIGEST_B Register Field Descriptions.......................................................................................... 728
Table 19-14. SHAMD5_ODIGEST_C Register Field Descriptions.......................................................................................... 729
Table 19-15. SHAMD5_ODIGEST_D Register Field Descriptions.......................................................................................... 730
Table 19-16. SHAMD5_ODIGEST_E Register Field Descriptions.......................................................................................... 731
Table 19-17. SHAMD5_ODIGEST_F Register Field Descriptions...........................................................................................732
Table 19-18. SHAMD5_ODIGEST_G Register Field Descriptions..........................................................................................733
Table 19-19. SHAMD5_ODIGEST_H Register Field Descriptions.......................................................................................... 734
Table 19-20. SHAMD5_IDIGEST_A Register Field Descriptions............................................................................................ 736
Table 19-21. SHAMD5_IDIGEST_B Register Field Descriptions............................................................................................ 737
Table 19-22. SHAMD5_IDIGEST_C Register Field Descriptions............................................................................................738
Table 19-23. SHAMD5_IDIGEST_D Register Field Descriptions............................................................................................739
Table 19-24. SHAMD5_IDIGEST_E Register Field Descriptions............................................................................................ 740
Table 19-25. SHAMD5_IDIGEST_F Register Field Descriptions............................................................................................ 741
Table 19-26. SHAMD5_IDIGEST_G Register Field Descriptions............................................................................................742
Table 19-27. SHAMD5_IDIGEST_H Register Field Descriptions............................................................................................743
Table 19-28. SHAMD5_DIGEST_COUNT Register Field Descriptions...................................................................................744
Table 19-29. SHAMD5_MODE Register Field Descriptions.................................................................................................... 745
Table 19-30. SHAMD5_LENGTH Register Field Descriptions................................................................................................ 747
Table 19-31. SHAMD5_DATA0_IN Register Field Descriptions.............................................................................................. 749
Table 19-32. SHAMD5_DATA1_IN Register Field Descriptions.............................................................................................. 750
Table 19-33. SHAMD5_DATA2_IN Register Field Descriptions.............................................................................................. 751
Table 19-34. SHAMD5_DATA3_IN Register Field Descriptions.............................................................................................. 752
Table 19-35. SHAMD5_DATA4_IN Register Field Descriptions.............................................................................................. 753
Table 19-36. SHAMD5_DATA5_IN Register Field Descriptions.............................................................................................. 754
Table 19-37. SHAMD5_DATA6_IN Register Field Descriptions.............................................................................................. 755
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Table 19-38. SHAMD5_DATA7_IN Register Field Descriptions.............................................................................................. 756
Table 19-39. SHAMD5_DATA8_IN Register Field Descriptions.............................................................................................. 757
Table 19-40. SHAMD5_DATA9_IN Register Field Descriptions.............................................................................................. 758
Table 19-41. SHAMD5_DATA10_IN Register Field Descriptions............................................................................................ 759
Table 19-42. SHAMD5_DATA11_IN Register Field Descriptions.............................................................................................760
Table 19-43. SHAMD5_DATA12_IN Register Field Descriptions............................................................................................ 761
Table 19-44. SHAMD5_DATA13_IN Register Field Descriptions............................................................................................ 762
Table 19-45. SHAMD5_DATA14_IN Register Field Descriptions............................................................................................ 763
Table 19-46. SHAMD5_DATA15_IN Register Field Descriptions............................................................................................ 764
Table 19-47. SHAMD5_SYSCONFIG Register Field Descriptions..........................................................................................765
Table 19-48. SHAMD5_IRQSTATUS Register Field Descriptions...........................................................................................766
Table 19-49. SHAMD5_IRQENABLE Register Field Descriptions.......................................................................................... 767
Table 19-50. DTHE_SHA_IM Register Field Descriptions.......................................................................................................768
Table 19-51. DTHE_SHA_RIS Register Field Descriptions.....................................................................................................769
Table 19-52. DTHE_SHA_MIS Register Field Descriptions.................................................................................................... 770
Table 19-53. DTHE_SHA_IC Register Field Descriptions....................................................................................................... 771
Table 20-1. Endian Configuration............................................................................................................................................ 775
Table 20-2. Endian Configuration With Bit Reversal................................................................................................................775
Table 20-3. CRC Registers......................................................................................................................................................777
Table 20-4. CRCCTRL Register Field Descriptions.................................................................................................................778
Table 20-5. CRCSEED Register Field Descriptions................................................................................................................ 780
Table 20-6. CRCDIN Register Field Descriptions....................................................................................................................781
Table 20-7. CRCRSLTPP Register Field Descriptions.............................................................................................................782
Table 21-1. Flash Registers..................................................................................................................................................... 786
Table 21-2. FMA Register Field Descriptions.......................................................................................................................... 787
Table 21-3. FMD Register Field Descriptions.......................................................................................................................... 788
Table 21-4. FMC Register Field Descriptions.......................................................................................................................... 789
Table 21-5. FCRIS Register Field Descriptions....................................................................................................................... 791
Table 21-6. FCIM Register Field Descriptions......................................................................................................................... 793
Table 21-7. FCMISC Register Field Descriptions.................................................................................................................... 795
Table 21-8. FMC2 Register Field Descriptions........................................................................................................................ 797
Table 21-9. FWBVAL Register Field Descriptions....................................................................................................................798
Table 21-10. FWBn Register Field Descriptions......................................................................................................................799
Table A-1. Peripheral Samples................................................................................................................................................ 807
Table 23-1. CC323x Device Miscellaneous Register Summary.............................................................................................. 809
Table 23-2. DMA_IMR Register Field Descriptions................................................................................................................. 810
Table 23-3. DMA_IMS Register Field Descriptions..................................................................................................................812
Table 23-4. DMA_IMC Register Field Descriptions................................................................................................................. 814
Table 23-5. DMA_ICR Register Field Descriptions..................................................................................................................816
Table 23-6. DMA_MIS Register Field Descriptions..................................................................................................................818
Table 23-7. DMA_RIS Register Field Descriptions..................................................................................................................820
Table 23-8. GPTTRIGSEL Register Field Descriptions........................................................................................................... 822
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Preface

Read This First

This technical reference manual describes the modules and peripherals of the CC323x SimpleLink™ Wi-Fi
®
microcontroller (MCU). Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals may be present on all devices. Pin functions, internal signal connections, and operational parameters differ from device to device. The user should consult the device­specific data sheet for these details.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature; it explains the features and functionality of each module, and it also explains how to use them. For each feature, references are given to the documentation for the driver of the corresponding operating systems. This document does not contain performance characteristics of the device or modules, which are gathered in the corresponding device data sheets.

Register Bit Conventions

Table 1-1 lists each register with a key indicating the accessibility of the individual bit, and the initial condition.
Table 1-1. Register Bit Accessibility and Initial Condition
Key Bit Accessibility
rw Read/write
r Read only r0 Read as 0 r1 Read as 1
w Write only w0 Write as 0 w1 Write as 1 (w) No register bit implemented; writing 1 results in a pulse. The register bit is always read as 0. h0 Cleared by hardware h1 Set by hardware
-0, -1 Condition after PUC
-(0), -(1) Condition after POR
-[0], -[1] Condition after BOR
-{0},-{1} Condition after Brownout

Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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Related Documentation

The following related documents about the CC323x device can be accessed at these links from Texas Instruments™: http://www.ti.com/simplelinkwifi and http://www.ti.com/simplelinkwifi-wiki
1. SimpleLink™ Wi-Fi® CC3x3x Networking Subsystem Power Management
2. Cortex-M3/M4F Instruction Set Technical User's Manual
Note
This list of documents was current as of publication date. Check the website for additional documentation, application notes, and white papers.
Additional related documentation follows:
1. Arm® Cortex®-M4 Processor Technical Reference Manual (ARM 100166_0001_00).
2. Cortex-M4 Devices Generic User Guide (ARM DUI 0553A).
3. Armv7-M Architecture Reference Manual (ARM DDI 0403E.b).
4. Bluetooth® Special Interest Group (SIG) Bluetooth Core Specifications.
5. Texas Instruments Bluetooth® low energy (BLE) Wiki.
6. Arm® Debug Interface V5 Architecture Specification (see Arm.com).
7. The Institute of Electrical and Electronic Engineers, Inc., IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a 1993 and Supplement Std. 1149.1b 1994 (see IEEExplore.ieee.org).
8. The Institute of Electrical and Electronic Engineers, Inc., IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture (see IEEExplore.ieee.org).
9. National Institute of Standards and Technology, NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation Methods and Techniques (see NIST.gov).
10.National Institute of Standards and Technology, NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC (see NIST.gov).
11.National Institute of Standards and Technology, FIPS 197, Advanced Encryption Standard (AES) (see
NIST.gov).

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Support Forum TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki
TI Product Information Centers (PIC)
Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
All technical support is channeled through the TI Product Information Centers (PIC). To send an email request, enter your contact information and your request to PIC
request form.
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Trademarks

SimpleLink™, Texas Instruments™, TI E2E™, Internet-on-a chip™, and are trademarks of Texas Instruments. AMBA™ and CoreSight™ are trademarks of Arm Limited. Wi-Fi® and Wi-Fi Direct®, and are registered trademarks of Wi-Fi Alliance. Arm®, Cortex®, Thumb®, and are registered trademarks of Arm Limited. Bluetooth® are registered trademarks of Bluetooth SIG, Inc.. All other trademarks are the property of their respective owners.
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Chapter 1

Architecture Overview

1.1 Introduction.................................................................................................................................................................30
1.2 Architecture Overview............................................................................................................................................... 31
1.3 Functional Overview.................................................................................................................................................. 32
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1.1 Introduction

The CC323x device is part of the SimpleLink™ microcontroller (MCU) platform which consists of Wi-Fi®, Bluetooth® low energy, Sub-1 GHz and host MCUs, which all share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink™ platform lets you add any combination of the devices from the portfolio into your design. The ultimate goal of the SimpleLink™ platform is to achieve 100 percent code reuse when your design requirements change. For more information, visit www.ti.com/simplelink.
The applications MCU subsystem contains an industry-standard Arm Cortex-M4 processor core running at 80 MHz. The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD, UART, SPI, I2C, and 4-channel ADC. The CC32xx family of devices includes flexible embedded RAM for code and data, and ROM with external serial flash bootloader and peripheral drivers.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a chip™, and contains an additional dedicated Arm MCU that completely offloads the applications MCU. This subsystem includes an 802.11 a/b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit encryption. The CC32xx device supports Station, Access Point, and Wi-Fi Direct® modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a chip™ includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols.
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