CC3200MOD SimpleLink™ Wi-Fi®and Internet-of-Things Module Solution, a Single-Chip
Wireless MCU
1Module Overview
1.1Features
1
• The CC3200MOD is a Wi-Fi Module that Consists
of the CC3200R1M2RGC Single-Chip Wireless
MCU. This Fully Integrated Module Includes all
Required Clocks, SPI Flash, and Passives.
• Modular FCC, IC, and CE Certifications Save
Customer Effort, Time, and Money
• Wi-Fi CERTIFIED™ Modules, With Ability to
Request Certificate Transfer for Wi-Fi Alliance
Members
• 1.27-mm Pitch LGA Package for Easy Assembly
and Low-Cost PCB Design
• Applications Microcontroller Subsystem
– ARM Cortex-M4 Core at 80 MHz
– Embedded Memory Options
•Integrated Serial
•RAM (up to 256KB)
•Peripheral Drivers in ROM
– Hardware Crypto Engine for Advanced
Hardware Security Including
•AES, DES, and 3DES
•SHA and MD5
•CRC and Checksum
– 8-Bit, Fast, Parallel Camera Interface
– 1 Multichannel Audio Serial Port (McASP)
Interface With Support for I2S Format
– 1 SD (MMC) Interface
– 32-Channel Micro Direct Memory Access
(ADCs)
– Up to 25 Individually Programmable GPIO Pins
• Wi-Fi Network Processor Subsystem
– 802.11b/g/n Radio, Baseband, and Medium
Access Control
– TCP/IP Stack
•8 Simultaneous TCP, UDP, or RAW Sockets
•2 Simultaneous TLS v1.2 or SSL 3.0
Sockets
– Powerful Crypto Engine for Fast, Secured
WLAN Connections With 256-Bit Encryption
– Station, Access Point, and Wi-Fi Direct™ Modes
– WPA2 Personal and Enterprise Security
– SimpleLink Connection Manager for Managing
Wi-Fi Security States
– TX Power
•17 dBm at 1 DSSS
•17.25 dBm at 11 CCK
•13.5 dBm at 54 OFDM
– RX Sensitivity
•–94.7 dBm at 1 DSSS
•–87 dBm at 11 CCK
•–73 dBm at 54 OFDM
– Application Throughput
•UDP: 16 Mbps
•TCP: 13 Mbps
• Power-Management Subsystem
– Integrated DC-DC Converter With a Wide-
Supply Voltage:
•VBAT: 2.3 to 3.6 V
– Low-Power Consumption at 3.6 V
•Hibernate With Real-Time Clock (RTC):
7 μA
•Low-Power Deep Sleep: <275 μA
•RX Traffic: 59 mA at 54 OFDM
•TX Traffic: 229 mA at 54 OFDM
– Additional Integrated Components
•40.0-MHz Crystal
•32.768-kHz Crystal (RTC)
•8-Mbit SPI Serial Flash RF Filter and
Passive Components
– Package and Operating Conditions
•1.27-mm Pitch, 63-Pin, 20.5-mm ×
17.5 mm LGA Package for Easy Assembly
and Low-Cost PCB Design
•Operating Temperature Range: –20°C to
70°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3200MOD
SWRS166 –DECEMBER 2014
1.2Applications
•Internet of Things (IoT)•Internet Gateway
•Cloud Connectivity•Industrial Control
•Home Automation•Smart Plug and Metering
•Home Appliances•Wireless Audio
•Access Control•IP Network Sensor Nodes
•Security Systems•Wearables
•Smart Energy
1.3Description
Start your design with the industry’s first programmable FCC, IC, CE, and Wi-Fi Certified Wireless
microcontroller (MCU) module with built-in Wi-Fi connectivity. Created for the Internet of Things (IoT), the
SimpleLink CC3200MOD is a wireless MCU module that integrates an ARM Cortex-M4 MCU, allowing
customers to develop an entire application with a single device. With on-chip Wi-Fi, Internet, and robust
security protocols, no prior Wi-Fi experience is required for faster development. The CC3200MOD
integrates all required system-level hardware components including clocks, SPI flash, RF switch, and
passives into an LGA package for easy assembly and low-cost PCB design. The CC3200MOD is provided
as a complete platform solution including software, sample applications, tools, user and programming
guides, reference designs, and the TI E2E™ support community
www.ti.com
The applications MCU subsystem contains an industry-standard ARM Cortex-M4 core running at 80 MHz.
The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD/MMC,
UART, SPI, I2C, and four-channel ADC. The CC3200 family includes flexible embedded RAM for code
and data; ROM with external serial flash bootloader and peripheral drivers; and SPI flash for Wi-Fi network
processor service packs, Wi-Fi certificates, and credentials.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a-chip™ and contains an additional
dedicated ARM MCU that completely off-loads the applications MCU. This subsystem includes an 802.11
b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with
256-bit encryption. The CC3200MOD supports station, access point, and Wi-Fi Direct™ modes. The
device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a-chip
includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols. The
power-management subsystem includes integrated DC-DC converters supporting a wide range of supply
voltages. This subsystem enables low-power consumption modes, such as the hibernate with RTC mode
requiring less than 7 μA of current.
Table 1-1. Module Information
PART NUMBERPACKAGEBODY SIZE
CC3200MODR1M2AMOBMOB (63)20.5 mm × 17.5 mm
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.
Table 3-1 lists the pin descriptions of the CC3200MOD module. "DEVICE PIN NO" refers to the pin
number of the QFN part CC3200. This is stated here because the QFN pin is referred to in the SDK.
Table 3-1. Pin Attributes
MODULEMODULE PIN NAMETYPEDEVICE PIN NO MODULE PIN DESCRIPTION
PIN NO.
1GND-Ground
2GND-Ground
3GPIO10I/O1GPIO
4GPIO11I/O2GPIO
5GPIO14I/O5GPIO
6GPIO15I/O6GPIO
7GPIO16I/O7GPIO
8GPIO17I/O8GPIO
9GPIO12I/O3GPIO
10GPIO13I/O4GPIO
11GPIO22I/O15GPIO
12JTAG_TDII/O16GPIO
13NC-13Reserved for TI
14NC-14Reserved for TI
15NC-11Reserved for TI
16GND-Ground
17NC-12Reserved for TI
18JTAG_TDOI/O17GPIO
19GPIO28I/O18GPIO
20NC-23Unused. Do not connect.
21JTAG_TCKI/O19JTAG TCK input. Needs 100-kΩ pulldown resistor to ground.
22JTAG_TMSI/O20JTAG TMS input. Leave unconnected if not used on product.
23SOP2-21Add 2.7-kΩ pulldown resistor to ground needed for functional
24SOP1-34Reserved. Do not connect.
25ANTSEL1I/O29Antenna selection control
26ANTSEL2I/O30Antenna selection control
27GND-Ground
28GND-Ground
29NC-27, 28Reserved for TI
30GND-Ground
31RF_BGI/O312.4-GHz RF input/output
32GND-Ground
33NC-38Reserved for TI
34SOP0-35Optional 10-kΩ pullup if user chooses to use SWD debug mode
35nRESETI32Power on reset. Does not require external RC circuit
36VBAT_DCDC_ANA-37Power supply for the device, can be connected to battery (2.3 V
37VBAT_DCDC_PA-39Power supply for the device, can be connected to battery (2.3 V
38GND-Ground
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
mode. Add option to pullup required for entering the UART load
mode for flashing.
The module makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled
using a combination of hardware configuration (at module reset) and register control.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware
does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode
used. Table 3-2 describes the general pin attributes and presents an overview of pin multiplexing. All pin
multiplexing options are configurable using the pin mux registers. The following special considerations
apply:
•All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is configurable individually for each
pin.
•All I/Os support 10-μA pullups and pulldowns.
•These pulls are not active and all of the I/Os remain floating while the device is in Hibernate state.
•The VIO and VBAT supply must be tied together at all times.
•All digital I/Os are nonfail-safe.
If an external device drives a positive voltage to the signal pads and the CC3200MOD is not
powered, DC current is drawn from the other device. If the drive strength of the external
device is adequate, an unintentional wakeup and boot of the CC3200MOD can occur. To
prevent current draw, TI recommends any one of the following:
•All devices interfaced to the CC3200MOD must be powered from the same power rail as
the chip.
•Use level-shifters between the module and any external devices fed from other
independent rails.
•The nRESET pin of the CC3200MOD must be held low until the VBAT supply to the
module is driven and stable
12GT_CCP00Timer Capture PortI
(1) LPDS mode: The state of unused GPIOs in LPDS is input with 500-kΩ pulldown. For all used GPIOs , the user can enable internal pulls, which would hold them in a valid state.
(2) Hibernate mode: The CC3200 device leaves the digital pins in a Hi-Z state without any internal pulls when the device enters hibernate state. This can cause glitches on output lines unless
held at valid levels by external resistors.
(3) To minimize leakage in some serial flash vendors during LPDS, TI recommends the user application always enable internal weak pulldowns on FLASH_SPI_DATA and FLASH_SPI_CLK
pins.
(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During
hibernate low-power mode, the pin is in a high impedance state but pulled down for SOP mode to disable TCXO. Because of SOP functionality, the pin must be used as output only.
(5) For details on proper use, see Drive Strength and Reset States for Analog-Digital Multiplexed Pins.
(6) This pin is one of three that must have a passive pullup or pulldown resistor on board to configure the chip hardware power-up mode. For this reason, the pin must be output only when
used for digital functions.
(7) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3200 module between two antennas. These pins should not be
used for other functionalities in general.
(8) Device firmware automatically enables the digital path during ROM boot.
(9) This pin is shared by the ADC inputs and digital I/O pad cells. Important: The ADC inputs are tolerant up to 1.8 V. On the other hand, the digital pads can tolerate up to 3.6 V. Hence, care
must be taken to prevent accidental damage to the ADC inputs. TI recommends that the output buffer(s) of the digital I/Os corresponding to the desired ADC channel be disabled first (that
is, converted to high-impedance state), and thereafter the respective pass switches (S7, S8, S9, S10) should be enabled (see Drive Strength and Reset States for Analog-Digital
Multiplexed Pins).
(10) Requires user configuration to enable the ADC channel analog switch. (The switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC
switch.
3.4Recommended Pin Multiplexing Configurations
Table 3-3 lists the recommended pin multiplexing configurations.
(1) Pins marked "wake" can be configured to wake up the chip from HIBERNATE or LPDS state. In the current silicon revision, any wake pin can trigger wake up from HIBERNATE. The
wakeup monitor in the hibernate control module logically ORs these pins applying a selection mask. However, wakeup from LPDS state can be triggered only by one of the wakeup pins
that can be configured before entering LPDS. The core digital wakeup monitor use a mux to select one of these pins to monitor.
3.5Drive Strength and Reset States for Analog-Digital Multiplexed Pins
Table 3-4 describes the use, drive strength, and default state of these pins at first-time power up and reset
(nRESET pulled low).
Table 3-4. Drive Strength and Reset States for Analog-Digital Multiplexed Pins
www.ti.com
Pin
25of the RF switch (ANTSEL1).4
26of the RF switch (ANTSEL2).4
44Generic I/O4
42Generic I/O4
474
484
494
504
Board Level Configuration Default State at First Power Analog Switches (ACTIVE,Maximum Effective Drive
Connected to the enable pin
Other use not recommended.
Connected to the enable pin
Other use not recommended.
Analog signal (1.8 VADC is isolated. The digitalDetermined by the I/O state,
absolute, 1.46 V full scale)I/O cell is also isolated.as are other digital I/Os.
Analog signal (1.8 VADC is isolated. The digitalDetermined by the I/O state,
absolute, 1.46 V full scale)I/O cell is also isolated.as are other digital I/Os.
Analog signal (1.8 VADC is isolated. The digitalDetermined by the I/O state,
absolute, 1.46 V full scale)I/O cell is also isolated.as are other digital I/Os.
Analog signal (1.8 VADC is isolated. The digitalDetermined by the I/O state,
absolute, 1.46 V full scale)I/O cell is also isolated.as are other digital I/Os.
and UseUp or Forced ResetLPDS, and HIB PowerStrength (mA)
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.as are other digital I/Os.
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.as are other digital I/Os.
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.as are other digital I/Os.
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.as are other digital I/Os.
State after Configuration of
Modes)
3.6Pad State After Application of Power To Chip But Prior To Reset Release
When a stable power is applied to the CC3200 chip for the first time or when supply voltage is restored to
the proper value following a prior period with supply voltage below 1.5 V, the level of the digital pads are
undefined in the period starting from the release of nRESET and until DIG_DCDC powers up. This period
is less than approximately 10 ms. During this period, pads can be internally pulled weakly in either
direction. If a certain set of pins are required to have a definite value during this pre-reset period, an
appropriate pullup or pulldown must be used at the board level. The recommended value of this external
pull is 2.7 KΩ.
These specifications indicate levels where permanent damage to the module can occur. Functional operation is not ensured
under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term
reliability of the module.
SYMBOLCONDITIONMINTYPMAXUNIT
VBAT and VIORespect to GND–0.53.33.8V
Digital I/ORespect to GND–0.5–VBAT + 0.5V
RF pins–0.52.1V
Analog pins–0.52.1V
Temperature–40+85°C
4.2Handling Ratings
MINMAXUNIT
T
stg
V
ESD
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Storage temperature range–4085°C
Electrostatic discharge (ESD)
performance:
Human body model (HBM), per ANSI/ESDA/JEDEC
(1)
JS001
Charged device model (CDM),
per JESD22-C101
(2)
All pins–250250V
–1.01.0kV
4.3Power-On Hours
CONDITIONSPOH
T
up to 85°C, assuming 20% active mode and 80% sleep mode17,500
Ambient
4.4Recommended Operating Conditions
Function operation is not ensured outside this limit, and operation outside this limit for extended periods can adversely affect
long-term reliability of the module.
SYMBOLCONDITION
VBAT and VIOBattery mode2.33.33.6V
Operating temperature––202570°C
Ambient thermal slew–2020°C/minute
(1) Operating temperature is limited by crystal frequency variation.
(2) To ensure WLAN performance, the ripple on the power supply must be less than ±300 mV.
The module enters a brown-out condition whenever the input voltage dips below V
BROWN
(see Figure 4-1 and
Figure 4-2). This condition must be considered during design of the power supply routing, especially if operating
from a battery. High-current operations (such as a TX packet) cause a dip in the supply voltage, potentially
triggering a brown-out. The resistance includes the internal resistance of the battery, contact resistance of the
battery holder (4 contacts for a 2 x AA battery) and the wiring and PCB routing resistance.
Figure 4-1. Brown-Out and Black-Out Levels (1 of 2)
Figure 4-2. Brown-Out and Black-Out Levels (2 of 2)
In the brown-out condition, all sections of the CC3200MOD shut down within the module except for the Hibernate
block (including the 32-kHz RTC clock), which remains on. The current in this state can reach approximately 400
µA.
The black-out condition is equivalent to a hardware reset event in which all states within the module are lost.
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(3) m/s = meters per second.
(3)
4.8Reset Requirement
PARAMETERSYMBOLMINTYPMAXUNIT
Operation mode levelViH0.65 × VBATV
Shutdown mode level
Minimum time for nReset low for resetting the5ms
module
Rise/fall timesTr/Tf20µs
(1) The nRESET pin must be held below 0.6 V for the module to register a reset.
(1) TX power level = 0 implies maximum power (see Figure 4-3 through Figure 4-5). TX power level = 4 implies output power backed off
approximately 4 dB.
(2) The CC3200 system is a constant power-source system. The active current numbers scale based on the V
(3) DTIM = 1
(4) The LPDS number reported is with retention of 64KB MCU SRAM. The CC3200 device can be configured to retain 0KB, 64KB, 128KB,
192KB or 256KB SRAM in LPDS. Each 64KB retained increases LPDS current by 4 µA.
(5) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms . Calibration is performed sparingly,
typically when coming out of Hibernate and only if temperature has changed by more than 20°C or the time elapsed from prior
calibration is greater than 24 hours.
= 3.6 V
BAT
PARAMETERTEST CONDITIONS
1 DSSS
TX6 OFDM
NWP ACTIVE
54 OFDM
1 DSSS59
54 OFDM59
NWP idle connected
RX
(3)
1 DSSS
TX6 OFDM
NWP ACTIVE
54 OFDM
1 DSSS56
54 OFDM56
NWP idle connected
RX
(3)
1 DSSS
TX6 OFDM
NWP active
1 DSSS53
54 OFDM53
NWP LPDS
(4)
NWP idle connected
(5)
RX
(3)
V
= 3.3 V450
BAT
V
= 2.3 V620
BAT
(1) (2)
TX power level = 0278
TX power level = 4194
TX power level = 0254
TX power level = 4185
TX power level = 4166
TX power level = 0275
TX power level = 4191
TX power level = 0251
TX power level = 4182
TX power level = 4163
TX power level = 0272
TX power level = 4188
TX power level = 0248
TX power level = 4179
TX power level = 0223
TX power level = 4160
Note: The area enclosed in the circle represents a significant reduction in current when transitioning from TX power
level 3 to 4. In the case of lower range requirements (13-dbm output power), TI recommends using TX power level 4
to reduce the current.
Figure 4-3. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
Figure 4-4. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
Sensitivity
(8% PER for 11b rates, 10% PER for9 OFDM–88.0
11g/11n rates)(10% PER)
Maximum input level
(10% PER)
(1) Sensitivity is 1-dB worse on channel 13 (2472 MHz).
= 2.3 to 3.6 V. Parameters measured at module pin on channel 7 (2442 MHz)
BAT
PARAMETERCONDITION (Mbps)MINTYPMAXUNITS
1 DSSS–94.7
2 DSSS–92.6
11 CCK–87.0
6 OFDM–89.0
(1)
18 OFDM–85.0dBm
36 OFDM–79.5
54 OFDM–73.0
MCS7 (Mixed Mode)–69.0
802.11b–3.0
802.11g–9.0
4.10.1WLAN Transmitter Characteristics(1)
TA= +25°C, V
PARAMETERSCONDITIONSMINTYPMAXUNIT
Max RMS Output Power measured at 1 dB
from IEEE spectral mask or EVM
Transmit center frequency accuracy–2020ppm
(1) Channel-to-channel variation is up to 2 dB. The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission
limits.
= 2.3 to 3.6 V. Parameters measured at module pin on channel 7 (2442 MHz)
Figure 4-8 shows the timing diagram for wakeup from the hibernate state.
CC3200MOD
SWRS166 –DECEMBER 2014
Figure 4-8. nHIB Timing Diagram
NOTE
The 32.768-kHz XTAL is kept enabled by default when the chip goes to hibernate.
Table 4-3 describes the timing requirements for nHIB.
Table 4-3. Software Hibernate Timing Requirements
ITEMNAMEDESCRIPTIONMINTYPMAX
T
hib_min
T
wake_from_
(1)
hib
(1) Twake_from_hib can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when
(2) Wake-up time can extend to 75 ms if a patch is downloaded from the serial flash.
Minimum hibernate10 ms
time
Hardware wakeup50 ms
time plus firmware
initialization time
exiting Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.
(2)
4.11.2 Peripherals
This section describes the peripherals that are supported by the CC3200 module:
The CC3200 microcontroller includes one SPI module, which can be configured as a master or slave
device. The SPI includes a serial clock with programmable frequency, polarity, and phase, a
programmable timing control between chip select and external clock generation, and a programmable
delay before the first SPI word is transmitted. Slave mode does not include a dead cycle between two
successive words.
Figure 4-9 shows the timing diagram for the SPI master.
www.ti.com
Figure 4-9. SPI Master Timing Diagram
Table 4-4 lists the timing parameters for the SPI master.
Figure 4-10 shows the timing diagram for the SPI slave.
Figure 4-10. SPI Slave Timing Diagram
Table 4-5 lists the timing parameters for the SPI slave.
Table 4-5. SPI Slave Timing Parameters
PARAMETERPARAMETER
NUMBER
I1FClock frequency @ VBAT = 3.3 V20MHz
I2TclkClock period50ns
I3tLPClock low period25ns
I4tHTClock high period25ns
I5DDuty cycle45%55%
I6tISRX data setup time4ns
I7tIHRX data hold time4ns
I8tODTX data output delay20
I9tOHTX data hold time24ns
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
(1)
PARAMETER NAMEMINMAXUNIT
Clock frequency @ VBAT ≤ 2.1 V12
CC3200MOD
SWRS166 –DECEMBER 2014
4.11.2.2 McASP
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of
transmit and receive sections that operate synchronously and have programmable clock and frame-sync
polarity. A fractional divider is available for bit-clock generation.
4.11.2.2.1 I2S Transmit Mode
Figure 4-11 shows the timing diagram for the I2S transmit mode.
Table 4-6 lists the timing parameters for the I2S transmit mode.
Table 4-6. I2S Transmit Mode Timing Parameters
PARAMETERPARAMETER
NUMBER
I1fclkClock frequency9.216MHz
I2tLPClock low period1/2 fclkns
I3tHTClock high period1/2 fclkns
I4tOHTX data hold time22ns
(1) Timing parameter assumes a maximum load of 20 pF.
(1)
PARAMETER NAMEMINMAXUNIT
4.11.2.2.2 I2S Receive Mode
Figure 4-12 shows the timing diagram for the I2S receive mode.
www.ti.com
Figure 4-12. I2S Receive Mode Timing Diagram
Table 4-7 lists the timing parameters for the I2S receive mode.
Table 4-7. I2S Receive Mode Timing Parameters
PARAMETERPARAMETER
NUMBER
I1fclkClock frequency9.216MHz
I2tLPClock low period1/2 fclkns
I3tHTClock high period1/2 fclkns
I4tOHRX data hold time0ns
I5tOSRX data setup time15ns
(1) Timing parameter assumes a maximum load of 20 pF.
(1)
PARAMETER NAMEMINMAXUNIT
4.11.2.3 GPIO
All digital pins of the device can be used as general-purpose input/output (GPIO) pins.The GPIO module
consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24
programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and
pulldown strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.
Table 4-10 lists the input transition time parameters.
Table 4-10. GPIO Input Transition Time Parameters
PARAMETERCONDITIONSYMBOLMINMAXUNIT
Input transition time
(tr,tf), 10% to 90%
t
r
t
f
13
13
4.11.2.4 I2C
The CC3200 microcontroller includes one I2C module operating with standard (100 Kbps) or fast (400
Kbps) transmission speeds.
Figure 4-14 shows the I2C timing diagram.
ns
Figure 4-14. I2C Timing
Table 4-11 lists the I2C timing parameters.
Table 4-11. I2C Timing Parameters
PARAMETERPARAMETERPARAMETER NAMEMINMAXUNIT
NUMBER
I2t
I3t
I4t
I5t
I6t
I7t
I8t
I9t
LP
SRT
DH
SFT
HT
DS
SCSR
SCS
Clock low periodSee
SCL/SDA rise time–See
Data hold timeNA–
SCL/SDA fall time–3ns
Clock high timeSee
Data setup timetLP/2System clock
Start condition setup36–System clock
time
Stop condition setup24–System clock
time
(1) All timing is with 6-mA drive and 20-pF load.
(2) This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
(3) Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the external signal capacitance and external pullup register value.
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,Test Access Port and Boundary- Scan Architecture.
Figure 4-15 shows the JTAG timing diagram.
CC3200MOD
SWRS166 –DECEMBER 2014
Figure 4-15. JTAG Timing
Table 4-12 lists the JTAG timing parameters.
Table 4-12. JTAG Timing Parameters
PARAMETERPARAMETERPARAMETER NAMEMINMAXUNIT
NUMBER
J1fTCKClock frequency15MHz
J2tTCKClock period1/fTCKns
J3tCLClock low periodtTCK/2ns
J4tCHClock high periodtTCK/2ns
J7tTMS_SUTMS setup time1
J8tTMS_HOTMS hold time16
J9tTDI_SUTDI setup time1
J10tTDI_HOTDI hold time16
J11tTDO_HOTDO hold time15
4.11.2.6 ADC
Table 4-13 lists the ADC electrical specifications.
Table 4-13. ADC Electrical Specifications
PARAMETERDESCRIPTIONCONDITION ANDMINTYPMAXUNIT
NbitsNumber of bits12Bits
INLIntegral nonlinearityWorst-case deviation from–2.52.5LSB
DNLDifferential nonlinearityWorst-case deviation of any step–14LSB
Input range01.4V
ASSUMPTIONS
histogram method over full scale
(not including first and last three
LSB levels)
Sampling rate of each ADC62.5KSPS
F_input_maxMaximum input signal frequency31kHz
SINADSignal-to-noise and distortionInput frequency dc to 300 Hz5560dB
I_activeActive supply currentAverage for analog-to-digital1.5mA
I_PDPower-down supply current forTotal for analog-to-digital when1µA
core supplynot active (this must be the SoC
Absolute offset errorFCLK = 10 MHz±2mV
Gain error±2%
ASSUMPTIONS
clock rate
and 1.4 Vppsine wave input
during conversion without
reference current
level test)
Figure 4-16 shows the ADC clock timing diagram.
4.11.2.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in
a FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 4-17 shows the timing diagram for the camera parallel port.
Figure 4-16. ADC Clock Timing
Figure 4-17. Camera Parallel Port Timing Diagram
Table 4-14 lists the timing parameters for the camera parallel port.
The CC3200 device includes two UARTs with the following features:
•Programmable baud-rate generator allowing speeds up to 3 Mbps
•Separate 16 x 8 TX and RX FIFOs to reduce CPU interrupt service loading
•Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered
interface
•FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
•Standard asynchronous communication bits for start, stop, and parity
•Line-break generation and detection
•Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation and detection
– 1 or 2 stop-bit generation
•RTS and CTS hardware flow support
•Standard FIFO-level and End-of-Transmission interrupts
•Efficient transfers using μDMA
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
The CC3200 device has a rich set of peripherals for diverse application requirements. The device
optimizes bus matrix and memory management to give the application developer the needed advantage.
This section briefly highlights the internal details of the CC3200 device and offers suggestions for
application configurations.
5.1.1Module Features
5.2Functional Block Diagram
Figure 5-1 shows the functional block diagram of the CC3200MOD SimpleLink Wi-Fi solution.
www.ti.com
5.3ARM Cortex-M4 Processor Core Subsystem
The high-performance ARM Cortex-M4 processor provides a low-cost platform that meets the needs of
minimal memory implementation, reduced pin count, and low power consumption, while delivering
outstanding computational performance and exceptional system response to interrupts.
•The ARM Cortex-M4 core has low-latency interrupt processing with the following features:
– A 32-bit ARM Cortex Thumb® instruction set optimized for embedded applications
– Handler and thread modes
– Low-latency interrupt handling by automatic processor state saving and restoration during entry and
•Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low
•Bus interfaces:
•Low-cost debug solution featuring:
CC3200MOD
SWRS166 –DECEMBER 2014
latency interrupt processing. Features include:
– Bits of priority configurable from 3 to 8
– Dynamic reprioritization of interrupts
– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt
levels
– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt
processing without the overhead of state saving and restoration between interrupts
– Processor state automatically saved on interrupt entry and restored on interrupt exit with no
instruction overhead
– Wake-up interrupt controller (WIC) providing ultra-low power sleep mode support
– Three advanced high-performance bus (AHB-Lite) interfaces: ICode, DCode, and system bus
interfaces
– Bit-band support for memory and select peripheral that includes atomic bit-band write and read
operations
– Debug access to all memory and registers in the system, including access to memory-mapped
devices, access to internal core registers when the core is halted, and access to debug control
registers even while SYSRESETn is asserted
– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
5.4CC3200 Device Encryption
Figure 5-2 shows a standard MCU for the CC3200 device. Application image and user data files are not
encrypted. Network certificates are encrypted using a device-specific key.
The Wi-Fi network processor subsystem includes a dedicated ARM MCU to completely offload the host
MCU along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast,
secure WLAN and Internet connections with 256-bit encryption. The CC3200 device supports station, AP,
and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0.
The Wi-Fi network processor includes an embedded IPv4 TCP/IP stack.
Table 5-1 summarizes the NWP features.
Table 5-1. Summary of Features Supported by the NWP Subsystem
ITEMDOMAINCATEGORYFEATUREDETAILS
1TCP/IPNetwork StackIPv4Baseline IPv4 stack
2TCP/IPNetwork StackTCP/UDPBase protocols
3TCP/IPProtocolsDHCPClient and server mode
4TCP/IPProtocolsARPSupport ARP protocol
5TCP/IPProtocolsDNS/mDNSDNS Address resolution and local server
6TCP/IPProtocolsIGMPUp to IGMPv3 for multicast management
7TCP/IPApplicationsmDNSSupport multicast DNS for service publishing over IP
8TCP/IPApplicationsmDNS-SDService discovery protocol over IP in local network
9TCP/IPApplicationsWeb Sever/HTTP Server URL static and dynamic response with template.
10TCP/IPSecurityTLS/SSLTLS v1.2 (client/server)/SSL v3.0
11TCP/IPSecurityTLS/SSLFor the supported Cipher Suite, go to SimpleLink Wi-Fi
CC3200 SDK.
12TCP/IPSocketsRAW SocketsUser-defined encapsulation at WLAN MAC/PHY or IP
layers
13WLANConnectionPoliciesAllows management of connection and reconnection
policy
14WLANMACPromiscuous modeFilter-based Promiscuous mode frame receiver
15WLANPerformanceInitialization timeFrom enable to first connection to open AP less than
50 ms
16WLANPerformanceThroughputUDP = 16 Mbps
17WLANPerformanceThroughputTCP = 13 Mbps
18WLANProvisioningWPS2Enrollee using push button or PIN method.
19WLANProvisioningAP ConfigAP mode for initial product configuration (with
configurable Web page and beacon Info element)
20WLANProvisioningSmartConfigAlternate method for initial product configuration
21WLANRoleStation802.11bgn Station with legacy 802.11 power save
22WLANRoleSoft AP802.11 bg single station with legacy 802.11 power
save
23WLANRoleP2PP2P operation as GO
24WLANRoleP2PP2P operation as CLIENT
25WLANSecuritySTA-PersonalWPA2 personal security
26WLANSecuritySTA-EnterpriseWPA2 enterprise security
27WLANSecuritySTA-EnterpriseEAP-TLS
28WLANSecuritySTA-EnterpriseEAP-PEAPv0/TLS
29WLANSecuritySTA-EnterpriseEAP-PEAPv1/TLS
30WLANSecuritySTA-EnterpriseEAP-PEAPv0/MSCHAPv2
31WLANSecuritySTA-EnterpriseEAP-PEAPv1/MSCHAPv2
32WLANSecuritySTA-EnterpriseEAP-TTLS/EAP-TLS
33WLANSecuritySTA-EnterpriseEAP-TTLS/MSCHAPv2
34WLANSecurityAP-PersonalWPA2 personal security
The CC3200 power-management subsystem contains DC-DC converters to accommodate the differing
voltage or current requirements of the system. The module can operate from an input voltage ranging from
2.3 V to 3.6 V and can be directly connected to 2xAA Alkaline batteries.
The CC3200MOD is a fully integrated module based WLAN radio solution used on an embedded system
with a wide-voltage supply range. The internal power management, including DC-DC converters and
LDOs, generates all of the voltages required for the module to operate from a wide variety of input
sources. For maximum flexibility, the module can operate in the modes described in the following sections.
5.6.1VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the module is powered directly by the battery or preregulated 3.3-V
supply. All other voltages required to operate the device are generated internally by the DC-DC
converters. This scheme is the most common mode for the device as it supports wide-voltage operation
from 2.3 to 3.6 V.
5.7Low-Power Operating Mode
From a power-management perspective, the CC3200 device comprises the following two independent
subsystems:
•Cortex-M4 application processor subsystem
•Networking subsystem
CC3200MOD
SWRS166 –DECEMBER 2014
Each subsystem operates in one of several power states.
The Cortex-M4 application processor runs the user application loaded from an external serial flash. The
networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer functions.
The user program controls the power state of the application processor subsystem and can be in one of
the five modes described in Table 5-2.
NOTE
Table 5-2 lists the modes by power consumption, with highest power modes listed first.
Table 5-2. User Program Modes
APPLICATION PROCESSORDESCRIPTION
(MCU) MODE
MCU active modeMCU executing code at 80-MHz state rate
MCU sleep modeThe MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode
MCU LPDS modeState information is lost and only certain MCU-specific register configurations are retained. The MCU
MCU hibernate modeThe lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly
offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity
from any GPIO line or peripheral.
can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)
Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory
retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU
can be configured to wake up using the RTC timer or by an external event on specific GPIOs defined in
Table 3-2 as the wake-up source.
powered by the input supply is retained. The real-time clock (RTC) clock keeps running and the MCU
supports wakeup from an external event or from an RTC timer expiry. Wake-up time is longer than
LPDS mode at about 15 ms plus the time to load the application from serial flash, which varies
according to code size. In this mode, the MCU can be configured to wake up using the RTC timer or
external event on a GPIO (GPIO0–GPIO6).
The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no
network activity, the NWP sleeps most of the time and wakes up only for beacon reception.
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Table 5-3. Networking Subsystem Modes
NETWORK PROCESSORDESCRIPTION
Network active mode processingTransmitting or receiving IP protocol packets
layer 3, 2, and 1
Network active mode (processing Transmitting or receiving MAC management frames; IP processing not required.
layer 2 and 1)
Network active listen modeSpecial power optimized active mode for receiving beacon frames (no other frames supported)
Network connected IdleA composite mode that implements 802.11 infrastructure power save operation. The CC3200R network
Network LPDS modeLow-power state between beacons in which the state is retained by the network processor, allowing for
Network disabled
MODE
processor automatically goes into LPDS mode between beacons and then wakes to active listen mode
to receive a beacon and determine if there is pending traffic at the access point. If not, the network
processor returns to LPDS mode and the cycle repeats.
a rapid wake up.
The operation of the application and network processor ensures that the device remains in the lowest
power mode most of the time to preserve battery life. Table 5-4 summarizes the important CC3200 chiplevel power modes.
Table 5-4. Important Chip-Level Power Modes
POWER STATESNETWORK PROCESSOR ACTIVE MODENETWORK PROCESSOR LPDS MODENETWORK
FOR APPLICATIONS(TRANSMIT, RECEIVE, OR LISTEN)PROCESSOR
MCU ANDDISABLED
NETWORK
PROCESSOR
MCU active modeChip = active (C)Chip = activeChip = active
MCU LPDS modeChip = active (A)Chip = LPDS (B)Chip = LPDS
MCU hibernate mode Not supported because chip is hibernated by Not supported because chip is hibernated by Chip = hibernate (D)
MCU; thus, network processor cannot be inMCU; thus, network processor cannot be in
active modeLPDS mode
The following examples show the use of the power modes in applications:
•A product that is continuously connected to the network in the 802.11 infrastructure power-save mode
but sends and receives little data spends most of the time in connected idle, which is a composite of
modes A (receiving a beacon frame) and B (waiting for the next beacon).
•A product that is not continuously connected to the network but instead wakes up periodically (for
example, every 10 minutes) to send data spends most of the time in mode D (hibernate), jumping
briefly to mode C (active) to transmit data.
5.8Memory
5.8.1Internal Memory
The CC3200 device includes on-chip SRAM to which application programs are downloaded and executed.
The application developer must share the SRAM for code and data. To select the appropriate SRAM
configuration, see the device variants listed in the orderable addendum at the end of this datasheet. The
micro direct memory access (μDMA) controller can transfer data to and from SRAM and various
peripherals. The CC3200 ROM holds the rich set of peripheral drivers, which saves SRAM space. For
more information on drivers, see the CC3200 API list.
The CC3200 family provides up to 256KB of zero-wait-state, on-chip SRAM. Internal RAM is capable of
selective retention during LPDS mode. This internal SRAM is located at offset 0x2000 0000 of the device
memory map.
Use the µDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of
memory based on need. Retaining the memory during low-power mode provides a faster wakeup. The
application developer can choose the amount of memory to retain in multiples of 64KB. For more
information, see the API guide.
5.8.1.2ROM
The internal zero-wait-state ROM of the CC3200 device is at address 0x0000 0000 of the device memory
and programmed with the following components:
•Bootloader
•Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
The bootloader is used as an initial program loader (when the serial flash memory is empty). The CC3200
DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs
peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support.
The DriverLib APIs in ROM can be called by applications to reduce flash memory requirements and free
the flash memory to be used for other purposes.
CC3200MOD
SWRS166 –DECEMBER 2014
5.8.1.3Memory Map
Table 5-5 describes the various MCU peripherals and how they are mapped to the processor memory. For
more information on peripherals, see the API document.
Table 5-5. Memory Map
START ADDRESSEND ADDRESSDESCRIPTIONCOMMENT
0x0000 00000x0007 FFFFOn-chip ROM (Bootloader + DriverLib)
0x2000 00000x2003 FFFFBit-banded on-chip SRAM
0x2200 00000x23FF FFFFBit-band alias of 0x2000 0000 through 0x200F FFFF
0x4000 00000x4000 0FFFWatchdog timer A0
0x4000 40000x4000 4FFFGPIO port A0
0x4000 50000x4000 5FFFGPIO port A1
0x4000 60000x4000 6FFFGPIO port A2
0x4000 70000x4000 7FFFGPIO port A3
0x4000 C0000x4000 CFFFUART A0
0x4000 D0000x4000 DFFFUART A1
0x4002 00000x400 07FFI2C A0 (Master)
0x4002 08000x4002 0FFFI2C A0 (Slave)
0x4003 00000x4003 0FFFGeneral-purpose timer A0
0x4003 10000x4003 1FFFGeneral-purpose timer A1
0x4003 20000x4003 2FFFGeneral-purpose timer A2
0x4003 30000x4003 3FFFGeneral-purpose timer A3
0x400F 70000x400F 7FFFConfiguration registers
0x400F E0000x400F EFFFSystem control
0x400F F0000x400F FFFFµDMA
0x4200 00000x43FF FFFFBit band alias of 0x4000.0000 through 0x400F.FFFF
0x4401 C0000x4401 EFFFMcASP
0xE004 00000xE004 0FFFTrace port interface unit (TPIU)
0xE004 10000xE004 1FFFReserved for embedded trace macrocell (ETM)
0xE004 20000xE00F FFFFReserved
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5.9Boot Modes
5.9.1Overview
The boot process of the application processor includes two phases. The first phase consists of
unrestricted access to all register space and configuration of the specific device setting. In the second
phase, the application processor executes user-specific code.
Note: For definitions of the SoP mode functional configurations, see Table 5-6.
Figure 5-3. Bootloader Flow Chart
5.9.2Invocation Sequence/Boot Mode Selection
The following sequence of events occur during the Cortex processor boot:
1. After power-on-reset (POR), the processor starts execution.
2. The processor jumps to the first few lines (FFL) of code in the ROM to determine if the current boot is
the first device-init boot or the second MCU boot. The determination is based on the Device-Init flag in
a secure register. The Device-Init flag is set out of POR. The registers in the secure region are
accessible only in the device-init mode.
3. If the current boot is the first boot, the processor executes the device-init code from ROM.
4. At the end of the boot, the processor clears the Device-Init flag and changes the master ID of the
processor and the DMA. These registers are part of the secure region.
5. The processor resets itself, initiating a second boot.
6. During the second boot, the processor rereads the Device-Init flag, the bit is cleared, and the
processor obtains a different master ID.
7. After executing FFL and the unsecure boot code, the processor jumps to the developer code
(application).
8. For the rest of the operation (until the next power cycle), the Cortex mode is designated the MCU.
During this phase, access to the secure region is restricted.
5.9.3Boot Mode List
The CC3200 device implements a sense-on-power (SoP) scheme to determine the device operation
mode. The device can be configured to power up in one of the three following modes:
•Fn4WJ: Functional mode with a 4-wire JTAG mapped to fixed pins.
•Fn2WJ: Functional mode with a 2-wire SWD mapped to fixed pins.
•LDfrUART: UART load mode to flash the system during development and in OEM assembly line (for
example, serial flash connected to the CC3200R device).
SoP values are sensed from the device pin during power up. This encoding determines the boot flow.
Before the device is taken out of reset, the SoP values are copied to a register and then determine the
device opeartion mode while powering up. These values determine the boot flow as well as the default
mapping for some of the pins (JTAG, SWD, UART0) Table 5-6 show the pull configurations.
Table 5-6. CC32x0 Functional Configurations
NAMESoP[2]SoP[1]SoP[0]SoP MODECOMMENT
UARTLOADPullupPulldownPulldownLDfrUARTFactory/Lab Flash/SRAM load through UART.
FUNCTIONAL_PulldownPulldownPullupFn2WJFunctional development mode. In this mode, two-
2WJpin SWD is available to the developer. TMS and
FUNCTIONAL_PulldownPulldownPulldownFn4WJFunctional development mode. In this mode, four-
4WJpin JTAG is available to the developer. TDI, TMS,
Device waits indefinitely for UART to load code.
The SOP bits then must be toggled to configure
the device in functional mode. Also puts JTAG in
4-wire mode.
TCK are available for debugger connection.
TCK, and TDO are available for debugger
connection.
The recommended value of pull resistors for SOP0 and SOP1 is 100 kΩ and 2.7 kΩ for SOP2. SOP2 can
be used by the application for other functions after chip power-up is complete. However, to avoid spurious
SOP values from being sensed at power-up, TI strongly recommends that the SOP2 pin be used only for
output signals. On the other hand, the SOP0 and SOP1 pins are multiplexed with WLAN analog test pins
and are not available for other functions.
Matching circuit shown
below is for the antenna.
The module is matched
internally to 50 Ohm
JTAG/DEBUG
VCC (2.3 to 3.6 V)
R2
100K
R3
2.7 K
C3
220 uF
C2
1.0 pF
L13.6 nH
Feed
E1
2.45-GHz Ant
U1
CC3200MOD
GND
1
GND
2
GPIO10
3
GPIO11
4
GPIO14
5
GPIO15
6
GPIO16
7
GPIO17
8
GPIO12
9
GPIO13
10
GPIO22
11
JTAG_TDI
12
NC
13
NC
14
NC
15
GND
16
NC
17
JTAG_TDO
18
GPIO28
19
NC
20
JTAG_TCK
21
JTAG_TMS
22
TCXO_EN/SOP2
23
SOP1
24
ANT_SEL_1
25
ANT_SEL_2
26
GND
27
GND
28
NC
29
GND
30
RF_BG
31
GND
32
NC
33
SOP0
34
nRESET
35
VBAT_DCDC_ANA
36
VBAT_DCDC_PA
37
GND
38
NC
39
VBAT_DCDC_DIG_IO
40
NC
41
GPIO30
42
GND
43
GPIO0
44
NC
45
GPIO1
46
GPIO2
47
GPIO3
48
GPIO4
49
GPIO5
50
GPIO6
51
GPIO7
52
GPIO8
53
GPIO9
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
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6Applications, Implementation, and Layout
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1Reference Schematics
Figure 6-1 shows the reference schematic for the CC3200MOD module.
(1) Resistors are not shown here. Any resistor of 5% tolerance can be used.
PART
REFERENCE
SimpleLink Wi-Fi MCU
Module
ANT Bluetooth WLAN
ZigBee®WIMAX
Murata Electronics NorthCAP CER 1 pF 50 V
AmericaNP0 0402
Murata Electronics NorthINDUCTOR 3.6 NH
America0.1 NH 0402
6.3Layout Recommendations
6.3.1RF Section (Placement and Routing)
Being wireless device, the RF section gets the top priority in terms of layout. It is very important for the RF
section to be laid out correctly to get the optimum performance from the device. A poor layout can cause
low output power, EVM degradation, sensitivity degradation and mask violations.
The antenna is the element used to convert the guided waves on the PCB traces to the free space
electromagnetic radiation. The placement and layout of the antenna is the key to increased range and
data rates.
The following points need to be observed for the antenna.
SR NO.GUIDELINES
1Place the antenna on an edge or corner of the PCB
2Make sure that no signals are routed across the antenna elements on all the layers of the
PCB
3Most antennas, including the chip antenna used on the booster pack require ground
clearance on all the layers of the PCB. Ensure that the ground is cleared on inner layers
as well.
4Ensure that there is provision to place matching components for the antenna. These need
to be tuned for best return loss once the complete board is assembled. Any plastics or
casing should also be mounted while tuning the antenna as this can impact the
impedance.
5Ensure that the antenna impedance is 50 Ω as the device is rated to work only with a
50-Ω system.
6In case of printed antenna, ensure that the simulation is performed with the solder mask
in consideration.
7Ensure that the antenna has a near omni-directional pattern.
8The feed point of the antenna is required to be grounded
9To use the FCC certification of the Booster pack board, the antenna used should be of
the same gain or lesser. In addition, the Antenna design should be exactly copied
including the Antenna traces.
CC3200MOD
SWRS166 –DECEMBER 2014
Table 6-1. Recommended Components
CHOICEPART NUMBERMANUFACTURERNOTES
1AH316M245001-TTaiyo YudenCan be placed on edge of the
2RFANT5220110A2TWalsimNeed to place on the corner of
The RF signal from the device is routed to the antenna using a CPW-G (Coplanar Waveguide with
ground) structure. This structure offers the maximum isolation across filter gap and the best possible
shielding to the RF lines. In addition to the ground on the L1 layer, placing GND vias along the line also
provides additional shielding
Figure 6-3. Coplanar Waveguide (Cross Section) with GND and Via Stitching
1. Have a solid ground plane and ground vias under the module for stable system and thermal
dissipation.
2. Do not run signal traces underneath the module on a layer where the module is mounted.
3. RF traces must have 50-Ω impedance
4. RF trace bends must be gradual with a maximum bend of approximately 45 degrees and with trace
mitered.
5. RF traces must not have sharp corners.
6. There must be no traces or ground under the antenna section.
7. RF traces must have via stitching on the ground plane beside the RF trace on both sides.
8. RF traces must be as short as possible. The antenna, RF traces, and the module must be on the edge
of the PCB product in consideration of the product enclosure material and proximity.
The PCB bending specification shall maintain planeness at a thickness of less than 0.1 mm.
7.2Handling Environment
7.2.1Terminals
The product is mounted with motherboard through land grid array (LGA). To prevent poor soldering, do
not touch the LGA portion by hand.
7.2.2Falling
The mounted components will be damaged if the product falls or is dropped. Such damage may cause the
product malfunction.
7.3Storage Condition
7.3.1Moisture Barrier Bag Before Opened
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A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH.
The calculated shelf life for the dry-packed product shall be a 12 months from the date the bag is sealed.
7.3.2Moisture Barrier Bag Open
Humidity indicator cards must be blue, < 30%.
7.4Baking Conditions
Products require baking before mounting if:
•Humidity indicator cards read > 30%
•Temp < 30°C, humidity < 70% RH, over 96 hours
Baking condition: 90°C, 12–24 hours
Baking times: 1 time
7.5Soldering and Reflow Condition
1. Heating method: Conventional Convection or IR/convection
2. Temperature measurement: Thermocouple d = 0.1 mm to 0.2 mm CA (K) or CC (T) at soldering
portion or equivalent method.
3. Solder paste composition: Sn/3.0 Ag/0.5 Cu
4. Allowable reflow soldering times: 2 times based on the following reflow soldering profile
(see Figure 7-1).
5. Temperature profile: Reflow soldering shall be done according to the following temperature profile (see
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the CC3200MOD applications:
Software Development Tools: Code Composer Studio Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software ( DSP/BIOS™), which provides the basic run-time target
software needed to support any CC3200MOD application.
Hardware Development Tools: Extended Development System ( XDS™) Emulator
For a complete listing of development-support tools for the CC3200MOD platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
8.1.1Firmware Updates
www.ti.com
TI updates features in the service pack for this module with no published schedule. Due to the ongoing
changes, TI recommends that the user has the latest service pack in his or her module for production. To
stay informed, sign up for the SDK Alert Me button on the tools page or www.ti.com/tool/cc3200sdk.
8.2Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3200MOD and support tools (see Figure 8-1).
For orderable part numbers of CC3200MOD devices in the MOB package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online CommunityTI'sEngineer-to-Engineer(E2E) Community.Createdto foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
8.4Trademarks
SimpleLink, E2E, Internet-on-a-chip, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas
Instruments.
Macrocell is a trademark of Kappa Global Inc.
Wi-Fi CERTIFIED, Wi-Fi Direct are trademarks of Wi-Fi Alliance.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
ZigBee is a registered trademark of ZigBee Alliance.
8.5Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
CC3200MOD
SWRS166 –DECEMBER 2014
8.6Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from Disclosing party under
this Agreement, or any direct product of such technology, to any destination to which such export or reexport is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from
U.S. Department of Commerce and other competent Government authorities to the extent required by
those laws.
8.7Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document.
We offer 2 reel size options for flexibility: a 1000-unit reel and a 250-unit reel.
9.2.1 Packaging Information
Package
Orderable DeviceStatus
(1)
PinsPackage Qty Eco Plan
(2)
Lead/Ball FinishMSL, Peak Temp
(3)
Op Temp (°C)Device Marking
(4) (5)
Drawing
CC3200MODR1M2AMOBRACTIVEMOB631000RoHS ExemptNi Au3, 250°C–20 to 70CC3200MODR1M2AMOB
CC3200MODR1M2AMOBTACTIVEMOB63250RoHS ExemptNi Au3, 250°C–20 to 70CC3200MODR1M2AMOB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0
P1
B0
W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
CC3200MODR1M2AMOBRACTIVE641000TBDCall TICall TI-20 to 70
CC3200MODR1M2AMOBTACTIVE64250TBDCall TICall TI-20 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2015
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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