TTL-Compatible Output Can Sink or
Source up to 200 mA
D
Functionally Interchangeable With the
D, JG, OR P PACKAGE
(TOP VIEW)
GND
TRIG
RESET
OUT
1
2
3
4
8
7
6
5
V
CC
DISCH
THRES
CONT
Signetics NE555, SA555, SE555, SE555C;
Have Same Pinout
FK PACKAGE
(TOP VIEW)
SE555C FROM TI IS NOT RECOMMENDED
FOR NEW DESIGNS
description
These devices are precision monolithic timing
circuits capable of producing accurate time delays
or oscillation. In the time-delay or monostable
mode of operation, the timed interval is controlled
by a single external resistor and capacitor
NC
TRIG
NC
OUT
NC
NC
GND
NC
32120 19
4
5
6
7
8
910111213
VCC
NC
18
17
16
15
14
NC
DISCH
NC
THRES
NC
network. In the astable mode of operation, the
NC
NC
CONT
. These levels can
CC
frequency and duty cycle may be independently
controlled with two external resistors and a single
external capacitor.
NC–No internal connection
NC
RESET
The threshold and trigger levels are normally two-thirds and one-third, respectively , of V
be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop
is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above
the threshold level, the flip-flop is reset and the output is low. RESET can override all other inputs and can be
used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low.
Whenever the output is low, a low-impedance path is provided between DISCH and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
The NE555 is characterized for operation from 0°C to 70°C. The SA555 is characterized for operation from
–40°C to 85°C. The SE555 and SE555C are characterized for operation over the full military range of –55°C
to 125°C.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C11.2 VNE555DNE555P
–40°C to 85°C11.2 VSA555DSA555P
–55°C to 125°C
The D package is available taped and reeled. Add the suffix R to the device type (e.g., NE555DR).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
LowIrrelevantIrrelevantLowOn
High< 1/3 V
High> 1/3 V
High> 1/3 V
†
Voltage levels shown are nominal.
functional block diagram
TRIGGER VOLTAGE†THRESHOLD VOLTAGE
DD
DD
DD
FUNCTION TABLE
†
OUTPUTDISCHARGE SWITCH
IrrelevantHighOff
> 2/3 V
< 2/3 V
DD
DD
LowOn
As previously established
V
CC
8
CONT
5
R
TRIG
6
R
2
R
1
GND
THRES
RESET can override TRIG, which can override THRES.
Pin numbers shown are for the D, JG, and P packages only.
RESET
4
R1
R
S
1
3
7
OUT
DISCH
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
chip information
These chips, properly assembled, display characteristics similar to the NE555 (see electrical table for NE555Y).
Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be
mounted with conductive epoxy or a gold-silicon preform.
41
(5)
(6)
BONDING PAD ASSIGNMENTS
(3)
(4)
42
(7)
(1)
(8)
(2)
THRES
TRIG
CONT
V
CC
(8)
R
(6)
R
(2)
R
(1)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJ max = 150° C
TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
PIN (1) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP
(5)
RESET
(4)
R1
R
S
1
(3)
(7)
OUT
DISCH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
NE555, NE555Y, SA555, SE555, SE555C
UNIT
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
monostable operation
For monostable operation, any of these timers may be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to TRIG sets the flip-flop (Q goes low), drives the output high, and turns
off Q1. Capacitor C is then charged through RA until the voltage across the capacitor reaches the threshold
voltage of THRES input. If TRIG has returned to a high level, the output of the threshold comparator will reset
the flip-flop (Q
R
A
goes high), drive the output low, and discharge C through Q1.
RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9
Voltage – 2 V/div
4
7
6
2
CONT
RESET
DISCH
THRES
TRIGInput
(5 V to 15 V)
5
V
V
GND
1
CC
8
CC
OUT
R
L
3
Output
Input Voltage
Output Voltage
Capacitor Voltage
Pin numbers shown are for the D, JG, and P packages.
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG
voltage falls below the trigger threshold. Once
initiated, the sequence ends only if TRIG is high
at the end of the timing interval. Because of the
threshold level and saturation voltage of Q1,
the output pulse duration is approximately
t
= 1.1RAC. Figure 11 is a plot of the time
w
constant for various values of R
and C. The
A
threshold levels and charge rates are both directly
proportional to the supply voltage, V
The timing
CC.
interval is therefore independent of the supply
voltage, so long as the supply voltage is constant
during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing
interval discharges C and re-initiates the cycle,
commencing on the positive edge of the reset
pulse. The output is held low as long as the reset
pulse is low. To prevent false triggering, when
RESET is not used, it should be connected to V
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input
to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C will charge
through R
values of R
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈0.67•V
times (and therefore the frequency and duty cycle) are independent of the supply voltage.
R
A
R
B
C
and RB and then discharge through RB only. The duty cycle may be controlled, therefore, by the
A
and R
A
) and the trigger-voltage level (≈0.33•VCC). As in the monostable circuit, charge and discharge
CC
(see Note A)
4
7
6
2
B.
V
CC
(5 V to 15 V)
µF
0.01
Open
58
1
V
OUT
GND
CC
CONT
RESET
DISCH
THRES
TRIG
RA = 5 kΩ RL = 1 kΩ
RB = 3 k
C = 0.15 µF
R
L
3
Output
Voltage – 1 V/div
t
H
t
L
Ω See Figure 12
Output Voltage
Pin numbrs shown are for the D, JG, and P packages.
NOTE A: Decoupling CONT voltage to ground with a
capacitor may improve operation. This should be
evaluated for individual applications.
Figure 12. Circuit for Astable Operation
Capacitor Voltage
Time – 0.5 ms/div
Figure 13. Typical Astable Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and
low-level duration tL may be calculated as follows:
tH+
0.693 (RA)
tL+
0.693 (RB)C
100 k
RB)C
10 k
RA + 2 RB = 1 kΩ
RA + 2 RB = 10 kΩ
RA + 2 RB = 100 kΩ
Other useful relationships are shown below.
period+tH)
frequency
Output driver duty cycle
[
tL+
(RA)
0.693 (RA)
1.44
2RB)C
t
L
+
tH)
+
t
L
Output waveform duty cycle
Low thigh ratio
-o-
+
+
t
H
tH)
t
L
t
H
+
t
L
+
RA)
1–
R
RA)
B
R
B
R
2RB)C
R
B
RA)
2R
B
2R
B
B
1 k
100
10
f – Free-Running Frequency – Hz
1
RA + 2 RB = 1 MΩ
RA + 2 RB = 10 MΩ
0.1
0.001
C – Capacitance – µF
Figure 14. Free-Running Frequency
missing-pulse detector
The circuit shown in Figure 15 may be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is continuously retriggered
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,
missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an
output pulse as illustrated in Figure 16.
VCC (5 V to 15 V)
VCC = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 15
Input Voltage
Input
48
RESET
2
TRIG
V
CC
DISCH
OUT
R
L
3
7
R
A
Output
1001010.10.01
5
CONT
0.01 µF
Pin numbers shown are shown for the D, JG, and P packages.
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 17 illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur
during the timing cycle.
VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9
Input Voltage
Voltage – 2 V/div
Output Voltage
Capacitor Voltage
Time – 0.1 ms/div
Figure 17. Divide-By-Three Circuit Waveforms
pulse-width modulation
The operation of the timer may be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 illustrates the resulting output pulse-width modulation. While a sine-wave
modulation signal is illustrated, any wave shape could be used.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
VCC (5 V to 15 V)
R
48
GND
1
V
CC
DISCH
THRES
OUT
RESET
Clock
Modulation
Input
(see Note A)
Pin numbers shown are for the D, JG, and P packages only.
NOTE A: The modulating signal may be direct or capacitively
2
Input
TRIG
5
CONT
coupled to CONT. For direct coupling, the effects of
modulation source voltage and impedance on the bias of
the timer should be considered.
L
3
7
6
R
A
Outpu
C
Figure 18. Circuit for Pulse-Width Modulation
pulse-position modulation
RA = 3 kΩ
C = 0.02 µF
RL = 1 kΩ
See Figure 18
Modulation Input Voltage
Clock Input Voltage
Voltage – 2 V/div
Output Voltage
Capacitor Voltage
Time – 0.5 ms/div
Figure 19. Pulse-Width Modulation Waveforms
As shown in Figure 20, any of these timers may be used as a pulse-position modulator. This application
modulates the threshold voltage, and thereby the time delay, of a free-running oscillator. Figure 21 illustrates
a triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
VCC (5 V to 15 V)
CC
OUT
DISCH
R
L
3
7
6
48
RESETV
2
TRIG
Modulation
(see Note A)
Pin numbers shown are for the D, JG, and P packages only.
NOTE A: The modulating signal may be direct or capacitively
5
Input
CONT
coupled to CONT. For direct coupling, the effects of
modulation source voltage and impedance on the bias of
the timer should be considered.
S closes momentarily at t = 0.
Pin numbers shown are for the D, JG, and P packages only.
RA
33 kΩ
0.001
µF
0.01
µF
48
RESETV
2
TRIG
5
CONT
CB = 4.7 µF
RB = 100 kΩ
GND
CC
OUT
DISCH
THRES
1
33 kΩ
R
B
3
7
6
C
B
0.001
µF
0.01
µF
Output BOutput A
48
2
5
TRIG
CONT
RESETV
CC = 14.7 µF
RC = 100 kΩ
CC
OUT
DISCH
THRES
GND
1
C
C
Figure 22. Sequential Timer Circuit
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits may
be connected to provide such sequential control. The timers may be used in various combinations of astable
or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22
illustrates a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
R
3
7
6
Output C
C
See Figure 22
Output A
Output B
Voltage – 5 V/div
Output C
Figure 23. Sequential Timer Waveforms
twA
twA = 1.1 RAC
twB
twB = 1.1 RBC
twC
t = 0
t – Time – 1 s/div
A
B
twC = 1.1 RCC
C
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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