Texas Instruments RM46L852 User Manual

Download

Page 1

PRODUCTPREVIEW

RM46L852

www.ti.com

RM46L852 16/32-Bit RISC Flash Microcontroller

1 RM46L852 16/32-Bit RISC Flash Microcontroller

1.1 Features

• High-Performance Microcontroller for Safety • Two High-End Timer Modules (N2HET) Critical Applications

– Dual CPUs running in lockstep – ECC on flash and RAM interfaces – Built-In Self Test for CPU and on-chip RAMs protection each – Error Signaling Module with Error Pin – Each includes Hardware Angle Generator – Voltage and Clock Monitoring – Dedicated Transfer Units (HTU) on N2HETs

• ARM® Cortex™ – R4F 32-bit RISC CPU • Two 10/12-bit Multi-Buffered ADC Modules – 1.66DMIPS/MHz with 8-stage pipeline – ADC1: 24 channels – FPU with Single/Double Precision – ADC2: 16 channels – 12-Region Memory Protection Unit – 16 shared channels – Open Architecture with 3rd Party Support – 64 result buffers with parity protection each

• Operating Conditions • Multiple Communication Interfaces – Up to 220MHz System Clock – 10/100 Mbps Ethernet MAC (EMAC) – Core Supply Voltage (VCC): 1.14V - 1.32V • IEEE 802.3 compliant (3.3V-I/O only) – I/O Supply Voltage (VCCIO): 3.0V - 3.6V • Supports MII, RMII and MDIO

• Integrated Memory – USB (revision 2.0 full-speed) – 1.25MB Program Flash with ECC • 2-port USB Specification, revision 2.0– 192KB RAM with ECC – 64KB Flash for emulated EEPROM with ECC

• 16- bit External Memory Interface (EMIF)

• Common Platform Architecture – Consistent memory map across family – Real-Time Interrupt Timer (RTI) OS Timer – 128-channel Vectored Interrupt Module (VIM) – 2-channel Cyclic Redundancy Checker (CRC)

• Direct Memory Access (DMA) Controller – 16 Channels and 32 Control Packets – Parity protection for control packet RAM – DMA Accesses Protected by Dedicated MPU

• Frequency-Modulated Phase-Locked-Loop (FMPLL) with Built-In Slip Detector

• Separate Non-Modulating PLL

• IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components

• Advanced JTAG Security Module (AJSM)

• Trace and Calibration Capabilities – Parameter Overlay Module (POM)

• Enhanced Timing Peripherals for Motor Control – 7 Enhanced Pulse Width Modulators (ePWM) – 6 Enhanced Capture (eCAP) – 2 Enhanced Quadrature Encoder Pulse

(eQEP)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

SPNS185 –SEPTEMBER 2012

Check for Samples: RM46L852

– N2HET1: 32 programmable channels – N2HET2: 18 programmable channels – 160 Word Instruction RAM with parity

compatible host controller, based on the OHCI Specification for USB, release 1.0

• USB device compatible with the USB Specification, revision 2.0 and USB Specification, revision 1.1

– Three CAN Controllers (DCAN)

• 64 mailboxes with parity protection each

• Compliant to CAN protocol version

2.0A/B

– Inter-Integrated Circuit (I2C) – Three Multi-buffered Serial Peripheral

Interfaces (MibSPI)

• 128 Words with Parity Protection each

• 8 Transfer groups

– Up to two Standard Serial Peripheral

Interfaces (SPI)

– Two UART (SCI) interfaces, one with Local

Interconnect Network Interface (LIN 2.1) Support

• Up to 101 general purpose I/O (GIO) capable pins

– 16 dedicated GIO pins with interrupt

generation capability

• Packages – 144-pin Quad Flatpack (PGE) [Green] – 337-Ball Grid Array (ZWT) [Green]

Page 2

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

1.2 Applications

• Industrial Safety Applications – Industrial Automation – Safe PLC’s (Programmable Logic Controllers) – Power Generation and Distribution – Turbines and Windmills – Elevators and Escalators

• Medical Applications – Ventilators – Defibrillators – Infusion and Insulin pumps – Radiation therapy – Robotic surgery

www.ti.com

Submit Documentation Feedback

Page 3

PRODUCTPREVIEW

RM46L852

www.ti.com

1.3 Description

The RM46L852 is a high performance microcontroller family for safety systems. The safety architecture includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash and the data SRAM, parity on peripheral memories, and loop back capability on peripheral IOs.

The RM46L852 integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient

1.66DMIPS/MHz, and has configurations which can run up to 220MHz providing up to 365 DMIPS. The RM46L852 has 1.25MB integrated Flash and 192KB data RAM configurations with single bit error

correction and double bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable, implemented with a 64-bit-wide data bus interface. The flash operates on a

3.3V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 220MHz. The SRAM supports singlecycle read/write accesses in byte, halfword, and word modes throughout the supported frequency range..

The RM46L852 device features peripherals for real-time control-based applications, including two Next Generation High End Timer (N2HET) timing coprocessors with up to 44 total IO terminals, seven Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture Modules (eCAP), two Enhanced Quadrature Encoders (eQEP) and two 12-bit Analog-to-Digital converters supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU.

SPNS185 –SEPTEMBER 2012

The enhanced pulse width modulator (ePWM) module is able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It is easy to use and supports both high side and low side PWM and deadband generation. With integrated trip zone protection and synchronization with the on chip MibADC, the ePWM module is ideal for digital motor control applications.

The enhanced Capture (eCAP) module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM generation when not needed for capture applications.

The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groups. Each group can be converted once when triggered or configured for continuous conversion mode.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, one I2C, one Ethernet, and one USB module.. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The Ethernet module supports MII, RMII and MDIO interfaces. The USB module includes a 2-port USB host controller and a USB device controller

Submit Documentation Feedback

Page 4

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

The I2C module is a multi-master communication module providing an interface between the microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds.

A frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible clock source inputs to the global clock module (GCM). The GCM module manages the mapping between the available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low frequency output can be monitored externally as an indicator of the device operating frequency.

The Direct Memory Access Controller (DMA) has 16 channels, 32 control packets and parity protection on its memory. A Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or external Error pin/ball is triggered when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous memories or other slave devices.

A Parameter Overlay Module (POM) is included to enhance the calibration capabilities of application code. The POM can re-route Flash accesses to internal memory or to the EMIF, thus avoiding the reprogramming steps necessary for parameter updates in Flash.

With integrated safety features and a wide choice of communication and control peripherals, the RM46L852 is an ideal solution for high performance real time control applications with safety critical requirements.

www.ti.com

Submit Documentation Feedback

Page 5

PRODUCTPREVIEW

Main Cross Bar: Arbitration and Prioritization Control

CRC

Switched Central Resource

Peripheral Central Resource Bridge

Dual Cortex-R4F

CPUs in Lockstep

DCAN1

DCAN2

DCAN3

LIN

SCI

SPI4

64 KB Flash

for EEPROM

Emulation

with ECC

MibSPI1

CAN1_RX CAN1_TX CAN2_RX CAN2_TX CAN3_RX CAN3_TX MIBSPI1_CLK MIBSPI1_SIMO[1:0] MIBSPI1_SOMI[1:0]

MIBSPI1_nCS[5:0] MIBSPI1_nENA

SPI2

SPI2_CLK SPI2_SIMO SPI2_SOMI

SPI2_nCS[1:0] SPI2_nENA

MibSPI3

MIBSPI3_CLK MIBSPI3_SIMO MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA

SPI4_CLK SPI4_SIMO SPI4_SOMI SPI4_nCS0 SPI4_nENA

MibSPI5

MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MIBSPI5_nCS[3:0] MIBSPI5_nENA

LIN_RX LIN_TX

SCI_RX SCI_TX

IOMM

PMM

VIM

RTI

DCC1

DCC2

32K 32K 32K

192kB RAM

with ECC

MibADC1 MibADC2

I2C

N2HET1

GIO

I2C_SCL

I2C_SDA

GIOB[7:0]

GIOA[7:0]

AD1EVT

AD1IN[7:0]

AD2EVT

# 2 # 3

# 5

# 1 # 2

# 1

always on

Core/RAM

RAM

Core

Color Legend for

Power Domains

SYS

nPORRST nRST ECLK

ESM

nERROR

1.25MB Flash

with

ECC

32K 32K 32K

Switched

Central Resource

Switched Central Resource

N2HET2[18,16]

N2HET2[15:0]

N2HET1[31:0]

N2HET1_PIN_nDIS

N2HET2_PIN_nDIS

VSSAD

VCCAD

ADREFHI

ADREFLO

N2HET2

AD1IN[15:8] \

AD2IN[15:8]

AD1IN[23:16] \

AD2IN[7:0]

EMAC Slaves

MDIO

MII

MDCLK MDIO MII_RXD[3:0] MII_RXER MII_TXD[3:0] MII_TXEN MII_TXCLK MII_RXCLK

MII_CRS MII_RXDV MII_COL

EMIF

EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EMIF_nCS[0]

EMIF_ADDR[12:0] EMIF_BA[1:0] EMIF_DATA[15:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_nWE

EMIF_nRAS EMIF_nCAS EMIF_nRW

EMIF_nWAIT

eQEP

1,2

eQEPxA

eQEPxB eQEPxS eQEPxI

eCAP

1..6

eCAP[6:1]

ePWM

1..7

nTZ[3:1]

SYNCO SYNCI ePWMxA ePWMxB

Device

Host

USB1.OverCurrent USB1.RCV USB1.VM USB1.VP USB1.PortPower USB1.SPEED USB1.SUSPEND USB1.TXDAT USB1.TXEN USB1.TXSE0 USB2.OverCurrent USB2.RCV USB2.VM USB2.VP USB2.PortPower USB2.SPEED USB2.SUSPEND USB2.TXDAT USB2.TXEN USB2.TXSE0

USB_FUNC.GZO USB_FUNC.PUENO USB_FUNC.PUENON USB_FUNC.RXDI USB_FUNC.RXDMI USB_FUNC.RXDPI USB_FUNC.SE0O USB_FUNC.SUSPENDO USB_FUNC.TXDO USB_FUNC.VBUSI

USB Slaves

HTU1 HTU2

Switched

Central Resource

DMA POM

Switched

Central Resource

Switched

Central Resource

EMAC OHCI

RM46L852

www.ti.com

1.4 Functional Block Diagram

The block diagram reflects the 337BGA package. Some pins are multiplexed or not available in the 144QFP. Please see the Terminal functions table for details.

NOTE

SPNS185 –SEPTEMBER 2012

Figure 1-1. Functional Block Diagram

Submit Documentation Feedback

Page 6

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

Table 1-1. Device Comparison Table

Orderable Part # Part # Flash RAM EMAC USB Package

xRM46L852PGET RM46L852 1.25MB 192kB 10/100 Host + Device 144-Pin QFP

xRM46L852ZWTT RM46L852 1.25MB 192kB 10/100 Host + Device 337-Ball Grid Array

www.ti.com

Submit Documentation Feedback

Page 7

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

1 RM46L852 16/32-Bit RISC Flash Microcontroller . 1 4.11 Tightly-Coupled RAM Interface Module ............ 84

1.1 Features ............................................. 1 4.12 Parity Protection for Accesses to peripheral RAMs 84

1.2 Applications .......................................... 2 4.13 On-Chip SRAM Initialization and Testing ........... 86

1.3 Description ........................................... 3 4.14 External Memory Interface (EMIF) ................. 88

1.4 Functional Block Diagram ........................... 5 4.15 Vectored Interrupt Manager ........................ 95

2 Device Package and Terminal Functions .......... 8 4.16 DMA Controller ..................................... 99

2.1 PGE QFP Package Pinout (144-Pin) ................ 8 4.17 Real Time Interrupt Module ....................... 102

2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array) . 9 4.18 Error Signaling Module ............................ 104

2.3 Terminal Functions ................................. 10 4.19 Reset / Abort / Error Sources ..................... 108

3 Device Operating Conditions ....................... 46 4.20 Digital Windowed Watchdog ...................... 111

3.1 Absolute Maximum Ratings Over Operating Free-

Air Temperature Range, ............................ 46

3.2 Device Recommended Operating Conditions ...... 46

3.3 Switching Characteristics over Recommended

Operating Conditions for Clock Domains .......... 47

3.4 Wait States Required ............................... 47

3.5 Power Consumption Over Recommended

Operating Conditions ............................... 48

3.6 Input/Output Electrical Characteristics Over

Recommended Operating Conditions .............. 49

3.7 Output Buffer Drive Strengths ...................... 50

3.8 Input Timings ....................................... 51

3.9 Output Timings ..................................... 51

3.10 Low-EMI Output Buffers ............................ 53

4 System Information and Electrical Specifications

............................................................. 54

4.1 Device Power Domains ............................ 54

4.2 Voltage Monitor Characteristics .................... 54

4.3 Power Sequencing and Power On Reset .......... 56

4.4 Warm Reset (nRST) ................................ 58

4.5 ARM

4.6 Clocks .............................................. 62

4.7 Clock Monitoring .................................... 71

4.8 Glitch Filters ........................................ 73

4.9 Device Memory Map ................................ 74

4.10 Flash Memory ...................................... 81

Cortex-R4F™ CPU Information ............. 59

4.21 Debug Subsystem ................................. 112

5 Peripheral Information and Electrical

Specifications ......................................... 117

5.1 Enhanced Translator PWM Modules (ePWM) .... 117

5.2 Enhanced Capture Modules (eCAP) .............. 122

5.3 Enhanced Quadrature Encoder (eQEP) .......... 124

5.4 Multi-Buffered 12bit Analog-to-Digital Converter .. 126

5.5 General-Purpose Input/Output .................... 137

5.6 Enhanced High-End Timer (N2HET) .............. 138

5.7 Controller Area Network (DCAN) .................. 142

5.8 Local Interconnect Network Interface (LIN) ....... 143

5.9 Serial Communication Interface (SCI) ............ 144

5.10 Inter-Integrated Circuit (I2C) ...................... 145

5.11 Multi-Buffered / Standard Serial Peripheral Interface

..................................................... 148

5.12 Ethernet Media Access Controller ................ 160

5.13 Universal Serial Bus Controller ................... 164

6 Device and Documentation Support ............. 165

6.1 Device and Development-Support Tool

Nomenclature ..................................... 165

6.2 Community Resources ............................ 165

6.3 Device Identification ............................... 166

7 Mechanical Data ...................................... 167

7.1 Thermal Data ...................................... 167

7.2 Packaging Information ............................ 167

Submit Documentation Feedback

Page 8

PRODUCTPREVIEW

108

GIOA[1]

nTRST

109

144

110 111 112 113 114 115 116 117 118 119 120 121

AD1IN[10]/ AD2IN[10]

122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

2323

2727

107

106

105

104

103

102

101

100

GIOB[3]

GIOA[0]

MIBSPI3NCS[3]

MIBSPI3NCS[2]

N2HET1[11]

FLTP1

FLTP2

GIOA[2]

VCCIO

VSS

CAN3RX

CAN3TX

GIOA[5]

N2HET1[22]

GIOA[6]

VCC

OSCIN

Kelvin_GND

OSCOUT

VSS

GIOA[7]

N2HET1[01]

N2HET1[03]

N2HET1[0]

VCCIO

VSS

VCC

N2HET1[02]

N2HET1[05]

MIBSPI5NCS[0]

N2HET1[07]

TEST

N2HET1[09]

N2HET1[4]

MIBSPI3NCS[1]

N2HET1[06]

N2HET1[13]

MIBSPI1NCS[2]

N2HET1[15]

VCCIO

VSS

VCC

nPORRST

VSS

VCC

VSS

MIBSPI3SOMI

MIBSPI3SIMO

MIBSPI3CLK

MIBSPI3NENA

MIBSPI3NCS[0]

VSS

VCC

AD1IN[16]/ AD2IN[0]

AD1IN[17]/ AD2IN[01]

AD1IN[0]

AD1IN[07]

AD1IN[18]/ AD2IN[02]

AD1IN[19]/ AD2IN[03]

AD1IN[20]/ AD2IN[04]

AD1IN[21]/ AD2IN[05]

ADREFHI

ADREFLO

VSSAD

VCCAD

AD1IN[09]/ AD2IN[09]

AD1IN[01]

AD1IN[02]

AD1IN[03]

AD1IN[11]/ AD2IN[11]

AD1IN[04]

AD1IN[12]/ AD2IN[12]

AD1IN[05]

AD1IN[13]/ AD2IN[13]

AD1IN[06]

AD1IN[22]/ AD2IN[06]

AD1IN[14]/ AD2IN[14]

AD1IN[08]/ AD2IN[08]

AD1IN[23]/ AD2IN[07]

AD1IN[15]/ AD2IN[15]

AD1EVT

VCC

VSS

CAN1TX

CAN1RX

N2HET1[24]

N2HET1[26]

MIBSPI1SIMO

MIBSPI1SOMI

MIBSPI1CLK

MIBSPI1NENA

MIBSPI5NENA

MIBSPI5SOMI[0]

MIBSPI5SIMO[0]

MIBSPI5CLK

VCC

VSS

VCCIO

N2HET1[08]

N2HET1[28]

TMS

TDI TDO TCK

RTCK

VCC

VSS

nRST

nERROR

N2HET1[10]

ECLK

VCCIO

VSS VSS

VCC N2HET1[12] N2HET1[14]

GIOB[0]

N2HET1[30]

CAN2TX

CAN2RX

MIBSPI1NCS[1]

LINRX LINTX

GIOB[1]

VCCP

VSS

VCCIO

VCC

VSS N2HET1[16] N2HET1[18] N2HET1[20]

GIOB[2]

VCC

VSS

MIBSPI1NCS[0]

RM46L852

SPNS185 –SEPTEMBER 2012

2 Device Package and Terminal Functions

2.1 PGE QFP Package Pinout (144-Pin)

www.ti.com

Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.

Figure 2-1. PGE QFP Package Pinout (144-Pin)

Submit Documentation Feedback

Page 9

PRODUCTPREVIEW

ABCDEFGHJKLMNPRTUVW

VSS

TMS

N2HET1

[10]

MIBSPI5

NCS[0]

MIBSPI1

SIMO

MIBSPI1

NENA

MIBSPI5

CLK

MIBSPI5 SIMO[0]

N2HET1

[28]

CAN3RX

AD1EVT

AD1IN[15]

AD2IN[15]

AD1IN[22]

AD2IN[06]

AD1IN

[06]

AD1IN[11]

AD2IN[11]

VSSAD

VSS

TCK

TDO

nTRST

N2HET1

[08]

MIBSPI1

CLK

MIBSPI1

SOMI

MIBSPI5

NENA

MIBSPI5

SOMI[0]

N2HET1

[0]

CAN3TX

AD1IN[08]

AD2IN[08]

AD1IN[14]

AD2IN[14]

AD1IN[13]

AD2IN[13]

AD1IN

[04]

AD1IN

[02]

VSSAD

1817TDI

nRST

EMIF_

nWE

MIBSPI5

SOMI[1]

MIBSPI5

SIMO[3]

MIBSPI5

SIMO[2]

N2HET1

[31]

EMIF_

nCS[3]

EMIF_

nCS[2]

EMIF_

nCS[4]

EMIF_

nCS[0]

AD1IN

[05]

AD1IN

[03]

AD1IN[10]

AD2IN[10]

AD1IN

[01]

AD1IN[09]

AD2IN[09]

RTCKNCNC

EMIF_ BA[1]

MIBSPI5

SIMO[1]

MIBSPI5

SOMI[3]

MIBSPI5

SOMI[2]

NCNCNCNCNC

AD1IN[23]

AD2IN[07]

AD1IN[12]

AD2IN[12]

AD1IN[19]

AD2IN[03]

ADREFLO

VSSAD

15NCNCNCNCNCNCNCNC

EMIF_

DATA[0]

EMIF_

DATA[1]

EMIF_

DATA[2]

EMIF_

DATA[3]

AD1IN[21]

AD2IN[05]

AD1IN[20]

AD2IN[04]

ADREFHI

VCCAD

N2HET1

[26]

nERRORNCNCNCVCCIO

VCCIO

VCC

VCCIO

VCCIONCNC

AD1IN[18]

AD2IN[02]

AD1IN

[07]

AD1IN

[0]

N2HET1

[17]

N2HET1

[19]

EMIF_BA[0]

VCCIO

VCCIONCNC

AD1IN[17]

AD2IN[01]

AD1IN[16]

AD2IN[0]

ECLK

N2HET1

[04]

EMIF_nOE

VCCIO

VSS

VCC

VSS

VCCIO

MIBSPI5

NCS[3]

NCNCNC

N2HET1

[14]

N2HET1

[30]

EMIF_

nDQM[1]

VCCIO

VSS

VCCPLLNCNCNCNCNC11

CAN1TX

CAN1RX

EMIF_

ADDR[12]

EMIF_

nDQM[0]

VCC

VSS

VCC

VCCNCNC

MIBSPI3

NCS[0]

GIOB[3]

N2HET1

[27]

EMIF_

ADDR[11]

EMIF_

ADDR[5]

VCC

VSS

VCCIO

EXTCLKI

MIBSPI3

CLK

MIBSPI3

NENA

98NC

EMIF_

ADDR[10]

EMIF_

ADDR[4]

VCCP

VSS

VCC

VSS

VCCIO

EMIF_

DATA[15]

MIBSPI3

SOMI

MIBSPI3

SIMO

87LINRX

LINTX

EMIF_

ADDR[9]

EMIF_

ADDR[3]

VCCIO

EMIF_

DATA[14]

N2HET1

[09]

nPORRST

76GIOA[4]

MIBSPI5

NCS[1]

EMIF_

ADDR[8]

EMIF_

ADDR[2]

VCCIO

VCC

VCCIO

EMIF_

DATA[13]

N2HET1

[05]

MIBSPI5

NCS[2]

65GIOA[0]

GIOA[5]

EMIF_

ADDR[7]

EMIF_

ADDR[1]

EMIF_

DATA[4]

EMIF_

DATA[5]

EMIF_

DATA[6]

FLTP2

FLTP1

EMIF_

DATA[7]

EMIF_

DATA[8]

EMIF_

DATA[9]

EMIF_

DATA[10]

EMIF_

DATA[11]

EMIF_

DATA[12]

MIBSPI3

NCS[1]

N2HET1

[02]

N2HET1

[16]

N2HET1

[12]

EMIF_

ADDR[6]

EMIF_

ADDR[0]

NCNCNC

N2HET1

[21]

N2HET1

[23]

NCNCNCNCNC

EMIF_ nCAS

NCNCNCNC4

N2HET1

[29]

N2HET1

[22]

MIBSPI3

NCS[3]

SPI2

NENA

N2HET1

[11]

MIBSPI1

NCS[1]

MIBSPI1

NCS[2]

GIOA[6]

MIBSPI1

NCS[3]

EMIF_

CLK

EMIF_

CKE

N2HET1

[25]

SPI2

NCS[0]

EMIF_

nWAIT

EMIF_ nRAS

NCNCNC

N2HET1

[06]

VSS

MIBSPI3

NCS[2]

GIOA[1]

SPI2

SOMI

SPI2CLK

GIOB[2]

GIOB[5]

CAN2TX

GIOB[6]

GIOB[1]

KELVIN_

GND

GIOB[0]

N2HET1

[13]

N2HET1

[20]

MIBSPI1

NCS[0]

TEST

N2HET1

[01]

VSS

GIOA[2]

SPI2

SIMO

GIOA[3]

GIOB[7]

GIOB[4]

CAN2RX

N2HET1

[18]

OSCIN

OSCOUT

GIOA[7]

N2HET1

[15]

N2HET1

[24]

N2HET1

[07]

N2HET1

[03]

VSS

ABCDEFGHJKLMNPRTUVW

RM46L852

www.ti.com

2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)

SPNS185 –SEPTEMBER 2012

Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.

Figure 2-2. ZWT Package Pinout. Top View

Submit Documentation Feedback

Page 10

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3 Terminal Functions

Section 2.3.1 and Section 2.3.2 identify the external signal names, the associated pin/ball numbers along

with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GIO, and a functional pin/ball description. The first signal name listed is the primary function for that terminal. The signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) User Guide for information on how to select between different multiplexed functions.

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High.

All output-only signals are configured as inputs while nPORRST is low, and are configured as outputs immediately after nPORRST goes High.

While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.

2.3.1 PGE Package

2.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

www.ti.com

Table 2-1. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)

ADREFHI

ADREFLO VCCAD VSSAD AD1EVT/MII_RX_ER/RMII_RX_ER 86 Input Pull Down Programmable, ADC1 event trigger input,

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ 55 I/O Pull Up Programmable, ADC2 event trigger input, EQEP1I/N2HET2_PIN_nDIS 20uA or GIO

AD1IN[0] 60 Input - - ADC1 analog input AD1IN[01] 71 AD1IN[02] 73 AD1IN[03] 74 AD1IN[04] 76 AD1IN[05] 78 AD1IN[06] 80 AD1IN[07] 61

(1)

(1) (1) (1)

Terminal Signal Default Pull Type Description

Signal Name 144

Type Pull State

PGE

66 Power - - ADC high reference

supply 67 Power ADC low reference supply 69 Power Operating supply for ADC 68 Ground

20uA or GIO

Submit Documentation Feedback

Page 11

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-1. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

AD1IN[08] / AD2IN[08] 83 Input - - ADC1/ADC2 shared AD1IN[09] / AD2IN[09] 70 AD1IN[10] / AD2IN[10] 72 AD1IN[11] / AD2IN[11] 75 AD1IN[12] / AD2IN[12] 77 AD1IN[13] / AD2IN[13] 79 AD1IN[14] / AD2IN[14] 82 AD1IN[15] / AD2IN[15] 85 AD1IN[16] / AD2IN[0] 58 AD1IN[17] / AD2IN[01] 59 AD1IN[18] / AD2IN[02] 62 AD1IN[19] / AD2IN[03] 63 AD1IN[20] / AD2IN[04] 64 AD1IN[21] / AD2IN[05] 65 AD1IN[22] / AD2IN[06] 81 AD1IN[23] / AD2IN[07] 84

MIBSPI3SOMI/AWM1_EXT_ENA/ECAP2 51 Output Pull Up - AWM1 external analog

MIBSPI3SIMO/AWM1_EXT_SEL[0]/ECAP3 52 Output Pull Up - AWM1 external analog

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Output Pull Up - AWM1 external analog

Type Pull State

analog inputs

mux enable

mux select line0

Submit Documentation Feedback

Page 12

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.1.2 Enhanced High-End Timer Modules (N2HET) Table 2-2. PGE Enhanced High-End Timer Modules (N2HET)

Terminal Signal Default Pull Pull Type Description

Signal Name 144

N2HET1[0]/SPI4CLK/EPWM2B 25 I/O Pull Down Programmable, N2HET1[01]/SPI4NENA/USB2.TXEN/ 23

USB_FUNC.PUENO/N2HET2[8]/EQEP2A

N2HET1[02]/SPI4SIMO/EPWM3A 30 N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24

USB_FUNC.PUENON/N2HET2[10]/EQEP2B

N2HET1[04]/EPWM4B 36 N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B 31 N2HET1[06]/SCIRX/EPWM5A 38 N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/ 33

N2HET2[14]/EPWM7B N2HET1[08]/MIBSPI1SIMO[1]/ 106

USB1.OverCurrent N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35

USB_FUNC.SUSPENDO/EPWM7A N2HET1[10]/MII_TX_CLK/USB1.TXEN 118

/MII_TX_AVCLK4/nTZ3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6

USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO

N2HET1[12]/MII_CRS/RMII_CRS_DV 124 N2HET1[13]/SCITX/EPWM5B 39 N2HET1[14]/USB1.TXSE0 125 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139

MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ 130 Pull Up USB1.SUSPEND/EQEP1S

N2HET1[18]/EPWM6A 140 Pull Down MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 Pull Up

N2HET1[20]/EPWM6B 141 Pull Down N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O 15

MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 Pull Up USB1.VP/ECAP4

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 Pull Down MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pull Up N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 Pull Down MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 Pull Up N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 107 Pull Down MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 Pull Up N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S 127 Pull Down MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 Pull Up GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 Pull Down

PGE

Type State

20uA

www.ti.com

N2HET1 time input capture or output compare, or GIO.

Each terminal has a suppression filter that ignores input pulses smaller than a programmable duration.

Submit Documentation Feedback

Page 13

PRODUCTPREVIEW

RM46L852

www.ti.com

Table 2-2. PGE Enhanced High-End Timer Modules (N2HET) (continued)

Terminal Signal Default Pull Pull Type Description

Signal Name 144

PGE

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQE 9 I/O Pull Down Programmable, P2I 20uA

GIOA[6]/N2HET2[4]/EPWM1B 16 GIOA[7]/N2HET2[6]EPWM2A 22 N2HET1[01]/SPI4NENA/USB2.TXEN/ 23

USB_FUNC.PUENO//N2HET2[8] N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24

USB_FUNC.PUENON/N2HET2[10]/EQEP2B N2HET1[05]/SPI4SOMI/N2HET2[12] 31 N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/ 33

N2HET2[14]/EPWM7B N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35

USB_FUNC.SUSPENDO N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6

USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_n 55 Pull Up

DIS

Type State

2.3.1.3 Enhanced Capture Modules (eCAP)

SPNS185 –SEPTEMBER 2012

N2HET2 time input capture or output compare, or GIO

Each terminal has a suppression filter that ignores input pulses smaller than a programmable duration.

Table 2-3. PGE Enhanced Capture Modules (eCAP)

Terminal Signal Default Pull Type Description

Signal Name 144

NHET1[15]/MIBSPI1NCS[4]/ECAP1 41 I/O Pull Down Fixed, 20uA Enhanced Capture

MIBSPI3SOMI/AWM1_EXT_ENA/ECAP2 51 Pull Up Enhanced Capture

MIBSPI3SIMO/AWM1_EXT_SEL[0]/ECAP3 52 Enhanced Capture

MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 Enhanced Capture USB1.VP/ECAP4 Module 4 I/O

MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA 97 Enhanced Capture P5 Module 5 I/O

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 Enhanced Capture USB1.RCV/ECAP6 Module 6 I/O

(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

(1)

Type Pull State

PGE

Module 1 I/O

Module 2 I/O

Module 3 I/O

Submit Documentation Feedback

Page 14

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

2.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 2-4. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Input Pull Up Fixed, 20uA Enhanced QEP1 Input A MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Input Enhanced QEP1 Input B MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDI 55 I/O Enhanced QEP1 Index

S MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 I/O Enhanced QEP1 Strobe

/USB1.SUSPEND /EQEP1S N2HET1[01]/SPI4NENA/USB2.TXEN/ 23 Input Pull Down Enhanced QEP2 Input A

USB_FUNC.PUENO/N2HET2[8]/EQEP2A N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24 Input Enhanced QEP2 Input B

USB_FUNC.PUENON/N2HET2[10]/EQEP2B GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP 9 I/O Enhanced QEP2 Index

N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S 127 I/O Enhanced QEP2 Strobe

(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

Type Pull State

(1)

Submit Documentation Feedback

Page 15

PRODUCTPREVIEW

RM46L852

www.ti.com

2.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 2-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM)

Terminal Signal Default Pull Type Description

Signal Name 144

GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 Output Pull Down - Enhanced PWM1 Output

GIOA[6]/N2HET2[4]/EPWM1B 16 Enhanced PWM1 Output

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 External ePWM Sync USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO Pulse Output

N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139 External ePWM Sync

GIOA[7]/N2HET2[6]/EPWM2A 22 Enhanced PWM2 Output

N2HET1[0]/SPI4CLK/EPWM2B 25 Enhanced PWM2 Output

N2HET1[02]/SPI4SIMO/EPWM3A 30 Enhanced PWM3 Output

N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B 31 Enhanced PWM3 Output

MIBSPI5NCS[0]/EPWM4A 32 Pull Up Enhanced PWM4 Output

N2HET1[04]/EPWM4B 36 Pull Down Enhanced PWM4 Output

N2HET1[06]/SCIRX/EPWM5A 38 Enhanced PWM5 Output

N2HET1[13]/SCITX/EPWM5B 39 Enhanced PWM5 Output

N2HET1[18]/EPWM6A 140 Enhanced PWM6 Output

N2HET1[20]/EPWM6B 141 Enhanced PWM6 Output

N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 Enhanced PWM7 Output USB_FUNC.SUSPENDO/EPWM7A A

N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/ 33 Enhanced PWM7 Output N2HET2[14]/EPWM7B B

MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 Input Pull Up Fixed, 20uA Trip Zone Inputs 1, 2 and MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 N2HET1[10]/MII_TX_CLK/USB1.TXEN 118 Pull Down

/MII_TX_AVCLK4/nTZ3

SPNS185 –SEPTEMBER 2012

Type Pull State

PGE

Pulse Output

3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or doublesynchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs.

Submit Documentation Feedback

Page 16

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

2.3.1.6 General-Purpose Input / Output (GIO)

Table 2-6. PGE General-Purpose Input / Output (GIO)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

GIOA[0]/USB2.VP/USB_FUNC.RXDPI 2 I/O Pull Down Programmable, General-purpose I/O. GIOA[1]/USB2.VM/USB_FUNC.RXDMI 5 GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP 9

2II

GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 GIOA[6]/N2HET2[4]/EPWM1B 16 GIOA[7]/N2HET2[6]/EPWM2A 22 GIOB[0]/USB1.TXDAT 126 GIOB[1]/USB1.PortPower 133 GIOB[2] 142

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD 55 IS

GIOB[3]USB2.RCV/USB_FUNC.RXDI 1 Pull Down

(1) GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt

whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pull up is enabled on the input. This is not programmable using the GIO module control registers.

Type Pull State

(1)

20uA All GIO terminals are

capable of generating interrupts to the CPU on rising / falling / both edges.

Pull Up

2.3.1.7 Controller Area Network Controllers (DCAN) Table 2-7. PGE Controller Area Network Controllers (DCAN)

Terminal Signal Default Pull Type Description

Signal Name 144

CAN1RX 90 I/O Pull Up Programmable, CAN1 receive, or GIO CAN1TX 89 CAN1 transmit, or GIO CAN2RX 129 CAN2 receive, or GIO CAN2TX 128 CAN2 transmit, or GIO CAN3RX 12 CAN3 receive, or GIO CAN3TX 13 CAN3 transmit, or GIO

2.3.1.8 Local Interconnect Network Interface Module (LIN)

Table 2-8. PGE Local Interconnect Network Interface Module (LIN)

Terminal Signal Default Pull Type Description

Signal Name 144

LINRX 131 I/O Pull Up Programmable, LIN receive, or GIO LINTX 132 LIN transmit, or GIO

Type Pull State

PGE

20uA

Type Pull State

PGE

20uA

Submit Documentation Feedback

Page 17

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

2.3.1.9 Standard Serial Communication Interface (SCI)

Table 2-9. PGE Standard Serial Communication Interface (SCI)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

N2HET1[06]/SCIRX/EPWM5A 38 I/O Pull Down Programmable, SCI receive, or GIO N2HET1[13]/SCITX/EPWM5B 39 SCI transmit, or GIO

Type Pull State

20uA

2.3.1.10 Inter-Integrated Circuit Interface Module (I2C)

Table 2-10. PGE Inter-Integrated Circuit Interface Module (I2C)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 I/O Pull Up Programmable, I2C serial data, or GIO MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 I2C serial clock, or GIO

Type Pull State

20uA

2.3.1.11 Standard Serial Peripheral Interface (SPI)

Table 2-11. PGE Standard Serial Peripheral Interface (SPI)

Terminal Signal Default Pull Type Description

Signal Name 144

N2HET1[0]/SPI4CLK/EPWM2B 25 I/O Pull Down Programmable, SPI4 clock, or GIO N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 SPI4 chip select, or GIO N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A 23 SPI4 enable, or GIO N2HET1[02]/SPI4SIMO/EPWM3A 30 SPI4 slave-input master-

N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B 31 SPI4 slave-output master-

Type Pull State

PGE

20uA

output, or GIO

input, or GIO

Submit Documentation Feedback

Page 18

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.1.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

Table 2-12. PGE Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

Terminal Signal Default Pull Type Description

Signal Name 144

MIBSPI1CLK 95 I/O Pull Up Programmable, MibSPI1 clock, or GIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 MibSPI1 chip select, or

USB1.RCV/ECAP6 GIO MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130

/USB1.SUSPEND /EQEP1S MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 Pull Down Programmable, MibSPI1 chip select, or N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 Pull Up Programmable, MibSPI1 enable, or GIO

USB1.VP/ECAP4 20uA MIBSPI1SIMO 93 MibSPI1 slave-in master-

N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ 106 Pull Down Programmable, MibSPI1 slave-in masterUSB1.OverCurrent 20uA out, or GIO

MIBSPI1SOMI 94 Pull Up Programmable, MibSPI1 slave-out master- MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105

USB1.RCV/ECAP6

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 I/O Pull Up Programmable, MibSPI3 clock, or GIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD 55 MibSPI3 chip select, or

IS GIO

MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 Pull Down Programmable, MibSPI3 chip select, or USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO 20uA GIO

MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pull Up Programmable, MibSPI3 chip select, or

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable, or GIO MIBSPI3SIMO/AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-in master-

MIBSPI3SOMI/AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-out master-

MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 I/O Pull Up Programmable, MibSPI5 clock, or GIO MIBSPI5NCS[0]/EPWM4A 32 MibSPI5 chip select, or

MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA 97 MibSPI5 enable, or GIO

MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MibSPI5 slave-in master-

MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MibSPI5 slave-out master-

MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA 97 MibSPI5 SOMI, or GIO P5

MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MibSPI5 SOMI, or GIO

www.ti.com

Type Pull State

PGE

20uA

20uA GIO

out, or GIO

20uA in, or GIO

20uA

20uA GIO

out, or GIO

in, or GIO

20uA

GIO

out, or GIO

in, or GIO

Submit Documentation Feedback

Page 19

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

2.3.1.13 Ethernet Controller

Table 2-13. PGE Ethernet Controller: MDIO Interface

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output Pull Up - Serial clock output MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pull Up Fixed, 20uA Serial data input/output

Type Pull State

Table 2-14. PGE Ethernet Controller: Reduced Media Independent Interface (RMII)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Input Pull Down Fixed, 20uA RMII carrier sense and

N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 107 RMII synchronous

AD1EVT/MII_RX_ER/RMII_RX_ER 86 RMII receive error N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 RMII receive data N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 Output Pull Up - RMII transmit data MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 RMII transmit enable

Type Pull State

data valid

reference clock for receive, transmit and control interface

Table 2-15. PGE Ethernet Controller: Media Independent Interface (MII)

Terminal Signal Default Pull Type Description

Signal Name 144

MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ 130 Input Pull Up - Collision detect USB1.SUSPEND/EQEP1S

N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Pull Down Fixed, 20uA Carrier sense and receive

N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Pull Down - MII output receive clock N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S/EQEP2S 127 Input Pull Down Fixed, 20uA Received data valid AD1EVT/MII_RX_ER/RMII_RX_ER 86 Receive error N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O Receive clock N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 Input Receive data N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 Pull Up Fixed, 20uA

USB1.VP/ECAP4 MIBSPI5NENA/MII_RXD[3]/USB1.VM/ECAP5/ECAP5 97 N2HET1[10]/MII_TX_CLK/USB1.TXEN/ 118 I/O Pull Down - MII output transmit clock

MII_TX_AVCLK4/nTZ3 N2HET1[10]/MII_TX_CLK/USB1.TXEN 118 Transmit clock

/MII_TX_AVCLK4/nTZ3

Type Pull State

PGE

valid

Submit Documentation Feedback

Page 20

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

Table 2-15. PGE Ethernet Controller: Media Independent Interface (MII) (continued)

Terminal Signal Default Pull Type Description

Signal Name 144

MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 Output Pull Up - Transmit data MIBSPI5SIMO[0]/MII_TXD[1] 99 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105

USB1.RCV/ECAP6 N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ 106 Pull Down -

USB1.OverCurrent MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 Pull Up - Transmit enable

2.3.1.14 USB Host Port Controller Interface

Table 2-16. PGE USB Host Port Controller Interface (USB1, USB2)

Terminal Signal Default Pull Type Description

Signal Name 144

N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Input Pull Down Fixed, 20uA Overcurrent indication /USB1.OverCurrent from USB power switch

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 Pull Up Fixed, 20uA Receive data from USB USB1.RCV/ECAP6 port transceiver

MIBSPI5NENA/MII_RXD[3]/USB1.VM 97 NRZI encoded D-minus

MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 NRZI encoded D-plus USB1.VP/ECAP4 from USB port transceiver

GIOB[1]/USB1.PortPower 133 Output Pull Down N2HET1[30]/MII_RX_DV/USB1.SPEED 127 Transmit speed indication MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ 130 Pull Up -

USB1.SUSPEND/EQEP1S GIOB[0]/USB1.TXDAT 126 Pull Down N2HET1[10]/MII_TX_CLK/USB1.TXEN 118 Transmit enable to port

/MII_TX_AVCLK4 transceiver N2HET1[14]/USB1.TXSE0 125 Single-ended zero to port

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 Input Pull Down Fixed, 20uA USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO

GIOB[3]/USB2.RCV/USB_FUNC.RXDI 1 Pull Down Fixed, 20uA GIOA[1]/USB2.VM/USB_FUNC.RXDMI 5 NRZI encoded D-minus

GIOA[0]/USB2.VP/USB_FUNC.RXDPI 2 NRZI encoded D-plus

N2HET1[07]/USB2.PortPower/ 33 Output Pull Down USB_FUNC.GZO/N2HET2[14]/EPWM7B

N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24 Transmit speed indication USB_FUNC.PUENON/N2HET2[10]

N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 Port suspend indication USB_FUNC.SUSPENDO

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP 9 NRZI encoded D-plus to 2I port transceiver

N2HET1[01]/SPI4NENA/USB2.TXEN/ 23 Transmit enable to port USB_FUNC.PUENO/N2HET2[8] transceiver

N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O 15 Single-ended zero to port

www.ti.com

Type Pull State

PGE

Type Pull State

PGE

from USB port transceiver

transceiver

from USB port transceiver

transceiver

Submit Documentation Feedback

Page 21

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-17. PGE USB Device Port Controller Interface (USB_FUNC)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/N2HET2[14] 33 Output Pull Down - Pull Up enable, allows for

N2HET1[01]/SPI4NENA/USB2.TXEN/USB_FUNC.PUENO/ 23 PUENO inverted N2HET2[8]

N2HET1[03]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENO 24 N/ N2HET2[10]/EQEP2B

GIOB[3]/USB2.RCV/USB_FUNC.RXDI 1 Input Pull Down Fixed, 20uA USB device single-ended

GIOA[1]/USB2.VM/USB_FUNC.RXDMI 5 USB device logic value of

GIOA[0]/USB2.VP/USB_FUNC.RXDPI 2 USB device logic value of

N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O 15 Output Pull Down - USB device single-ended

N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 USB device suspend USB_FUNC.SUSPENDO output

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0] 9 USB device transmit data N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 Input Pull Down Fixed, 20uA USB device power

USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO connected

Type Pull State

software-programmable USB device connect/disconnect

data input

D-minus

D-plus

zero

2.3.1.15 System Module Interface

Terminal Signal Default Pull Type Description

Signal Name 144

nPORRST 46 Input Pull Down 100uA Power-on reset, cold reset

nRST 116 I/O Pull Up 100uA System reset, warm reset,

Table 2-18. PGE System Module Interface

Type Pull State

PGE

External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of thespecified range. This terminal has a glitch filter. See Section 4.8.

bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pull-up resistor is connected to this terminal. This terminal has a glitch filter. See Section 4.8.

Submit Documentation Feedback

Page 22

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

Table 2-18. PGE System Module Interface (continued)

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

nERROR 117 I/O Pull Down 20uA ESM Error Signal

Type Pull State

Indicates error of high severity. See

Section 4.18.

2.3.1.16 Clock Inputs and Outputs

Table 2-19. PGE Clock Inputs and Outputs

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

OSCIN 18 Input - - From external

KELVIN_GND 19 Input Kelvin ground for oscillator OSCOUT 20 Output To external

ECLK 119 I/O Pull Down Programmable, External prescaled clock

GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS 14 Input Pull Down 20uA External clock input #1

Type Pull State

crystal/resonator, or external clock input

crystal/resonator

20uA output, or GIO.

2.3.1.17 Test and Debug Modules Interface

Terminal Signal Default Pull Type Description

Signal Name 144

TEST 34 Input Pull Down Fixed, 100uA Test enable nTRST 109 Input JTAG test hardware reset RTCK 113 Output - - JTAG return test clock TCK 112 Input Pull Down Fixed, 100uA JTAG test clock TDI 110 Input Pull Up JTAG test data in TDO 111 Output Pull Down JTAG test data out TMS 108 Input Pull Up JTAG test select

2.3.1.18 Flash Supply and Test Pads

Terminal Signal Default Pull Type Description

Signal Name 144

VCCP 134 3.3V - - Flash pump supply

FLTP1 7 - - - Flash test pads. These FLTP2 8

Table 2-20. PGE Test and Debug Modules Interface

Type Pull State

PGE

Table 2-21. PGE Flash Supply and Test Pads

Type Pull State

PGE

Power

terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].

Submit Documentation Feedback

Page 23

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

2.3.1.19 Supply for Core Logic: 1.2V nominal

Table 2-22. PGE Supply for Core Logic: 1.2V nominal

Terminal Signal Default Pull Type Description

Signal Name 144

PGE

VCC 17 1.2V - - Core supply VCC 29 VCC 45 VCC 48 VCC 49 VCC 57 VCC 87 VCC 101 VCC 114 VCC 123 VCC 137 VCC 143

Type Pull State

Power

2.3.1.20 Supply for I/O Cells: 3.3V nominal

Terminal Signal Default Pull Type Description

Signal Name 144

VCCIO 10 3.3V - - Operating supply for I/Os VCCIO 26 VCCIO 42 VCCIO 104 VCCIO 120 VCCIO 136

Table 2-23. PGE Supply for I/O Cells: 3.3V nominal

Type Pull State

PGE

Power

Submit Documentation Feedback

Page 24

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.1.21 Ground Reference for All Supplies Except VCCAD

Table 2-24. PGE Ground Reference for All Supplies Except VCCAD

Terminal Signal Default Pull Type Description

Signal Name 144

VSS 11 Ground - - Ground reference VSS 21 VSS 27 VSS 28 VSS 43 VSS 44 VSS 47 VSS 50 VSS 56 VSS 88 VSS 102 VSS 103 VSS 115 VSS 121 VSS 122 VSS 135 VSS 138 VSS 144

www.ti.com

Type Pull State

PGE

Submit Documentation Feedback

Page 25

PRODUCTPREVIEW

RM46L852

www.ti.com

2.3.2 ZWT Package

2.3.2.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

Table 2-25. ZWT Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal Signal Default Pull Type Description

Signal Name 337

ADREFHI

ADREFLO VCCAD VSSAD V19 Ground - - ADC supply power

AD1EVT/MII_RX_ER/RMII_RX_ER N19 Input Pull Down Programmable, ADC1 event trigger input,

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 I/O Pull Up Programmable, ADC2 event trigger input, IS 20uA or GIO

AD1IN[0] W14 Input - - ADC1 analog input AD1IN[01] V17 AD1IN[02] V18 AD1IN[03] T17 AD1IN[04] U18 AD1IN[05] R17 AD1IN[06] T19 AD1IN[07] V14 AD1IN[08] / AD2IN[08] P18 Input - - ADC1/ADC2 shared AD1IN[09] / AD2IN[09] W17 AD1IN[10] / AD2IN[10] U17 AD1IN[11] / AD2IN[11] U19 AD1IN[12] / AD2IN[12] T16 AD1IN[13] / AD2IN[13] T18 AD1IN[14] / AD2IN[14] R18 AD1IN[15] / AD2IN[15] P19 AD1IN[16] / AD2IN[0] V13 AD1IN[17] / AD2IN[01] U13 AD1IN[18] / AD2IN[02] U14 AD1IN[19] / AD2IN[03] U16 AD1IN[20] / AD2IN[04] U15 AD1IN[21] / AD2IN[05] T15 AD1IN[22] / AD2IN[06] R19 AD1IN[23] / AD2IN[07] R16

MIBSPI3SOMI/AWM1_EXT_ENA/ECAP2 V8 Output Pull Up - AWM1 external analog

MIBSPI3SIMO/AWM1_EXT_SEL[0]/ECAP3 W8 AWM1 external analog

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 AWM1 external analog

(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

(1)

SPNS185 –SEPTEMBER 2012

Type Pull State

ZWT

V15 Power - - ADC high reference

supply

V16 Power ADC low reference supply

W15 Power Operating supply for ADC

W16 W18 W19

20uA or GIO

analog inputs

mux enable

mux select line0

Submit Documentation Feedback

Page 26

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.2 Enhanced High-End Timer Modules (N2HET)

Table 2-26. ZWT Enhanced High-End Timer Modules (N2HET)

Terminal Signal Default Pull Type Description

Signal Name 337

N2HET1[0]/SPI4CLK/EPWM2B K18 I/O Pull Down Programmable, N2HET1[01]/SPI4NENA/N2HET2[8] V2 N2HET1[02]/SPI4SIMO/EPWM3A W5 N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1

USB_FUNC.PUENON/N2HET2[10]/EQEP2B

N2HET1[04]/EPWM4B B12 N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 programmable duration. N2HET1[06]/SCIRX/EPWM5A W3 N2HET1[07]/EPWM7B/USB2.PortPower/ T1

USB_FUNC.GZO/N2HET2[14]/EPWM7B N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ E18

USB1.OverCurrent N2HET1[09]/N2HET2[16]/ V7

USB2.SUSPEND/USB_FUNC.SUSPENDO/EPWM7A N2HET1[10]/MII_TX_CLK/ D19

USB1.TXEN/MII_TX_AVCLK4/nTZ3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3

USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO

N2HET1[12]/MII_CRS/RMII_CRS_DV B4 N2HET1[13]/SCITX/EPWM5B N2 N2HET1[14]/USB1.TXSE0 A11 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4 N2HET1[17] A13 N2HET1[18]/EPWM6A J1 N2HET1[19] B13 N2HET1[20]/EPWM6B P2 N2HET1[21] H4 N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O B3 N2HET1[23] J4 N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 N2HET1[25] M3 N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 N2HET1[27] A9 N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 N2HET1[29] A3 N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S B11 N2HET1[31] J17 GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 input Pull Down Fixed, 20uA

ZWT

Type Pull State

20uA

www.ti.com

N2HET1 time input capture or output compare, or GIO.

Each terminal has a suppression filter that ignores input pulses smaller than a

Submit Documentation Feedback

Page 27

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-26. ZWT Enhanced High-End Timer Modules (N2HET) (continued)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP C1 I/O Pull Down Programmable, 2I 20uA

EMIF_ADDR[0]/N2HET2[1] D4 GIOA[3]/N2HET2[2] E1 EMIF_ADDR[1]/N2HET2[3] D5 GIOA[6]/N2HET2[4]/EPWM1B H3 EMIF_BA[1]/N2HET2[5] D16 programmable duration. GIOA[7]/N2HET2[6]/EPWM2A M1 EMIF_nCS[0]/N2HET2[7] N17 N2HET1[01]/SPI4NENA/USB2.TXEN/ V2

USB_FUNC.PUENO/N2HET2[8] EMIF_nCS[3]/N2HET2[9] K17 N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1

USB_FUNC.PUENON/N2HET2[10]/EQEP2B EMIF_ADDR[6]/N2HET2[11] C4 N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 EMIF_ADDR[7]/N2HET2[13] C5 N2HET1[07]/USB2.PortPower/ T1

USB_FUNC.GZO/N2HET2[14]/EPWM7B EMIF_ADDR[8]/N2HET2[15] C6 N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ V7

USB_FUNC.SUSPENDO/EPWM7A N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3

USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 Pull Up

Type Pull State

N2HET2 time input capture or output compare, or GIO.

Each terminal has a suppression filter that ignores input pulses smaller than a

2.3.2.3 Enhanced Capture Modules (eCAP)

Table 2-27. ZWT Enhanced Capture Modules (eCAP)

Terminal Signal Default Pull Type Description

Signal Name 337

N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 I/O Pull Down Fixed, 20uA Enhanced Capture

MIBSPI3SOMI/AWM1_EXT_ENA/ECAP2 V8 std Pull Up Enhanced Capture

MIBSPI3SIMO/AWM1_EXT_SEL[0]/ECAP3 W8 std Enhanced Capture

MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/USB1.VP/ECAP4 G19 std Enhanced Capture

MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA H18 std Enhanced Capture P5 buffer Module 5 I/O

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/USB1.RCV/EC R2 std Enhanced Capture AP6 buffer Module 6 I/O

(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

(1)

Type Pull State

ZWT

Module 1 I/O

buffer Module 2 I/O

buffer Module 3 I/O

buffer Module 4 I/O

Submit Documentation Feedback

Page 28

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

2.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 2-28. ZWT Enhanced Quadrature Encoder Pulse Modules (eQEP)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 Input Pull Up Fixed, 20uA Enhanced QEP1 Input A MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Input Enhanced QEP1 Input B MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDI V10 I/O Enhanced QEP1 Index

S MIBSPI1NCS[1]/N2HET1[17]/MII_COL/USB1.SUSPEND/EQ F3 I/O Enhanced QEP1 Strobe

EP1S

N2HET1[01]/SPI4NENA/USB2.TXEN/USB_FUNC.PUENO/N V2 Input Pull Down Enhanced QEP2 Input A 2HET2[8]/EQEP2A

N2HET1[03]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENO U1 Input Pull Down Enhanced QEP2 Input B N/N2HET2[10]/EQEP2B

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP C1 I/O Pull Down Enhanced QEP2 Index

N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S B11 I/O Pull Down Enhanced QEP2 Strobe

(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

Type Pull State

(1)

Submit Documentation Feedback

Page 29

PRODUCTPREVIEW

RM46L852

www.ti.com

2.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 2-29. ZWT Enhanced Pulse-Width Modulator Modules (ePWM)

Terminal Signal Default Pull Type Description

Signal Name 337

GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 Output Pull Down - Enhanced PWM1 Output

GIOA[6]/N2HET2[4]/EPWM1B H3 Enhanced PWM1 Output

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/USB2.OverCurrent E3 External ePWM Sync /USB_FUNC.VBUSI/EPWM1SYNCO Pulse Output

N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4 External ePWM Sync

GIOA[7]/N2HET2[6]/EPWM2A M1 Enhanced PWM2 Output

N2HET1[0]/SPI4CLK/EPWM2B K18 Enhanced PWM2 Output

N2HET1[02]/SPI4SIMO/EPWM3A W5 Enhanced PWM3 Output

N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 Enhanced PWM3 Output

MIBSPI5NCS[0]/EPWM4A E19 Pull Up Enhanced PWM4 Output

N2HET1[04]/EPWM4B B12 Pull Down Enhanced PWM4 Output

N2HET1[06]/SCIRX/EPWM5A W3 Enhanced PWM5 Output

N2HET1[13]/SCITX/EPWM5B N2 Enhanced PWM5 Output

N2HET1[18]/EPWM6A J1 Enhanced PWM6 Output

N2HET1[20]/EPWM6B P2 Enhanced PWM6 Output

N2HET1[09]/N2HET2[16]/USB2.SUSPEND/USB_FUNC.SUS V7 Enhanced PWM7 Output PENDO/EPWM7A A

N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/N2HET2[14]/ T1 Enhanced PWM7 Output EPWM7B B

MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 Input Pull Up Fixed, 20uA Trip Zone Inputs 1, 2 and MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 N2HET1[10]/MII_TX_CLK/USB1.TXEN//MII_TX_AVCLK4/nT D19 Pull Down

SPNS185 –SEPTEMBER 2012

Type Pull State

ZWT

Pulse Output

3These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or doublesynchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs.

Submit Documentation Feedback

Page 30

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.6 General-Purpose Input / Output (GIO)

Terminal Signal Default Pull Type Description

Signal Name 337

GIOA[0]/USB2.VP/USB_FUNC.RXDPI A5 I/O Pull Down Programmable, General-purpose I/O. GIOA[1]/USB2.VM/USB_FUNC.RXDMI C2 GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0] C1

/EQEP2I

GIOA[3]/N2HET2[2] E1 GIOA[4] A6 GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 GIOA[6]/N2HET2[4]/EPWM1B H3 GIOA[7]/N2HET2[6]/EPWM2A M1 GIOB[0]/USB1.TXDAT M2 GIOB[1]/USB1.PortPower K2 GIOB[2] F2 /

GIOB[3]/USB2.RCV W10 GIOB[4] G1 GIOB[5] G2 GIOB[6] J2 GIOB[7] F1

(1) GIOB[2] cannot output a level on to terminal V10. Only the input functionality is supported so that the application can generate an

interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pull up is enabled on the input. This is not programmable using the GIO module control registers.

Table 2-30. ZWT General-Purpose Input / Output (GIO)

Type Pull State

ZWT

20uA All GIO terminals are

(1)

V10

www.ti.com

capable of generating interrupts to the CPU on rising / falling / both edges.

Submit Documentation Feedback

Page 31

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

2.3.2.7 Controller Area Network Controllers (DCAN)

Table 2-31. ZWT Controller Area Network Controllers (DCAN)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

CAN1RX B10 I/O Pull Up Programmable, CAN1 receive, or GIO CAN1TX A10 CAN1 transmit, or GIO CAN2RX H1 CAN2 receive, or GIO CAN2TX H2 CAN2 transmit, or GIO CAN3RX M19 CAN3 receive, or GIO CAN3TX M18 CAN3 transmit, or GIO

Type Pull State

20uA

2.3.2.8 Local Interconnect Network Interface Module (LIN)

Table 2-32. ZWT Local Interconnect Network Interface Module (LIN)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

LINRX A7 I/O Pull Up Programmable, LIN receive, or GIO LINTX B7 LIN transmit, or GIO

Type Pull State

20uA

2.3.2.9 Standard Serial Communication Interface (SCI)

Table 2-33. ZWT Standard Serial Communication Interface (SCI)

Terminal Signal Default Pull Type Description

Signal Name 337

N2HET1[06]/SCIRX/EPWM5A W3 I/O Pull Down Programmable, SCI receive, or GIO N2HET1[13]/SCITX/EPWM5B N2 SCI transmit, or GIO

Type Pull State

ZWT

20uA

Submit Documentation Feedback

Page 32

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.10 Inter-Integrated Circuit Interface Module (I2C)

Table 2-34. ZWT Inter-Integrated Circuit Interface Module (I2C)

Terminal Signal Default Pull Type Description

Signal Name 337

MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 I/O Pull Up Programmable, I2C serial data, or GIO MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 I2C serial clock, or GIO

2.3.2.11 Standard Serial Peripheral Interface (SPI)

Table 2-35. ZWT Standard Serial Peripheral Interface (SPI)

Terminal Signal Default Pull Type Description

Signal Name 337

SPI2CLK E2 I/O Pull Up Programmable, SPI2 clock, or GIO SPI2NCS[0] N3 SPI2 chip select, or GIO SPI2NENA/SPI2NCS[1] D3 SPI2 chip select, or GIO SPI2NENA/SPI2NCS[1] D3 SPI2 enable, or GIO SPI2SIMO D1 SPI2 slave-input master-

SPI2SOMI D2 SPI2 slave-output master-

N2HET1[0]/SPI4CLK/EPWM2B K18 I/O Pull Down Programmable, SPI4 clock, or GIO N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1 SPI4 chip select, or GIO

USB_FUNC.PUENON/N2HET2[10]/EQEP2B N2HET1[01]/SPI4NENA/USB2.TXEN/ V2 SPI4 enable, or GIO

USB_FUNC.PUENO/N2HET2[8] N2HET1[02]/SPI4SIMO/EPWM3A W5 SPI4 slave-input master-

N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 SPI4 slave-output master-

www.ti.com

Type Pull State

ZWT

20uA

Type Pull State

ZWT

20uA

output, or GIO

input, or GIO

20uA

output, or GIO

input, or GIO

Submit Documentation Feedback

Page 33

PRODUCTPREVIEW

RM46L852

www.ti.com

2.3.2.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

Table 2-36. ZWT Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

Terminal Signal Default Pull Type Description

Signal Name 337

MIBSPI1CLK F18 I/O Pull Up Programmable, MibSPI1 clock, or GIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2 MibSPI1 chip select, or

USB1.RCV GIO MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ F3

USB1.SUSPEND /EQEP1S

MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 MIBSPI1NCS[3]/N2HET1[21] J3

N2HET1[15]/MIBSPI1NCS[4] N1 Pull Down Programmable, MibSPI1 chip select, or N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ G19 Pull Up Programmable, MibSPI1 enable, or GIO

USB1.VP/ECAP4 20uA MIBSPI1SIMO F19 MibSPI1 slave-in master-

N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/USB1.OverCurrent E18 Pull Down Programmable, MibSPI1 slave-in master-

MIBSPI1SOMI G18 Pull Up Programmable, MibSPI1 slave-out master- MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6/ R2

USB1.RCV

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 I/O Pull Up Programmable, MibSPI3 clock, or GIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 MibSPI3 chip select, or

IS GIO

MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 Pull Down Programmable, MibSPI3 chip select, or USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO 20uA GIO

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Pull Up Programmable, MibSPI3 chip select, or

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 MibSPI3 enable, or GIO MIBSPI3SIMO/AWM1_EXT_SEL[0]/ECAP3 W8 MibSPI3 slave-in master-

MIBSPI3SOMI/AWM1_EXT_ENA/ECAP2 V8 MibSPI3 slave-out master-

MIBSPI5CLK/MII_TXEN/RMII_TXEN H19 I/O Pull Up Programmable, MibSPI5 clock, or GIO MIBSPI5NCS[0]/EPWM4A E19 MibSPI5 chip select, or MIBSPI5NCS[1] B6 MIBSPI5NCS[2] W6 MIBSPI5NCS[3] T12 MIBSPI5NENAMII_RXD[3]/ H18 MibSPI5 enable, or GIO

USB1.VM/MIBSPI5SOMI[1]/ECAP5

MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] J19 MibSPI5 slave-in master- MIBSPI5SIMO[1] E16 MIBSPI5SIMO[2] H17 MIBSPI5SIMO[3] G17 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 MIBSPI5SOMI[1] E17 MIBSPI5SOMI[2] H16 MIBSPI5SOMI[3] G16

SPNS185 –SEPTEMBER 2012

Type Pull State

ZWT

20uA

20uA GIO

out, or GIO

20uA out, or GIO

20uA in, or GIO

20uA

20uA GIO

out, or GIO

in, or GIO

20uA

GIO

out, or GIO

Submit Documentation Feedback

Page 34

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.13 Ethernet Controller

Terminal Signal Default Pull Type Description

Signal Name 337

MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Output Pull Up - Serial clock output MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 I/O Pull Up Fixed, 20uA Serial data input/output

Table 2-38. ZWT Ethernet Controller: Reduced Media Independent Interface (RMII)

Terminal Signal Default Pull Type Description

Signal Name 337

N2HET1[12]/MII_CRS/RMII_CRS_DV B4 Input Pull Down Fixed, 20uA RMII carrier sense and

N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 RMII synchronous

AD1EVT/MII_RX_ER/RMII_RX_ER N19 RMII receive error N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 RMII receive data N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 Output Pull Up - RMII transmit data MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] J19 MIBSPI5CLK//MII_TXEN/RMII_TXEN H19 RMII transmit enable

www.ti.com

Table 2-37. ZWT Ethernet Controller: MDIO Interface

Type Pull State

ZWT

Type Pull State

ZWT

data valid

reference clock for receive, transmit and control interface

Table 2-39. ZWT Ethernet Controller: Media Independent Interface (MII)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ F3 Input Pull Up - Collision detect USB1.SUSPEND/EQEP1S

N2HET1[12]/MII_CRS/RMII_CRS_DV B4 Pull Down Fixed, 20uA Carrier sense and receive

N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 K19 I/O Pull Down - MII output receive clock N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S B11 Input Pull Down Fixed, 20uA Received data valid AD1EVT/MII_RX_ER/RMII_RX_ER N19 Receive error N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 I/O Receive clock N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 Input Receive data N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ G19 Pull Up Fixed, 20uA

USB1.VP/ECAP4 MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA H18

P5 N2HET1[10]/MII_TX_CLK/USB1.TXEN/ D19 I/O Pull Down - MII output transmit clock

MII_TX_AVCLK4/nTZ3 N2HET1[10]/MII_TX_CLK/USB1.TXEN D19 Transmit clock

/MII_TX_AVCLK4/nTZ3

Type Pull State

valid

Submit Documentation Feedback

Page 35

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-39. ZWT Ethernet Controller: Media Independent Interface (MII) (continued)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 Output Pull Up - Transmit data MIBSPI5SIMO[0]/MII_TXD[1] J19 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2

USB1.RCV N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ E18 Pull Down -

USB1.OverCurrent MIBSPI5CLK/MII_TXEN/RMII_TXEN H19 Pull Up - Transmit enable

Type Pull State

Submit Documentation Feedback

Page 36

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.14 USB Host Port Controller Interface

Table 2-40. ZWT USB Host Port Controller Interface (USB1, USB2)

Terminal Signal Default Pull Type Description

Signal Name 337

N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ E18 Input Pull Down Fixed, 20uA Overcurrent indication USB1.OverCurrent from USB power switch

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2 Pull Up Fixed, 20uA Receive data from USB USB1.RCV port transceiver

MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA H18 NRZI encoded D-minus P5 from USB port transceiver

MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ G19 NRZI encoded D-plus USB1.VP/ECAP4 from USB port transceiver

GIOB[1]/USB1.PortPower K2 Output Pull Down N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S B11 Transmit speed indication MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ F3 Pull Up -

USB1.SUSPEND/EQEP1S GIOB[0]/USB1.TXDAT M2 Pull Down N2HET1[10]/MII_TX_CLK/USB1.TXEN/ D19 Transmit enable to port

MII_TX_AVCLK4/nTZ3 transceiver N2HET1[14]/USB1.TXSE0 A11 Single-ended zero to port

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 Input Pull Down Fixed, 20uA USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO

GIOB[3]/USB2.RCV/USB_FUNC.RXDI W10 Pull Down Fixed, 20uA GIOA[1]/USB2.VM/USB_FUNC.RXDMI C2 NRZI encoded D-minus

GIOA[0]/USB2.VP/USB_FUNC.RXDPI A5 NRZI encoded D-plus

N2HET1[07]/USB2.PortPower/ T1 Output Pull Down USB_FUNC.GZO/N2HET2[14]/EPWM7B

N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1 Transmit speed indication USB_FUNC.PUENON/N2HET2[10]/EQEP2B

N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ V7 Port suspend indication USB_FUNC.SUSPENDO/EPWM7A

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP C1 NRZI encoded D-plus to 2I port transceiver

N2HET1[01]/SPI4NENA/USB2.TXEN\ V2 Transmit enable to port USB_FUNC.PUENO/N2HET2[8] transceiver

N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O B3 Single-ended zero to port

www.ti.com

Type Pull State

ZWT

transceiver

from USB port transceiver

transceiver

Table 2-41. ZWT USB Device Port Controller Interface (USB_FUNC)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/N2HET2[14]/ T1 Output Pull Down - Pull Up enable, allows for EPWM7B software-programmable

N2HET1[01]/SPI4NENA/USB2.TXEN/USB_FUNC.PUENO/ V2 PUENO inverted N2HET2[8]

N2HET1[03]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENO U1 N/ N2HET2[10]/EQEP2B

Submit Documentation Feedback

Type Pull State

USB device connect/disconnect

Page 37

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-41. ZWT USB Device Port Controller Interface (USB_FUNC) (continued)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

GIOB[3]/USB2.RCV/USB_FUNC.RXDI W10 Input Pull Down Fixed, 20uA USB device single-ended

GIOA[1]/USB2.VM/USB_FUNC.RXDMI C2 USB device logic value of

GIOA[0]/USB2.VP/USB_FUNC.RXDPI A5 USB device logic value of

N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O B3 Output Pull Down - USB device single-ended

N2HET1[09]/N2HET2[16]/USB2.SUSPEND/USB_FUNC.SUS V7 USB device suspend PENDO/EPWM7A output

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP C1 USB device transmit data 2I

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 Input Pull Down Fixed, 20uA USB device power USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO connected

Type Pull State

data input

D-minus

D-plus

zero

Submit Documentation Feedback

Page 38

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.15 External Memory Interface (EMIF)

Terminal Signal Default Pull Type Description

Signal Name 337

EMIF_CKE L3 Output Pull Down - EMIF Clock Enable EMIF_CLK K3 I/O EMIF clock. This is an

EMIF_nWE/EMIF_RNW D17 Output Pull Up - EMIF Read-Not-Write EMIF_nOE E12 Pull Down - EMIF Read Enable EMIF_nWAIT P3 I/O Pull Up Fixed, 20uA EMIF Extended Wait

EMIF_nWE/EMIF_RNW D17 Output Pull Up Programmable, EMIF Write Enable. EMIF_nCAS R4 Output EMIF column address

EMIF_nRAS R3 Output EMIF row address strobe EMIF_nCS[0]/N2HET2[7]

EMIF_nCS[2] L17 Output Pull Up EMIF chip selects, EMIF_nCS[3]/N2HET2[9] EMIF_nCS[4] M17 Output Pull Up EMIF_nDQM[0] E10 Output Pull Down Programmable, EMIF Data Mask or Write EMIF_nDQM[1] E11 Output

EMIF_BA[0] E13 Output EMIF bank address or

EMIF_BA[1]/N2HET2[5]

EMIF_ADDR[0]/N2HET2[1] EMIF_ADDR[1]/N2HET2[3] EMIF_ADDR[2] E6 Output EMIF_ADDR[3] E7 Output EMIF_ADDR[4] E8 Output EMIF_ADDR[5] E9 Output EMIF_ADDR[6]/NHET2[11] EMIF_ADDR[7]/NHET2[13] EMIF_ADDR[8]/NHET2[15] EMIF_ADDR[9] C7 Output EMIF_ADDR[10] C8 Output EMIF_ADDR[11] C9 Output EMIF_ADDR[12] C10 Output

(1)

(1) (1)

(1) (1) (1)

Table 2-42. External Memory Interface (EMIF)

Type Pull State

ZWT

N17 Output Pull Down EMIF chip select,

K17 Output Pull Down

D16 Output EMIF bank address or

D4 Output EMIF address D5 Output

C4 Output C5 Output C6 Output

www.ti.com

output signal in functional mode. It is gated off by default, so that the signal is tri-stated. PINMUX29[8] must be cleared to enable this output.

Signal

20uA

strobe

synchronous

asynchronous This applies to chip selects 2, 3 and 4

20uA Strobe.

Data mask for SDRAM devices, write strobe for connected asynchronous devices.

address line

(1) These signals are tri-stated and pulled down by default after power-up. Any application that requires the EMIF must set the bit 31 of the

system module general-purpose register GPREG1.

Submit Documentation Feedback

Page 39

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-42. External Memory Interface (EMIF) (continued)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

EMIF_DATA[0] K15 I/O Pull Up Fixed, 20uA EMIF Data EMIF_DATA[1] L15 I/O EMIF_DATA[2] M15 I/O EMIF_DATA[3] N15 I/O EMIF_DATA[4] E5 I/O EMIF_DATA[5] F5 I/O EMIF_DATA[6] G5 I/O EMIF_DATA[7] K5 I/O EMIF_DATA[8] L5 I/O EMIF_DATA[9] M5 I/O EMIF_DATA[10] N5 I/O EMIF_DATA[11] P5 I/O EMIF_DATA[12] R5 I/O EMIF_DATA[13] R6 I/O EMIF_DATA[14] R7 I/O EMIF_DATA[15] R8 I/O

Type Pull State

Submit Documentation Feedback

Page 40

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.16 System Module Interface

Terminal Signal Default Pull Type Description

Signal Name 337

nPORRST W7 Input Pull Down 100uA Power-on reset, cold reset

nRST B17 I/O Pull Up 100uA System reset, warm reset,

nERROR B14 I/O Pull Down 20uA ESM Error Signal

www.ti.com

Table 2-43. ZWT System Module Interface

Type Pull State

ZWT

External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of thespecified range. This terminal has a glitch filter. See Section 4.8.

Indicates error of high severity. See

Section 4.18.

2.3.2.17 Clock Inputs and Outputs

Table 2-44. ZWT Clock Inputs and Outputs

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

OSCIN K1 Input - - From external

KELVIN_GND L2 Input Kelvin ground for oscillator OSCOUT L1 Output To external

ECLK A12 I/O Pull Down Programmable, External prescaled clock

GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 Input Pull Down 20uA External clock input #1 EXTCLKIN2 R9 Input External clock input #2 VCCPLL P11 1.2V - Dedicated core supply for

Type Pull State

crystal/resonator, or external clock input

crystal/resonator

20uA output, or GIO.

Power PLL's

Submit Documentation Feedback

Page 41

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

2.3.2.18 Test and Debug Modules Interface

Table 2-45. ZWT Test and Debug Modules Interface

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

TEST U2 Input Pull Down Fixed, 100uA Test enable nTRST D18 Input JTAG test hardware reset RTCK A16 Output - - JTAG return test clock TCK B18 Input Pull Down Fixed, 100uA JTAG test clock TDI A17 Input Pull Up JTAG test data in TDO C18 Output Pull Down JTAG test data out TMS C19 Input Pull Up JTAG test select

Type Pull State

2.3.2.19 Flash Supply and Test Pads

Table 2-46. ZWT Flash Supply and Test Pads

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

VCCP F8 3.3V - - Flash pump supply

FLTP1 J5 - - - Flash test pads. These FLTP2 H5

Type Pull State

Power

terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].

2.3.2.20 No Connects

Terminal Signal Default Pull Type Description

Signal Name 337

NC A8 - - NC A15 - - NC B8 - - NC B9 - - NC B15 - - NC B16 - - -

Table 2-47. No Connects

Type Pull State

ZWT

Submit Documentation Feedback

Page 42

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

Terminal Signal Default Pull Type Description

Signal Name 337

NC C11 - - - No Connects. These balls NC C12 - - NC C13 - - NC C14 - - NC C15 - - NC C16 - - NC C17 - - NC D6 - - NC D7 - - NC D8 - - NC D9 - - NC D10 - - NC D11 - - NC D12 - - NC D13 - - NC D14 - - NC D15 - - NC E4 - - NC F4 - - NC F16 - - NC F17 - - NC G4 - - NC K4 - - NC K16 - - NC L4 - - NC L16 - - NC M4 - - NC M16 - - NC N4 - - NC N16 - - NC N18 - - NC P4 NC P15 - - NC P16 - - NC P17 - - NC R1 - - NC R10 - - NC R11 - - NC R12 - - NC R13 - - NC R14 - - NC R15 - - -

www.ti.com

Table 2-47. No Connects (continued)

Type Pull State

ZWT

are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.

Submit Documentation Feedback

Page 43

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 2-47. No Connects (continued)

Terminal Signal Default Pull Type Description

Signal Name 337

ZWT

NC T2 - - - No Connects. These balls NC T3 - - NC T4 - - NC T5 - - NC T6 - - NC T7 - - NC T8 - - NC T9 - - NC T10 - - NC T11 - - NC T13 - - NC T14 - - NC U3 - - NC U4 - - NC U5 - - NC U6 - - NC U7 - - NC U8 - - NC U9 - - NC U10 - - NC U11 - - NC U12 - - NC V3 - - NC V4 - - NC V11 - - NC V12 - - NC W4 - - NC W13 - - -

Type Pull State

are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.

2.3.2.21 Supply for Core Logic: 1.2V nominal

Table 2-48. ZWT Supply for Core Logic: 1.2V nominal

VCC F9 1.2V - - Core supply VCC F10 VCC H10 VCC J14 VCC K6 VCC K8 VCC K12 VCC K14 VCC L6 VCC M10 VCC P10

Terminal Signal Default Pull Type Description

Signal Name 337

Type Pull State

ZWT

Power

Submit Documentation Feedback

Page 44

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

2.3.2.22 Supply for I/O Cells: 3.3V nominal

Terminal Signal Default Pull Type Description

Signal Name 337

VCCIO F6 3.3V - - Operating supply for I/Os VCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 VCCIO L14 VCCIO M6 VCCIO M14 VCCIO N6 VCCIO N14 VCCIO P6 VCCIO P7 VCCIO P8 VCCIO P9 VCCIO P12 VCCIO P13 VCCIO P14

www.ti.com

Table 2-49. ZWT Supply for I/O Cells: 3.3V nominal

Type Pull State

ZWT

Power

Submit Documentation Feedback

Page 45

PRODUCTPREVIEW

RM46L852

www.ti.com

2.3.2.23 Ground Reference for All Supplies Except VCCAD

Table 2-50. ZWT Ground Reference for All Supplies Except VCCAD

Terminal Signal Default Pull Type Description

Signal Name 337

VSS A1 Ground - - Ground reference VSS A2 VSS A18 VSS A19 VSS B1 VSS B19 VSS H8 VSS H9 VSS H11 VSS H12 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VSS K9 VSS K10 VSS K11 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS M8 VSS M9 VSS M11 VSS M12 VSS V1 VSS W1 VSS W2

SPNS185 –SEPTEMBER 2012

Type Pull State

ZWT

Submit Documentation Feedback

Page 46

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

3 Device Operating Conditions

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range,

(2)

Supply voltage range: V

Input voltage range:

CCIO

CCAD

All input pins, with exception of ADC pins -0.3 V to 4.1 V ADC input pins -0.3 V to 5.25 V IIK(VI< 0 or VI> V

All pins, except AD1IN[23:0]

Input clamp current: IIK(VI< 0 or VI> V

AD1IN[23:0]

Total ±40 mA Operating free-air temperature range, TA: -40°C to 105°C Operating junction temperature range, TJ: -40°C to 150°C Storage temperature range, T

stg

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated

grounds.

, V

CCP

(2)

) ±20 mA

CCIO

) ±10 mA

CCAD

(1)

-0.3 V to 1.43 V

-0.3 V to 4.1 V

-0.3 V to 5.5 V

-65°C to 150°C

3.2 Device Recommended Operating Conditions

CCPLL

CCIO

CCAD

CCP

SSAD

ADREFHI

ADREFLO

(1) All voltages are with respect to VSS, except V

Digital logic supply voltage (Core) 1.14 1.2 1.32 V PLL Supply Voltage 1.14 1.2 1.32 V Digital logic supply voltage (I/O) 3 3.3 3.6 V MibADC supply voltage 3 5.25 V Flash pump supply voltage 3 3.3 3.6 V Digital logic supply ground 0 V MibADC supply ground -0.1 0.1 V A-to-D high-voltage reference source V A-to-D low-voltage reference source V Operating free-air temperature -40 105 °C Operating junction temperature -40 150 °C

, which is with respect to V

CCAD

(1)

SSAD

MIN NOM MAX UNIT

SSAD SSAD

V V

CCAD CCAD

V V

Submit Documentation Feedback

Page 47

PRODUCTPREVIEW

AddressWaitstates

DataWaitstates

RAM

AddressWaitstates

DataWaitstates

Flash

0MHz

110MHz

0 1 3

165MHz

120MHz

220MHz

220MHz55MHz

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains

Table 3-1. Clock Domain Timing Specifications

Parameter Description Conditions Max Unit

GCLK

HCLK

VCLK

VCLK2

VCLK3

VCLKA1

VCLKA2

VCLKA3

VCLKA4

RTICLK

GCLK - CPU clock frequency f HCLK - System clock frequency Pipeline mode 220 MHz

enabled

Pipeline mode 55 MHz

disabled VCLK - Primary peripheral clock frequency 110 MHz VCLK2 - Secondary peripheral clock 110 MHz

frequency VCLK3 - Secondary peripheral clock 110 MHz

frequency VCLKA1 - Primary asynchronous 110 MHz

peripheral clock frequency VCLKA2 - Secondary asynchronous 110 MHz

peripheral clock frequency VCLKA3 - Primary asynchronous 110 MHz

peripheral clock frequency VCLKA4 - Secondary asynchronous 110 MHz

peripheral clock frequency RTICLK - clock frequency f

HCLK

VCLK

MHz

3.4 Wait States Required

As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required.

The TCM flash can support zero address and data wait states up to a CPU speed of 55MHz in non-pipelined mode.

The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state.

Figure 3-1. Wait States Scheme

Submit Documentation Feedback

Page 48

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

3.5 Power Consumption Over Recommended Operating Conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCCdigital supply current (operating mode) mA

VCCDigital supply current (LBIST mode) mA

VCC Digital supply current (PBIST mode)

CCPLL

CCIO

CCAD

CCREFHI

VCCPLL digital supply current (operating mode) V V

Digital supply current (operating mode. No DC load, V

CCIO

supply current (operating mode) mA

CCAD

supply current (operating mode) mA

REFHI

CCP

supply current mA

CCP

= 220MHz

HCLK

350 for PGE

Package

= 110MHz, 375 for ZWT

VCLK

Flash in pipelined Package400 mode, V

CCmax

LBIST clock rate = 110MHz

400

Peak PBIST ROM clock TBD RMS 260

frequency = 110MHz

= V

CCPLL

CCPLLmax

CCmax

10 mA 15 mA

Single ADC 15 operational, V

CCADmax

Both ADCs 30 operational, V

CCADmax

Single ADC 3 operational, AD

REFHImax

Both ADCs 6 operational, AD

REFHImax

read operation 34 V

CCPmax

program, V

CCPmax

read from 1 bank 55 and program another bank, V

CCPmax

erase, V

CCPmax

www.ti.com

Submit Documentation Feedback

Page 49

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

3.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V V V

C C

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

Input hysteresis All inputs 180 mV

hys

Low-level input voltage All inputs -0.3 0.8 V

High-level input voltage All inputs 2 V

IOL= I

OLmax

0.2 V

IOL= 50 µA, standard 0.2

Low-level output voltage V

output mode IOL= 50 µA, low-EMI 0.2 V

output mode (see

Section 3.10)

IOH= I

OHmax

IOH= 50 µA, standard V

High-level output voltage V

output mode IOH= 50 µA, low-EMI 0.8 V

output mode (see

0.8 V

CCIO

-0.2

CCIO

Section 3.10)

Input clamp current (I/O pins) mA

VI< V

> V IIHPulldown 20µA VI= V IIHPulldown 100µA VI= V

Input current (I/O pins) IILPullup 20µA VI= V

IILPullup 100µA VI= V

CCIO

SSIO

CCIO CCIO SS SS

+ 0.3

- 0.3 or V

-2 2

5 40

40 195

-40 -5 µA

-195 -40

All other pins No pullup or pulldown -1 1

Input capacitance 2 pF

Output capacitance 3 pF

+ 0.3 V

CCIO

(1)

Submit Documentation Feedback

Page 50

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

3.7 Output Buffer Drive Strengths

Low-level Output Current,

IOLfor VI=V

High-level Output Current,

IOHfor VI=V

OLmax

or Signals

OHmin

8mA

www.ti.com

Table 3-2. Output Buffer Drive Strengths

MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],

TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13],

N2HET2[15] ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B,

EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B EMIF_ADDR[0:12], EMIF_BA[0:1], EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15], EMIF_nCAS,

EMIF_nCS[0:4], EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE, EMIF_RNW

MDCLK, MDIO, MII_RX_VCLKA4, MII_TX_VCLKA4, MII_TXD[0:3], MII_TXEN, RMII_REFCLK, RMII_TXD[0:1], RMII_TXEN

USB1.PortPower, USB1.SPEED, USB1.SUSPEND, USB1.TXDAT, USB1.TXEN, USB1.TXSE0, USB2.PortPower, USB2.SPEED, USB2.SUSPEND, USB2.TXDAT, USB2.TXEN, USB2.TXSE0 ,USB_FUNC.GZO, USB_FUNC.PUENO, USB_FUNC.PUENON, USB_FUNC.SE0O, USB_FUNC.SUSPENDO, USB_FUNC.TXDO

4mA

2mA zero-dominant

selectable 8mA / 2mA

TEST, MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, ECAP2, ECAP3 nRST

AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7], GIOB[0-7], LINRX, LINTX, MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA,

MIBSPI5NCS[0-3], MIBSPI5NENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],

N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15], N2HET2[16], N2HET2[18],

SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA ECLK,

SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8mA for these signals.

Submit Documentation Feedback

Page 51

PRODUCTPREVIEW

CCIO

Input

RM46L852

www.ti.com

3.8 Input Timings

in_slew

(1) t (2) The timing shown above is only valid for pin used in general-purpose input mode.

= peripheral VBUS clock cycle time = 1 / f

c(VCLK)

Input minimum pulse width t Time for input signal to go from VILto VIHor from VIHto V

3.9 Output Timings

Table 3-4. Switching Characteristics for Output Timings versus Load Capacitance (CL)

Rise time, t

Fall time, t

Rise time, t

Fall time, t

8mA low EMI pins CL = 15 pF 2.5 ns (see Table 3-2)

4mA low EMI pins CL = 15 pF 5.6 ns (see Table 3-2)

Rise time, t

Fall time, t

2mA-z low EMI pins CL = 15 pF 8 ns (see Table 3-2)

SPNS185 –SEPTEMBER 2012

Figure 3-2. TTL-Level Inputs

c(VCLK)

(1)

+ 10

(2)

1 ns

Table 3-3. Timing Requirements for Inputs

Parameter MIN MAX Unit

(VCLK)

Parameter MIN MAX Unit

CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5

CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2

CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33

Submit Documentation Feedback

Page 52

PRODUCTPREVIEW

CCIO

Output

RM46L852

SPNS185 –SEPTEMBER 2012

Table 3-4. Switching Characteristics for Output Timings versus Load Capacitance (CL) (continued)

Parameter MIN MAX Unit

Rise time, t

Fall time, t

Rise time, t

Fall time, t

Selectable 8mA / 2mA-z 8mA mode CL = 15 pF 2 ns pins (see Table 3-2)

CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11 CL = 15 pF 2 ns CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11

2mA-z mode CL = 15 pF 8 ns

CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33

www.ti.com

d(parallel_out)

(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check

Table 3-2 for output buffer drive strength information on each signal.

Delay between low to high, or high to low transition of general-purpose output signals 6 ns that can be configured by an application in parallel, e.g. all signals in a GIOA port, or all N2HET1 signals, etc.

Figure 3-3. CMOS-Level Outputs

Table 3-5. Timing Requirements for Outputs

Parameter MIN MAX UNIT

(1)

Submit Documentation Feedback

Page 53

PRODUCTPREVIEW

RM46L852

www.ti.com

3.10 Low-EMI Output Buffers

The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads.

This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively.

Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW.

Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so as to maintain the output voltage at or above VREFHIGH.

SPNS185 –SEPTEMBER 2012

The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.

Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an issue since the actual clamp current capability is always greater than the IOH / IOL specifications.

The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode.

Module or Signal Name Control Register to Enable Low-EMI Mode

Module: MibSPI1 GPREG1.0 Module: SPI2 GPREG1.1 Module: MibSPI3 GPREG1.2 Reserved GPREG1.3 Module: MibSPI5 GPREG1.4 Reserved GPREG1.5 Module: EMIF GPREG1.6 Reserved GPREG1.7 Signal: TMS GPREG1.8 Signal: TDI GPREG1.9 Signal: TDO GPREG1.10 Signal: RTCK GPREG1.11 Signal: TEST GPREG1.12 Signal: nERROR GPREG1.13 Signal: AD1EVT GPREG1.14

Table 3-6. Low-EMI Output Buffer Hookup

Submit Documentation Feedback

Page 54

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4 System Information and Electrical Specifications

4.1 Device Power Domains

The device core logic is split up into multiple power domains in order to optimize the power for a given application use case. There are 6 core power domains in total: PD1, PD2, PD3, PD5, RAM_PD1, and RAM_PD2. Refer to Section 1.4 for more information.

PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains can be turned ON/OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of the device technical reference manual for more details.

NOTE

The clocks to a module must be turned off before powering down the core domain that contains the module.

NOTE

The logic in the modules that are powered down loses its power completely. Any access to modules that are powered down results in an abort being generated. When power is restored, the modules power-up to their default states (after normal power-up). No register or memory contents are preserved in the core domains that are turned off.

www.ti.com

4.2 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies.

4.2.1 Important Considerations

• The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the device is held in reset when the voltage supplies are out of range.

• The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

4.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 4.3.3.1 for the timing information on this glitch filter.

Submit Documentation Feedback

Page 55

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 4-1. Voltage Monitoring Specifications

PARAMETER MIN TYP MAX UNIT

VCC low - VCC level below this 0.8 0.9 1.0 V threshold is detected as too low.

MON

Voltage monitoring VCC high - VCC level above this 1.40 1.7 2.1 thresholds threshold is detected as too high.

VCCIO low - VCCIO level below this 1.9 2.4 2.9 threshold is detected as too low.

4.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies. The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the

maximum specification cannot be filtered.

Table 4-2. VMON Supply Glitch Filtering Capability

Parameter MIN MAX

Width of glitch on VCC that can be filtered 250ns 1us

Width of glitch on VCCIO that can be filtered 250ns 1us

Submit Documentation Feedback

Page 56

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.3 Power Sequencing and Power On Reset

4.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The powerup sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 4-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 4-3. Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles

eFuse autoload 1160 oscillator cycles

Flash pump power-up 688 oscillator cycles

Flash bank power-up 617 oscillator cycles

Total 3497 oscillator cycles

The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000.

www.ti.com

4.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

4.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

4.3.3.1 nPORRST Electrical and Timing Requirements

NO Parameter MIN MAX Unit

3 t

6 t 7 t

8 t 9 t

CCPORL

CCPORH

CCIOPORL

CCIOPORH

IL(PORRST)

su(PORRST)

h(PORRST) su(PORRST)

h(PORRST) h(PORRST)

VCClow supply level when nPORRST must be active during power- 0.5 V up

VCChigh supply level when nPORRST must remain active during 1.14 V power-up and become active during power down

CCIO

power-up V

CCIO

during power-up and become active during power down Low-level input voltage of nPORRST V Low-level input voltage of nPORRST V Setup time, nPORRST active before V

during power-up Hold time, nPORRST active after VCC> V Setup time, nPORRST active before VCC< V

down Hold time, nPORRST active after V Hold time, nPORRST active after VCC< V

Table 4-4. Electrical Requirements for nPORRST

/ V

low supply level when nPORRST must be active during 1.1 V

CCP

/ V

high supply level when nPORRST must remain active 3.0 V

CCP

> 2.5V 0.2 * V

CCIO

< 2.5V 0.5 V

CCIO

and V

CCPORH

CCPORL

> V

CCP

CCIOPORL

during power 2 µs

> V

CCP

CCIOPORH

0 ms

1 ms

1 ms 0 ms

CCIO

Submit Documentation Feedback

Page 57

PRODUCTPREVIEW

3.3 V V

CCIOPORH

1.2 V

CCPORH

CCIOPORL

V (1.2 V)

V / V (3.3 V)

CCIO CCP

nPORRST

CCPORL

IL(PORRST)

V / V

CCIO CCP

CCPORL

IL(PORRST)

CCIOPORH

CCPORH

CCIOPORL

NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

Table 4-4. Electrical Requirements for nPORRST (continued)

NO Parameter MIN MAX Unit

f(nPORRST)

Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses greater than MAX

will generate a reset.

500 2000 ns

Figure 4-1. nPORRST Timing Diagram

Submit Documentation Feedback

Page 58

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

www.ti.com

4.4 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

4.4.1 Causes of Warm Reset

Table 4-5. Causes of Warm Reset

DEVICE EVENT SYSTEM STATUS FLAG

Power-Up Reset Exception Status Register, bit 15 Oscillator fail Global Status Register, bit 0 PLL slip Global Status Register, bits 8 and 9 Watchdog exception / Debugger reset Exception Status Register, bit 13 CPU Reset (driven by the CPU STC) Exception Status Register, bit 5 Software Reset Exception Status Register, bit 4 External Reset Exception Status Register, bit 3

4.4.2 nRST Timing Requirements

v(RST)

f(nRST)

(1) Specified values do NOT include rise/fall times. For rise and fall timings, see Table 3-4.

PARAMETER MIN MAX UNIT

Valid time, nRST active after 1160 t nPORRST inactive

Valid time, nRST active (all other 8t System reset conditions)

Filter time nRST pin; pulses less than MIN will be

filtered out, pulses greater than MAX will generate a reset

Table 4-6. nRST Timing Requirements

+ 1048t

c(OSC)

c(VCLK)

500 2000 ns

c(OSC)

(1)

Submit Documentation Feedback

Page 59

PRODUCTPREVIEW

North

Flip West

RM46L852

www.ti.com

4.5 ARM©Cortex-R4F™ CPU Information

4.5.1 Summary of ARM Cortex-R4F™ CPU Features

The features of the ARM Cortex-R4F™ CPU include:

• An integer unit with integral EmbeddedICE-RT logic.

• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.

• Floating Point Coprocessor

• Dynamic branch prediction with a global history buffer, and a 4-entry return stack

• Low interrupt latency.

• Non-maskable interrupt.

• A Harvard Level one (L1) memory system with: – Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking

memories

– ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions

• Dual core logic for fault detection in safety-critical applications.

• An L2 memory interface: – Single 64-bit master AXI interface – 64-bit slave AXI interface to TCM RAM blocks

• A debug interface to a CoreSight Debug Access Port (DAP).

• A Performance Monitoring Unit (PMU).

• A Vectored Interrupt Controller (VIC) port.

SPNS185 –SEPTEMBER 2012

For more information on the ARM Cortex-R4F™ CPU please see www.arm.com.

4.5.2 ARM Cortex-R4F™ CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

• ECC On Tightly-Coupled Memory (TCM) Accesses

• Hardware Vectored Interrupt (VIC) Port

• Floating Point Coprocessor

• Memory Protection Unit (MPU)

4.5.3 Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCMR4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock cycles as shown in Figure 4-3.

The CPUs have a diverse CPU placement given by following requirements:

• different orientation; e.g. CPU1 = "north" orientation, CPU2 = "flip west" orientation

• dedicated guard ring for each CPU

Figure 4-2. Dual - CPU Orientation

Submit Documentation Feedback

Page 60

PRODUCTPREVIEW

CPU 1 CPU 2

2cycledelay

CCM-R4

compare

CPU1CLK

CPU2CLK

compare

error

Input+Control

Output+Control

RM46L852

SPNS185 –SEPTEMBER 2012

4.5.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 4-3.

4.5.5 ARM Cortex-R4F™ CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4F™ CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in the figure below.

www.ti.com

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

4.5.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

• Ability to divide the complete test run into independent test intervals

• Capable of running the complete test as well as running few intervals at a time

• Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set)

• Complete isolation of the self-tested CPU core from rest of the system during the self-test run

• Ability to capture the Failure interval number

• Timeout counter for the CPU self-test run as a fail-safe feature

Figure 4-3. Dual Core Implementation

Submit Documentation Feedback

Page 61

PRODUCTPREVIEW

RM46L852

www.ti.com

4.5.6.1 Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.

2. Select number of test intervals to be run.

3. Configure the timeout period for the self-test run.

4. Enable self-test.

5. Wait for CPU reset.

6. In the reset handler, read CPU self-test status to identify any failures.

7. Retrieve CPU state if required.

For more information see the device Technical Reference Manual.

4.5.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 110MHz. The STCCLK is divided down from the CPU clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see the device Technical Reference Manual.

4.5.6.3 CPU Self-Test Coverage

Table 4-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test

cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 4-7. CPU Self-Test Coverage

SPNS185 –SEPTEMBER 2012

INTERVALS TEST COVERAGE, % TEST CYCLES

0 0 0 1 62.13 1365 2 70.09 2730 3 74.49 4095 4 77.28 5460 5 79.28 6825 6 80.90 8190 7 82.02 9555 8 83.10 10920

9 84.08 12285 10 84.87 13650 11 85.59 15015 12 86.11 16380 13 86.67 17745 14 87.16 19110 15 87.61 20475 16 87.98 21840 17 88.38 23205 18 88.69 24570 19 88.98 25935 20 89.28 27300 21 89.50 28665 22 89.76 30030 23 90.01 31395 24 90.21 32760

Submit Documentation Feedback

Page 62

PRODUCTPREVIEW

OSCIN

OSCOUT

(see Note A)

Crystal

(a)

OSCIN OSCOUT

(b)

External

(toggling 0-3.3V)

Clock Signal

Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.

Kelvin_GND

Note B: Kelvin_GND should not be connected to any other GND.

(see Note B)

RM46L852

SPNS185 –SEPTEMBER 2012

4.6 Clocks

4.6.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

Table 4-8. Available Clock Sources

Clock

Source #

0 OSCIN Main Oscillator Enabled 1 PLL1 Output From PLL1 Disabled 2 Reserved Reserved Disabled 3 EXTCLKIN1 External Clock Input #1 Disabled 4 LFLPO Low Frequency Output of Internal Reference Oscillator Enabled

5 HFLPO Enabled 6 PLL2 Output From PLL2 Disabled

7 EXTCLKIN2 External Clock Input #2 Disabled

Name Description Default State

High Frequency Output of Internal Reference

Oscillator

www.ti.com

4.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in the figure below.

Figure 4-4. Recommended Crystal/Clock Connection

Submit Documentation Feedback

Page 63

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

4.6.1.1.1 Timing Requirements for Main Oscillator

Table 4-9. Timing Requirements for Main Oscillator

Parameter MIN Type MAX Unit

tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a 12.5 200 ns

tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN 15 ns

tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN 15 ns

square wave )

is a square wave)

Submit Documentation Feedback

Page 64

PRODUCTPREVIEW

BIAS_EN

Low

Power

Oscillator

LFEN

LF_TRIM

HFEN

HF_TRIM

LFLPO

HFLPO

HFLPO_VALID

nPORRST

RM46L852

SPNS185 –SEPTEMBER 2012

4.6.1.2 Low Power Oscillator

The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

4.6.1.2.1 Features

The main features of the LPO are:

• Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module.

• Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5 of the Global Clock Module.

• Provides a comparison clock for the crystal oscillator failure detection circuit.

www.ti.com

Figure 4-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO)

and provides two clock sources: one nominally 80KHz and one nominally 10MHz.

Clock Detection oscillator fail frequency - lower threshold, using 1.375 2.4 4.875 MHz

LPO - HF oscillator untrimmed frequency 5.5 9.6 19.5 MHz

LPO - LF oscillator untrimmed frequency 36 85 180 kHz

untrimmed LPO output oscillator fail frequency - higher threshold, using 22 38.4 78 MHz

untrimmed LPO output

startup time from STANDBY (LPO BIAS_EN High for 10 µs at least 900µs)

cold startup time 900 µs

startup time from STANDBY (LPO BIAS_EN High for 100 µs at least 900µs)

cold startup time 2000 µs

Figure 4-5. LPO Block Diagram

Table 4-10. LPO Specifications

Parameter MIN Typical MAX Unit

Submit Documentation Feedback

Page 65

PRODUCTPREVIEW

/NR

/1 to /64

OSCIN

PLL

INTCLK

/OD

/1 to /8

VCOCLK

/1 to /32

post_ODCLK

/NF

/1 to /256

PLLCLK

/NR2

/1 to /64

OSCIN

PLL#2

INTCLK2

/OD2

/1 to /8

VCOCLK2

/R2

/1 to /32

post_ODCLK2

/NF2

/1 to /256

PLL2CLK

PLLCLK

= (f

OSCIN

/ NR) * NF / (OD * R)

PLL2CLK

= (f

OSCIN

/ NR2) * NF2 / (OD2 * R2)

RM46L852

www.ti.com

4.6.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are:

• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled.

• Configurable frequency multipliers and dividers.

• Built-in PLL Slip monitoring circuit.

• Option to reset the device on a PLL slip detection.

4.6.1.3.1 Block Diagram

Figure 4-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and

PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2.

SPNS185 –SEPTEMBER 2012

4.6.1.3.2 PLL Timing Specifications

PARAMETER MIN MAX UNIT

INTCLK

post_ODCLK

VCOCLK

INTCLK2

post_ODCLK2

VCOCLK2

PLL1 Reference Clock frequency 1 f Post-ODCLK – PLL1 Post-divider input 400 MHz

clock frequency VCOCLK – PLL1 Output Divider (OD) input 150 550 MHz

clock frequency PLL2 Reference Clock frequency 1 f Post-ODCLK – PLL2 Post-divider input 400 MHz

clock frequency VCOCLK – PLL2 Output Divider (OD) input 150 550 MHz

clock frequency

Figure 4-6. PLLx Block Diagram

Table 4-11. PLL Timing Specifications

Submit Documentation Feedback

(OSC_SQR)

MHz

Page 66

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.6.1.4 External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square wave input. The electrical and timing requirements for these clock inputs are specified below.

Table 4-12. External Clock Timing and Electrical Specifications

Parameter Description Min Max Unit

EXTCLKx

w(EXTCLKIN)H

w(EXTCLKIN)L

iL(EXTCLKIN)

iH(EXTCLKIN)

External clock input frequency 80 MHz EXTCLK high-pulse duration 6 ns EXTCLK low-pulse duration 6 ns Low-level input voltage -0.3 0.8 V High-level input voltage 2 VCCIO + 0.3 V

4.6.2 Clock Domains

4.6.2.1 Clock Domain Descriptions

The table below lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain.

Clock Domain Name Default Clock Clock Source Description

HCLK OSCIN GHVSRC

Source Selection Register

GCLK OSCIN GHVSRC

GCLK2 OSCIN GHVSRC

VCLK OSCIN GHVSRC

VCLK2 OSCIN GHVSRC

VCLK3 OSCIN GHVSRC

VCLK4 OSCIN GHVSRC

VCLKA1 VCLK VCLKASRC

VCLKA2 VCLK VCLKASRC

www.ti.com

Table 4-13. Clock Domain Descriptions

• Is disabled via the CDDISx registers bit 1

• Used for all system modules including DMA, ESM

• Always the same frequency as HCLK

• In phase with HCLK

• Is disabled separately from HCLK via the CDDISx registers bit 0

• Can be divided by 1up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108

• Always the same frequency as GCLK

• 2 cycles delayed from GCLK

• Is disabled along with GCLK

• Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST)

• Divided down from HCLK

• Can be HCLK/1, HCLK/2, ... or HCLK/16

• Is disabled separately from HCLK via the CDDISx registers bit 2

• Divided down from HCLK

• Can be HCLK/1, HCLK/2, ... or HCLK/16

• Frequency must be an integer multiple of VCLK frequency

• Is disabled separately from HCLK via the CDDISx registers bit 3

• Divided down from HCLK

• Can be HCLK/1, HCLK/2, ... or HCLK/16

• Is disabled separately from HCLK via the CDDISx registers bit 8

• Divided down from HCLK

• Can be HCLK/1, HCLK/2, ... or HCLK/16

• Is disabled separately from HCLK via the CDDISx registers bit 9

• Defaults to VCLK as the source

• Is disabled via the CDDISx registers bit 4

• Defaults to VCLK as the source

• Is disabled via the CDDISx registers bit 5

Submit Documentation Feedback

Page 67

PRODUCTPREVIEW

RM46L852

www.ti.com

Table 4-13. Clock Domain Descriptions (continued)

Clock Domain Name Default Clock Clock Source Description

VCLKA3_S VCLK VCLKACON

VCLKA3_DIVR VCLK VCLKACON1

VCLKA4_S VCLK VCLKACON1

VCLKA4_DIVR VCLK VCLKACON1

RTICLK VCLK RCLKSRC

Source Selection Register

• Defaults to VCLK as the source

• Frequency can be as fast as HCLK frequency.

• Is disabled via the CDDISx registers bit 10

• Divided down from the AVCLK3_S using the VCLKA3R field of the VCLKACON1 register at address 0xFFFFE140

• Frequency can be VCLKA3_S/1, VCLKA3_S/2, ..., or VCLKA3_S/8

• Default frequency is VCLKA3_S/2

• Is disabled separately via the VCLKACON1 register VCLKA3_DIV_CDDIS bit only if the VCLKA3_S clock is not disabled

• Defaults to VCLK as the source

• Frequency can be as fast as HCLK frequency

• Is disabled via the CDDISx registers bit 11

• Divided down from the VCLKA4_S using the VCLKA4R field of the VCLKACON1 register at address 0xFFFFE140

• Frequency can be VCLKA4_S/1, VCLKA4_S/2, ..., or VCLKA4_S/8

• Default frequency is VCLKA4_S/2

• Is disabled separately via the VCLKACON1 register VCLKA4_DIV_CDDIS bit only if the VCLKA4_S clock is not disabled

• Defaults to VCLK as the source

• If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3

– Application can ensure this by programming the RTI1DIV

field of the RCLKSRC register, if necessary

• Is disabled via the CDDISx registers bit 6

SPNS185 –SEPTEMBER 2012

Submit Documentation Feedback

Page 68

PRODUCTPREVIEW

HCLK (toSYSTEM)

GCLK,GCLK2 (toCPU)

GCM

VCLK_peri (VCLK to peripherals onPCR1)

VCLK2(toN2HETx andHTUx)

/1..16

OSCIN

LowPower

Oscillator

10MHz

80kHz

PLL #1(FMzPLL)

/1..64

X1..256

/1..8

/1..32

PLL #2

/1,2,..256

SPIx,MibSPIx

/2,3..2

LIN,SCI

SPI

LIN /SCI

/1,2..32

MibADCx

ADCLK

/1,2..65536

ExternalClock

ECLK

VCLK2

N2HETx

HRP

/1..64

LRP

/20..2

Loop

ResolutionClock

High

BaudRate

VCLK2

Ethernet

VCLKA4_DIVR

/1..64 X1..256 /1..8

/1..32 *

EXTCLKIN1

EXTCLKIN2

VCLKA1(to DCANx)to

0 1

4 5

VCLK

RTICLK (toRTI,DWWD)

/1,2,4,or8

VCLK

0 1

4 5

VCLK3

VCLK3(toEthernet,USB)

/1..16

VCLK_sys (VCLK to systemmodules)

*thefrequencyatthisnodemustnot exceedthemaximumHCLKspecifiation.

/1,2..256

I2C

I2Cbaud rate

4 5

VCLK

NTU[1]

NTU[0]

NTU[2]

NTU[3]

RTI

PLL#2output

EXTCLKIN1

Reserved

VCLK

/1,2,..1024

Phase_seg2

CANBaudRate

Phase_seg1

VCLKA1

Prop_seg

(FMzPLL)

VCLKA3_S(leftopen)

/DIVR

VCLKA3_DIVR (toUSBDevice/48MHZ andUSBHost/48MHz)

USBHost

VCLKA3_DIVR/4

VCLKA3_DIVR

DCANx

EMIF USBDevice

VCLKA3_DIVR

N2HETx

VCLKA4_DIVR

/DIVR

PLL2ODCLK/8

PLL2ODCLK/16

VCLKA4_DIVR_EMAC

(toEMAC)

VCLKA4_S(leftopen)

4 5 6

VCLK

VCLKA3_DIVR/4 (toUSBHost/12MHz)

VCLKA4_SRC

RM46L852

SPNS185 –SEPTEMBER 2012

4.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figures below.

www.ti.com

Figure 4-7. Device Clock Domains

Submit Documentation Feedback

Page 69

PRODUCTPREVIEW

VCLKA4_SRC

0 1 3 4 5 6 7

VCLK

VCLKA4_S(leftopen)

/DIVR

PLL2post_ODCLK/8

PLL2post_ODCLK/16

VCLKA4_DIVR_EMAC (toEMAC)

RM46L852

www.ti.com

4.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC

Some applications may need to use both the of Ethernet interfaces. The MII interface requires VCLKA4_DIVR_EMAC to be 25MHz and the RMII requires VCLKA4_DIVR_EAMC to be 50MHz.

These different frequencies are supported by adding special dedicated clock source selection options for the VCLKA4_DIVR_EMAC clock domain. This logic is shown in .

Figure 4-8. VCLKA4_DIVR Source Selection Options

The PLL2 post_ODCLK is brought out as a separate output from the PLL wrapper module. There are two additional dividers implemented at the device-level to divide this PLL2 post_ODCLK by 8 and by 16.

As shown in , the VCLKA4_SRC configured via the system module VCLKACON1 control register is used to determine the clock source for the VCLKA4_S and VCLKA4_DIVR. An additional multiplexor is implemented to select between the VCLKA4_DIVR and the two additional clock sources – PLL2 post_ODCLK/8 and post_ODCLK/16.

SPNS185 –SEPTEMBER 2012

The selection is done as shown in the following table.

Table 4-14. VCLKA4_DIVR_EMAC Clock Source

Selection

VCLKA4_SRC from Clock Source for

VCLKACON1[19–16] VCLKA4_DIVR_EMAC

0x0 OSCIN / VCLKA4R 0x1 PLL1CLK / VCLKA4R 0x2 Reserved 0x3 EXTCLKIN1 / VCLKA4R 0x4 LF LPO / VCLKA4R 0x5 HF LPO / VCLKA4R 0x6 PLL2CLK / VCLKA4R 0x7 EXTCLKIN2 / VCLKA4R

Submit Documentation Feedback

Page 70

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.6.3 Clock Test Mode

The platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured via the CLKTEST register in the system module.

SEL_ECP_PIN SEL_GIO_PIN

= SIGNAL ON ECLK = SIGNAL ON N2HET1[12]

CLKTEST[3-0] CLKTEST[11-8]

0000 Oscillator 0000 Oscillator Valid Status 0001 Main PLL free-running clock output 0001 Main PLL Valid status 0010 Reserved 0010 Reserved 0011 EXTCLKIN1 0011 Reserved 0100 LFLPO 0100 Reserved 0101 HFLPO 0101 HFLPO Valid status 0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status 0111 EXTCLKIN2 0111 Reserved 1000 GCLK 1000 LFLPO 1001 RTI Base 1001 Oscillator Valid status 1010 Reserved 1010 Oscillator Valid status 1011 VCLKA1 1011 Oscillator Valid status 1100 Reserved 1100 Oscillator Valid status 1101 VCLKA3_DIVR 1101 VCLKA3_S 1110 VCLKA4_DIVR 1110 VCLKA4_S 1111 Reserved 1111 Oscillator Valid status

www.ti.com

Table 4-15. Clock Test Mode Options

Submit Documentation Feedback

Page 71

PRODUCTPREVIEW

f[MHz]

1.375 4.875 22 78

guaranteed fail

lower

threshold

guaranteed pass

upper

threshold

guaranteed fail

RM46L852

www.ti.com

4.7 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO).

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO). The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN

frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock).

The valid OSCIN frequency range is defined as: f

4.7.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 4-10.

Figure 4-9. LPO and Clock Detection, Untrimmed HFLPO

HFLPO

/ 4 < f

OSCIN

< f

HFLPO

SPNS185 –SEPTEMBER 2012

* 4.

4.7.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

4.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0.

4.7.3.1 Features

• Takes two different clock sources as input to two independent counter blocks.

• One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."

• Each counter block is programmable with initial, or seed values.

• The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU.

Submit Documentation Feedback

Page 72

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.7.3.2 Mapping of DCC Clock Source Inputs Table 4-16. DCC1 Counter 0 Clock Sources

CLOCK SOURCE [3:0] CLOCK NAME

others oscillator (OSCIN)

0x5 high frequency LPO

0xA test clock (TCK)

Table 4-17. DCC1 Counter 1 Clock Sources

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME

others - N2HET1[31]

0xA 0x3 high frequency LPO

www.ti.com

0x0 Main PLL free-running clock output 0x1 PLL #2 free-running clock output 0x2 low frequency LPO

0x4 reserved 0x5 EXTCLKIN1 0x6 EXTCLKIN2 0x7 reserved

0x8 - 0xF VCLK

CLOCK SOURCE [3:0] CLOCK NAME

others oscillator (OSCIN)

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME

others - N2HET2[0]

0xA 00x0 - 0x7 Reserved

Table 4-18. DCC2 Counter 0 Clock Sources

0xA test clock (TCK)

Table 4-19. DCC2 Counter 1 Clock Sources

0x8 - 0xF VCLK

Submit Documentation Feedback

Page 73

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

4.8 Glitch Filters

A glitch filter is present on the following signals.

Table 4-20. Glitch Filter Timing Specifications

Pin Parameter MIN MAX Unit

nPORRST t

nRST t

TEST t

(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,

I/O pins, etc.) without also generating a valid reset signal to the CPU.

f(nPORRST)

f(nRST)

f(TEST)

Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses greater than

MAX will generate a reset Filter time nRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

Filter time TEST pin; pulses less than MIN will be filtered out, pulses greater than

MAX will pass through

(1)

500 2000 ns

Submit Documentation Feedback

Page 74

PRODUCTPREVIEW

Flash(1.25MB)

RAM(192KB)

0x00000000

0x0013FFFF

0x08000000

0x0802FFFF

CRC

0xFE000000

Peripherals -Frame1

0xFF000000

SYSTEMModules

0xFFFFFFFF

0xF07FFFFF

RAM-ECC

0x08400000

0x0842FFFF

RESERVED

0xF0000000

0x60000000

0x6FFFFFFF

CS2

RESERVED

CS3

Flash(1.25MB)(MirroredImage)

0x20000000

RESERVED

CS4

RESERVED

Peripherals -Frame2

0xFC000000

0xFCFFFFFF

0xFFF80000

0x80000000

0x87FFFFFF

CS0

RESERVED

reserved

AsyncRAM

SDRAM

0x64000000

0x68000000

0x6C000000

FlashModuleBus2Interface

RESERVED

(FlashECC,OTP and

EEPROMEmulationaccesses)

EMIF(64MB)

EMIF(32kB*3)

0x2013FFFF

RM46L852

SPNS185 –SEPTEMBER 2012

4.9 Device Memory Map

4.9.1 Memory Map Diagram

The figure below shows the device memory map.

www.ti.com

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.

Figure 4-10. Memory Map

Submit Documentation Feedback

Page 75

PRODUCTPREVIEW

RM46L852

www.ti.com

4.9.2 Memory Map Table

Please refer to for a block diagrams showing the devices interconnect.

MODULE NAME UNIMPLEMENTED LOCATIONS IN

TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 1.25MB

TCM RAM + RAM

ECC Abort

Mirrored Flash 0x2000_0000 0x20FF_FFFF 16MB 1.25MB

EMIF Chip Select 2 (asynchronous)

EMIF Chip Select 3 (asynchronous)

EMIF Chip Select 4 (asynchronous)

EMIF Chip Select

0 (synchronous)

Customer OTP,

TCM Flash Banks

Customer OTP,

Bank 7

Customer

OTP–ECC, TCM 0xF004_0000 0xF004_03FF 1kB 512B

Flash Banks

Customer

OTP–ECC, 0xF004_1C00 0xF004_1FFF 1kB 512B

Bank 7

TI OTP, TCM

Flash Banks

TI OTP,

Bank 7

TI OTP–ECC,

TCM Flash Banks

TI OTP–ECC,

Bank 7

Bank 7 – ECC 0xF010_0000 0xF013_FFFF 256kB 8kB

Bank 7 0xF020_0000 0xF03F_FFFF 2MB 64kB

Flash Data Space

ECC

CPPI Memory

Slave (Ethernet 0xFC52_0000 0xFC52_1FFF 8kB 8kB Abort

RAM)

CPGMAC Slave (Ethernet Slave)

CPGMACSS

Wrapper (Ethernet Wrapper)

Ethernet MDIO

Interface

FRAME CHIP FRAME ACTUA

SELECT SIZE L SIZE

CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 192kB

Flash mirror

frame

EMIF select 2 0x6000_0000 0x63FF_FFFF 64MB 32kB

EMIF select 3 0x6400_0000 0x67FF_FFFF 64MB 32kB

EMIF select 4 0x6800_0000 0x6BFF_FFFF 64MB 32kB

EMIF select 0 0x8000_0000 0x87FF_FFFF 128MB 64MB

SPNS185 –SEPTEMBER 2012

Table 4-21. Device Memory Map

FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO

START END

Memories tightly coupled to the ARM Cortex-R4F CPU

External Memory Accesses

Access to "Reserved" space will

Flash Module Bus2 Interface

0xF000_0000 0xF000_1FFF 8kB 4kB

0xF000_E000 0xF000_FFFF 8kB 4kB

0xF008_0000 0xF008_1FFF 8kB 4kB

0xF008_E000 0xF008_FFFF 8kB 4kB

0xF00C_0000 0xF00C_03FF 1kB 512B

0xF00C_1C00 0xF00C_1FFF 1kB 512B

0xF040_0000 0xF04F_FFFF 1MB 160kB

Ethernet and EMIF slave interfaces

0xFCF7_8000 0xFCF7_87FF 2kB 2kB No error

0xFCF7_8800 0xFCF7_88FF 256B 256B No error

0xFCF7_8900 0xFCF7_89FF 256B 256B No error

FRAME

generate Abort

Abort

Submit Documentation Feedback

Page 76

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

MODULE NAME UNIMPLEMENTED LOCATIONS IN

W2FC (USB

device controller 0xFCF7_8A00 0xFCF7_8A7F 128B 128B Abort

registers)

OHCI (USB Host

controller 0xFCF7_8B00 0xFCF7_8BFF 256B 256B Abort registers)

EMIF Registers 0xFCFF_E800 0xFCFF_E8FF 256B 256B Abort

ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort ePWM5 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort

eCAP1 0xFCF7_9300 0xFCF7_94FF 256B 256B Abort eCAP2 0xFCF7_9400 0xFCF7_95FF 256B 256B Abort eCAP3 0xFCF7_9500 0xFCF7_96FF 256B 256B Abort eCAP4 0xFCF7_9600 0xFCF7_97FF 256B 256B Abort eCAP5 0xFCF7_9700 0xFCF7_98FF 256B 256B Abort eCAP6 0xFCF7_9800 0xFCF7_99FF 256B 256B Abort eQEP1 0xFCF7_9900 0xFCF7_9AFF 256B 256B Abort eQEP2 0xFCF7_9A00 0xFCF7_9BFF 256B 256B Abort

CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort.

MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128kB 2kB Abort for accesses above 2kB MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128kB 2kB Abort for accesses above 2kB MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128kB 2kB Abort for accesses above 2kB

DCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128kB 2kB

DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128kB 2kB

DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128kB 2kB

MIBADC2 RAM 8kB

MIBADC2 Look- ends at address offset 0x217F. Wrap

Up Table around for accesses between offsets

FRAME CHIP FRAME ACTUA

SELECT SIZE L SIZE

PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128kB

Table 4-21. Device Memory Map (continued)

FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO

START END

SCR5: Enhanced Timer Peripherals

Cyclic Redundancy Checker (CRC) Module Registers

Peripheral Memories

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF. Abort generated for

accesses beyond 0x1FFF.

Look-Up Table for ADC2 wrapper.

Starts at address offset 0x2000 and

384B

0x0180 and 0x3FFF. Abort generated

for accesses beyond offset 0x4000.

FRAME

www.ti.com

Submit Documentation Feedback

Page 77

PRODUCTPREVIEW

RM46L852

www.ti.com

MODULE NAME UNIMPLEMENTED LOCATIONS IN

MIBADC1 RAM 8kB

MibADC1 Look- ends at address offset 0x217F. Wrap

Up Table around for accesses between offsets

N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128kB 16kB

N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128kB 16kB

N2HET2 TU2

RAM

N2HET1 TU1

RAM

CoreSight Debug Reads return zeros, writes have no

ROM effect

Cortex-R4F Reads return zeros, writes have no

Debug effect

POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4kB 4kB Abort

HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B

HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B

N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B

N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B

GIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B

MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B

MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B

I2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B

DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B

DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B

DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B

LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B

SCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B

FRAME CHIP FRAME ACTUA

SELECT SIZE L SIZE

PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128kB

PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128kB 1kB Abort

PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128kB 1kB Abort

CSCS0 0xFFA0_0000 0xFFA0_0FFF 4kB 4kB

CSCS1 0xFFA0_1000 0xFFA0_1FFF 4kB 4kB

SPNS185 –SEPTEMBER 2012

Table 4-21. Device Memory Map (continued)

FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO

START END

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF. Abort generated for

accesses beyond 0x1FFF.

Look-Up Table for ADC1 wrapper.

Starts at address offset 0x2000 and

384B

0x0180 and 0x3FFF. Abort generated

for accesses beyond offset 0x4000.

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

Debug Components

Peripheral Control Registers

Reads return zeros, writes have no

FRAME

effect

Submit Documentation Feedback

Page 78

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

MODULE NAME UNIMPLEMENTED LOCATIONS IN

MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B

SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B

MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B

SPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B

MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B

DMA RAM PPCS0 0xFFF8_0000 0xFFF8_0FFF 4kB 4kB Abort

VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4kB 1kB unimplemented address offsets

Flash Module PPCS7 0xFFF8_7000 0xFFF8_7FFF 4kB 4kB Abort

eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4kB 4kB Abort

Power

Management PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort

Module (PMM)

PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B

System Module -

Frame 2 (see PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B

device TRM)

PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B

STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B

IOMM

Multiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B

Control Module

DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B

DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1kB 1kB

DCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B

ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B

CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B

RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B

RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B

RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B

VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B

VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B

System Module -

Frame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B

device TRM)

FRAME CHIP FRAME ACTUA

SELECT SIZE L SIZE

Table 4-21. Device Memory Map (continued)

FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO

START END

Reads return zeros, writes have no

System Modules Control Registers and Memories

Wrap around for accesses to

Reads return zeros, writes have no

Generates address error interrupt, if

Reads return zeros, writes have no

FRAME

effect

between 1kB and 4kB.

effect

enabled

effect

www.ti.com

Submit Documentation Feedback

Page 79

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

4.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s program status register (CPSR).

4.9.4 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module.

Table 4-22. Master / Slave Access Matrix

MASTERS ACCESS MODE SLAVES ON MAIN SCR

Flash Module Non-CPU CRC EMIF, Slave Peripheral

Bus2 Interface: Accesses to Interfaces Control

OTP, ECC, Bank Program Flash Registers, All

7 and CPU Data Peripheral

CPU READ User/Privilege Yes Yes Yes Yes Yes

CPU WRITE User/Privilege No Yes Yes Yes Yes

DMA User Yes Yes Yes Yes Yes POM User Yes Yes Yes Yes Yes

DAP Privilege Yes Yes Yes Yes Yes HTU1 Privilege No Yes Yes Yes Yes HTU2 Privilege No Yes Yes Yes Yes

EMAC User No Yes No Yes No

OHCI User No Yes No Yes No

RAM Memories, And

Module Control

All System

Registers And

Memories

4.9.5 Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode. The device contains dedicated logic to generate a bus error response on any access to a module that is in

a power domain that has been turned OFF.

4.9.6 Parameter Overlay Module (POM) Considerations

• The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of the memory overlay are configurable via the POM control registers. Care must be taken to ensure that the overlay is mapped on to available memory.

• ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors will be generated.

• POM overlay must not be enabled when the flash and internal RAM memories are swapped via the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).

Submit Documentation Feedback

Page 80

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

• When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when another master accesses the TCM flash. This results in a system hang.

– The POM implements a timeout feature to detect this exact scenario. The timeout needs to be

enabled whenever POM overlay is enabled.

– The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global

Control register (POMGLBCTRL, address = 0xFFA04000).

– In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)

flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a data fetch.

– The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If

so, then the application can assume that the timeout is caused by a bus contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to a timeout from the POM.

www.ti.com

Submit Documentation Feedback

Page 81

PRODUCTPREVIEW

RM46L852

www.ti.com

4.10 Flash Memory

4.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Memory Arrays (or Banks) Sector Segment Low Address High Address

BANK0 (1.25MBytes) 0 16K Bytes 0x0000_0000 0x0000_3FFF

BANK7 (64kBytes) for EEPROM emulation 0 16K Bytes 0xF020_0000 0xF020_3FFF

4.10.2 Main Features of Flash Module

• Support for multiple flash banks for program and/or data storage

• Simultaneous read access on a bank while performing program or erase operation on any other bank

• Integrated state machines to automate flash erase and program operations

• Pipelined mode operation to improve instruction access interface bandwidth

• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU – Error address is captured for host system debugging

• Support for a rich set of diagnostic features

SPNS185 –SEPTEMBER 2012

Table 4-23. Flash Memory Banks and Sectors

No.

1 16K Bytes 0x0000_4000 0x0000_7FFF 2 16K Bytes 0x0000_8000 0x0000_BFFF 3 16K Bytes 0x0000_C000 0x0000_FFFF 4 16K Bytes 0x0001_0000 0x0001_3FFF 5 16K Bytes 0x0001_4000 0x0001_7FFF 6 32K Bytes 0x0001_8000 0x0001_FFFF 7 128K Bytes 0x0002_0000 0x0003_FFFF 8 128K Bytes 0x0004_0000 0x0005_FFFF

9 128K Bytes 0x0006_0000 0x0007_FFFF 10 128K Bytes 0x0008_0000 0x0009_FFFF 11 128K Bytes 0x000A_0000 0x000B_FFFF 12 128K Bytes 0x000C_0000 0x000D_FFFF 13 128K Bytes 0x000E_0000 0x000F_FFFF 14 128K Bytes 0x0010_0000 0x0011_FFFF 15 128K Bytes 0x0012_0000 0x0013_FFFF

1 16K Bytes 0xF020_4000 0xF020_7FFF

2 16K Bytes 0xF020_8000 0xF020_BFFF

3 16K Bytes 0xF020_C000 0xF020_FFFF

Submit Documentation Feedback

Page 82

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multi-bit error is only flagged. The CPU signals an ECC error via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states ORR r1, r1, #0x00000010 MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register MRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1 ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs DMB MCR p15, #0, r1, c1, c0, #1

4.10.4 Flash Access Speeds

www.ti.com

For information on flash memory access speeds and the relevant wait states required, refer to Section 3.4.

Submit Documentation Feedback

Page 83

PRODUCTPREVIEW

RM46L852

www.ti.com

SPNS185 –SEPTEMBER 2012

4.10.5 Program Flash

Table 4-24. Timing Requirements for Program Flash

Parameter MIN NOM MAX Unit

prog(144bit)

prog(Total)

erase(bank0)

wec

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

Wide Word (144bit) programming time 40 300 µs

1.25MByte programming time

Sector/Bank erase time -40°C to 105°C 0.3 4 s

Write/erase cycles with 15 year Data Retention -40°C to 105°C 1000 cycles requirement

(1)

-40°C to 105°C 13 s 0°C to 60°C, for first 3.3 6.6 s

25 cycles

0°C to 60°C, for first 30 500 ms 25 cycles

4.10.6 Data Flash

Table 4-25. Timing Requirements for Data Flash

Parameter MIN NOM MAX Unit

prog(144bit)

prog(Total)

EEPROM Emulation (bank 7) Sector/Bank erase time t

wec

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

Wide Word (144bit) programming time 40 300 µs EEPROM Emulation (bank 7) 64kByte -40°C to 105°C 660 ms

programming time

Write/erase cycles with 15 year Data Retention -40°C to 105°C 100000 cycles requirement

(1)

erase(bank7)

0°C to 60°C, for first 165 330 ms 25 cycles

-40°C to 105°C 0.08 8 s 0°C to 60°C, for first 30 500 ms

25 cycles

Submit Documentation Feedback

Page 84

PRODUCTPREVIEW

TCMBUS

72Bitdata+ECC

Upper32bits data&

4ECCbits

Lower 32bits data&

4ECCbits

36Bit

wide

RAM

36Bit wide RAM

36Bit

wide

RAM

36Bit wide RAM

Upper32bits data&

4ECCbits

Lower 32bits data&

4ECCbits

36Bit wide RAM

36Bit

wide RAM

36Bit wide RAM

36Bit

wide RAM

36Bit wide RAM

TCRAM

Interface1

CortexR4F™

TCM

TCRAM

Interface2

RM46L852

SPNS185 –SEPTEMBER 2012

4.11 Tightly-Coupled RAM Interface Module

Figure 4-11 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.

Figure 4-11. TCRAM Block Diagram

www.ti.com

4.11.1 Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

• Acts as slave to the Cortex-R4F CPU's BTCM interface

• Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code

• Monitors CPU Event Bus and generates single or multi-bit error interrupts

• Stores addresses for single and multi-bit errors

• Supports RAM trace module

• Provides CPU address bus integrity checking by supporting parity checking on the address bus

• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic

• Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks

• Supports auto-initialization of the RAM banks along with the ECC bits

4.11.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The TCRAMW monitors the CPU's event bus and provides registers for indicating single/multi-bit errors and also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information see the device Technical Reference Manual.

4.12 Parity Protection for Accesses to peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error.

Submit Documentation Feedback

Page 85

PRODUCTPREVIEW

RM46L852

www.ti.com

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM.

SPNS185 –SEPTEMBER 2012

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.

Submit Documentation Feedback

Page 86

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.13 On-Chip SRAM Initialization and Testing

4.13.1 On-Chip SRAM Self-Test Using PBIST

4.13.1.1 Features

• Extensive instruction set to support various memory test algorithms

• ROM-based algorithms allow application to run TI production-level memory tests

• Independent testing of all on-chip SRAM

4.13.1.2 PBIST RAM Groups

Memory RAM Group Test Clock MEM Type slow read fast read

PBIST_ROM 1 ROM CLK ROM X X

STC_ROM 2 ROM CLK ROM X X

DCAN1 3 VCLK Dual Port 25200 DCAN2 4 VCLK Dual Port 25200 DCAN3 5 VCLK Dual Port 25200

ESRAM1 6 HCLK Single Port 266280

MIBSPI1 7 VCLK Dual Port 33440 MIBSPI3 8 VCLK Dual Port 33440 MIBSPI5 9 VCLK Dual Port 33440

VIM 10 VCLK Dual Port 12560

MIBADC1 11 VCLK Dual Port 4200

DMA 12 HCLK Dual Port 18960

N2HET1 13 VCLK Dual Port 31680

HET TU1 14 VCLK Dual Port 6480

MIBADC2 18 VCLK Dual Port 4200

N2HET2 19 VCLK Dual Port 31680

HET TU2 20 VCLK Dual Port 6480

ESRAM5 21 HCLK Single Port 266280 ESRAM6 22 HCLK Single Port 266280

23 8700

ETHERNET 24 VCLK3 6360

25 Single Port 133160

USB VCLK3

(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for

application testing.

26 Dual Port 4240 27 Single Port 66600

Table 4-26. PBIST RAM Grouping

triple read triple read

ALGO MASK ALGO MASK ALGO MASK ALGO MASK

0x1 0x2 0x4 0x8

Dual Port

Test Pattern (Algorithm)

March 13N

two port single port

(cycles) (cycles)

(1)

www.ti.com

March 13N

(1)

The PBIST ROM clock frequency is limited to 100MHz, if 100MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

Submit Documentation Feedback

Page 87

PRODUCTPREVIEW

RM46L852

www.ti.com

4.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers see the device Technical Reference Manual. The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in

Table 4-27.

CONNECTING MODULE MSINENA REGISTER BIT #

RAM (PD#1) 0x08000000 0x0800FFFF 0 RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0 RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0

MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12 MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11 MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7

DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6

DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8

N2HET2 RAM 0xFF440000 0xFF57FFFF 15

N2HET1 RAM 0xFF460000 0xFF47FFFF 3 HET TU2 RAM 0xFF4C0000 0xFF4DFFFF 16 HET TU1 RAM 0xFF4E0000 0xFF4FFFFF 4

DMA RAM 0xFFF80000 0xFFF80FFF 1

VIM RAM 0xFFF82000 0xFFF82FFF 2

USB Device RAM RAM is not CPU-Addressable n/a

Ethernet RAM (CPPI Memory

(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized. (2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset..

This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method. The MibSPIx module must be first brought out of its local reset in order to use the system module auto-initialization method.

Slave)

SPNS185 –SEPTEMBER 2012

Table 4-27. Memory Initialization

ADDRESS RANGE

BASE ADDRESS ENDING ADDRESS

(1) (1) (1)

(2) (2)

(2)

0xFC520000 0xFC521FFF n/a

Submit Documentation Feedback

Page 88

PRODUCTPREVIEW

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[12:0]

EMIF_nOE

EMIF_DATA[15:0]

EMIF_nWE

5 9

4 8

EMIF_nDQM[1:0]

RM46L852

SPNS185 –SEPTEMBER 2012

4.14 External Memory Interface (EMIF)

4.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or SDRAM devices. The EMIF features includes support for:

• 3 addressable chip select for asynchronous memories of up to 32kB each

• 1 addressable chip select space for SDRAMs up to 128MB

• 8 or 16-bit data bus width

• Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time

• Select strobe mode

• Extended Wait mode

• Data bus parking

4.14.2 Electrical and Timing Specifications

4.14.2.1 Read Timing (Asynchronous RAM)

www.ti.com

Figure 4-12. Asynchronous Memory Read Timing

Submit Documentation Feedback

Page 89

PRODUCTPREVIEW

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[12:0]

EMIF_nWE

EMIF_DATA[15:0]

EMIF_nOE

EMIF_nDQM[1:0]

EMIF_nCS[3:2]

Asserted Deasserted

EMIF_BA[1:0]

EMIF_ADDR[12:0]

EMIF_DATA[15:0]

EMIF_nOE

EMIF_WAIT

SETUP

Extended Due to EMIF_WAIT

STROBE HOLD

STROBE

RM46L852

www.ti.com

Figure 4-13. EMIFnWAIT Read Timing Requirements

4.14.2.2 Write Timing (Asynchronous RAM)

SPNS185 –SEPTEMBER 2012

Figure 4-14. Asynchronous Memory Write Timing

Submit Documentation Feedback

Page 90

PRODUCTPREVIEW

EMIF_CLK

EMIF_BA[1:0]

EMIF_ADDR[12:0]

EMIF_DATA[15:0]

2 2

2 EM_CLK Delay

BASIC SDRAM

READ OPERATION

EMIF_nCS[0]

EMIF_nDQM[1:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

EMIF_nCS[3:2]

Asserted

EMIF_BA[1:0]

EMIF_ADDR[12:0]

EMIF_DATA[15:0]

EMIF_nWE

EMIF_WAIT

SETUP

Extended Due to EMIF_WAIT

Deasserted

STROBE STROBE HOLD

RM46L852

SPNS185 –SEPTEMBER 2012

Figure 4-15. EMIFnWAIT Write Timing Requirements

4.14.2.3 Read Timing (Synchronous RAM)

www.ti.com

Figure 4-16. Basic SDRAM Read Operation

Submit Documentation Feedback

Page 91

PRODUCTPREVIEW

EMIF_CLK

EMIF_BA[1:0]

EMIF_ADDR[12:0]

EMIF_DATA[15:0]

2 2

BASIC SDRAM

WRITE OPERATION

EMIF_CS[0]

EMIF_DQM[1:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

RM46L852

www.ti.com

4.14.2.4 Write Timing (Synchronous RAM)

SPNS185 –SEPTEMBER 2012

4.14.2.5 EMIF Asynchronous Memory Timing

NO. Value Unit

2 t

w(EM_WAIT)

12 t

su(EMDV-EMOEH)

13 t

h(EMOEH-EMDIV)

14 t

su(EMOEL-EMWAIT)

28 t

su(EMWEL-EMWAIT)

(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended

wait states. Figure Figure 4-13 and Figure Figure 4-15 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Figure 4-17. Basic SDRAM Write Operation

Table 4-28. EMIF Asynchronous Memory Timing Requirements

Pulse duration, EMIFnWAIT 2E ns assertion and deassertion

Setup time, EMIFDATA[15:0] 11 ns valid before EMIFnOE high

Hold time, EMIFDATA[15:0] 0.5 ns valid after EMIFnOE high

Setup Time, EMIFnWAIT 4E+3 ns asserted before end of Strobe Phase

(1)

Reads and Writes

Reads

Writes

MIN NOM MAX

Submit Documentation Feedback

Page 92

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

Table 4-29. EMIF Asynchronous Memory Switching Characteristics

NO Parameter Value Unit

1 t

d(TURNAROUND)

3 t

c(EMRCYCLE)

4 t

su(EMCEL-EMOEL)

5 t

h(EMOEH-EMCEH)

6 t

su(EMBAV-EMOEL)

7 t

h(EMOEH-EMBAIV)

8 t

su(EMBAV-EMOEL)

9 t

h(EMOEH-EMAIV)

10 t

w(EMOEL)

11 t

d(EMWAITH-EMOEH)

15 t

c(EMWCYCLE)

16 t

su(EMCEL-EMWEL)

17 t

h(EMWEH-EMCEH)

www.ti.com

(1)(2)(3)

MIN NOM MAX

Reads and Writes

Turn around time (TA)*E -3 (TA)*E (TA)*E + 3 ns

Reads

EMIF read cycle time (EW = 0) (RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)* ns

E -3 E E + 3

EMIF read cycle time (EW = 1) (RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+( ns

EWC*16))*E -3 EWC*16))*E EWC*16))*E +

Output setup time, (RS)*E-3 (RS)*E (RS)*E+3 ns EMIFnCS[4:2] low to EMIFnOE low (SS = 0)

Output setup time, -3 0 +3 ns EMIFnCS[4:2] low to EMIFnOE low (SS = 1)

Output hold time, EMIFnOE high (RH)*E -3 (RH)*E (RH)*E + 3 ns to EMIFnCS[4:2] high (SS = 0)

Output hold time, EMIFnOE high -3 0 +3 ns to EMIFnCS[4:2] high (SS = 1)

Output setup time, EMIFBA[1:0] (RS)*E-3 (RS)*E (RS)*E+3 ns valid to EMIFnOE low

Output hold time, EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns to EMIFBA[1:0] invalid

Output setup time, (RS)*E-3 (RS)*E (RS)*E+3 ns EMIFADDR[12:0] valid to EMIFnOE low

Output hold time, EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns to EMIFADDR[12:0] invalid

EMIFnOE active low width (EW (RST)*E-3 (RST)*E (RST)*E+3 ns = 0)

EMIFnOE active low width (EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16 ns = 1) )) *E-3 ))*E )) *E+3

Delay time from EMIFnWAIT 3E-3 4E 4E+3 ns deasserted to EMIFnOE high

Writes

EMIF write cycle time (EW = 0) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns

)* E-3 )*E )* E+3

EMIF write cycle time (EW = 1) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns

+( EWC*16))*E +(E WC*16))*E +( EWC*16))*E

-3 + 3

Output setup time, (WS)*E -3 (WS)*E (WS)*E + 3 ns EMIFnCS[4:2] low to EMIFnWE low (SS = 0)

Output setup time, -3 0 +3 ns EMIFnCS[4:2] low to EMIFnWE low (SS = 1)

Output hold time, EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns high to EMIFnCS[4:2] high (SS =

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],

WH[8–1], and MEWC[1–256]. See the EMIF User’s guide for more information. (2) E = EMIF_CLK period in ns. (3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note

that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See

Submit Documentation Feedback

Page 93

PRODUCTPREVIEW

RM46L852

www.ti.com

Table 4-29. EMIF Asynchronous Memory Switching Characteristics

(1)(2)(3)

SPNS185 –SEPTEMBER 2012

(continued)

NO Parameter Value Unit

MIN NOM MAX

Output hold time, EMIFnWE -3 0 +3 ns high to EMIFCS[4:2] high (SS =

18 t

su(EMDQMV-EMWEL)

19 t

h(EMWEH-EMDQMIV)

20 t

su(EMBAV-EMWEL)

21 t

h(EMWEH-EMBAIV)

22 t

su(EMAV-EMWEL)

Output setup time, EMIFBA[1:0] (WS)*E-3 (WS)*E (WS)*E+3 ns valid to EMIFnWE low

Output hold time, EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns high to EMIFBA[1:0] invalid

Output setup time, EMIFBA[1:0] (WS)*E-3 (WS)*E (WS)*E+3 ns valid to EMIFnWE low

Output hold time, EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns high to EMIFBA[1:0] invalid

Output setup time, (WS)*E-3 (WS)*E (WS)*E+3 ns EMIFADDR[12:0] valid to EMIFnWE low

23 t

24 t

h(EMWEH-EMAIV)

w(EMWEL)

Output hold time, EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns high to EMIFADDR[12:0] invalid

EMIFnWE active low width (EW (WST)*E-3 (WST)*E (WST)*E+3 ns = 0)

EMIFnWE active low width (EW (WST+(EWC*1 (WST+(EWC*1 (WST+(EWC*1 ns = 1) 6)) *E-3 6))*E 6)) *E+3

25 t

d(EMWAITH-EMWEH)

26 t

su(EMDV-EMWEL)

Delay time from EMIFnWAIT 3E-3 4E 4E+3 ns deasserted to EMIFnWE high

Output setup time, (WS)*E-3 (WS)*E (WS)*E+3 ns EMIFDATA[15:0] valid to EMIFnWE low

27 t

h(EMWEH-EMDIV)

Output hold time, EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns high to EMIFDATA[15:0] invalid

Table 4-30. EMIF Synchronous Memory Timing Requirements

NO. Parameter MIN MAX Unit

19 t

su(EMIFDV-EM_CLKH)

20 t

h(CLKH-DIV)

Table 4-31. EMIF Synchronous Memory Switching Characteristics

NO. Parameter MIN MAX Unit

1 t

c(CLK)

2 t

w(CLK)

3 t

d(CLKH-CSV)

4 t

oh(CLKH-CSIV)

5 t

d(CLKH-DQMV)

6 t

oh(CLKH-DQMIV)

7 t

d(CLKH-AV)

Input setup time, read data valid on 1 ns EMIFDATA[15:0] before EMIF_CLK rising

Input hold time, read data valid on 1.5 ns EMIFDATA[15:0] after EMIF_CLK rising

Cycle time, EMIF clock EMIF_CLK 10 ns Pulse width, EMIF clock EMIF_CLK 3 ns

high or low Delay time, EMIF_CLK rising to 7 ns

EMIFnCS[0] valid Output hold time, EMIF_CLK rising to 1 ns

EMIFnCS[0] invalid Delay time, EMIF_CLK rising to 7 ns

EMIFnDQM[1:0] valid Output hold time, EMIF_CLK rising to 1 ns

EMIFnDQM[1:0] invalid Delay time, EMIF_CLK rising to 7 ns

EMIFADDR[12:0] and EMIFBA[1:0] valid

Submit Documentation Feedback

Page 94

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

Table 4-31. EMIF Synchronous Memory Switching Characteristics (continued)

NO. Parameter MIN MAX Unit

8 t

9 t

10 t

11 t

12 t

13 t

14 t

15 t

16 t

17 t

18 t

oh(CLKH-AIV)

d(CLKH-DV)

oh(CLKH-DIV)

d(CLKH-RASV)

oh(CLKH-RASIV)

d(CLKH-CASV)

oh(CLKH-CASIV)

d(CLKH-WEV)

oh(CLKH-WEIV)

dis(CLKH-DHZ)

ena(CLKH-DLZ)

Output hold time, EMIF_CLK rising to 1 ns EMIFADDR[12:0] and EMIFBA[1:0] invalid

Delay time, EMIF_CLK rising to 7 ns EMIFDATA[15:0] valid

Output hold time, EMIF_CLK rising to 1 ns EMIFDATA[15:0] invalid

Delay time, EMIF_CLK rising to 7 ns EMIFnRAS valid

Output hold time, EMIF_CLK rising to 1 ns EMIFnRAS invalid

Delay time, EMIF_CLK rising to 7 ns EMIFnCAS valid

Output hold time, EMIF_CLK rising to 1 ns EMIFnCAS invalid

Delay time, EMIF_CLK rising to 7 ns EMIFnWE valid

Output hold time, EMIF_CLK rising to 1 ns EMIFnWE invalid

Delay time, EMIF_CLK rising to 7 ns EMIFDATA[15:0] tri-stated

Output hold time, EMIF_CLK rising to 1 ns EMIFDATA[15:0] driving

www.ti.com

Submit Documentation Feedback

Page 95

PRODUCTPREVIEW

RM46L852

www.ti.com

4.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).

4.15.1 VIM Features

The VIM module has the following features:

• Supports 128 interrupt channels. – Provides programmable priority and enable for interrupt request lines.

• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.

• Provides two software dispatch mechanisms when the CPU VIC port is not used. – Index interrupt – Register vectored interrupt

• Parity protected vector interrupt table against soft errors.

4.15.2 Interrupt Request Assignments

Table 4-32. Interrupt Request Assignments

SPNS185 –SEPTEMBER 2012

Modules Interrupt Sources Default VIM Interrupt

ESM ESM High level interrupt (NMI) 0

Reserved Reserved 1

RTI RTI compare interrupt 0 2 RTI RTI compare interrupt 1 3 RTI RTI compare interrupt 2 4 RTI RTI compare interrupt 3 5 RTI RTI overflow interrupt 0 6 RTI RTI overflow interrupt 1 7 RTI RTI timebase interrupt 8

GIO GIO interrupt A 9

N2HET1 N2HET1 level 0 interrupt 10

HET TU1 HET TU1 level 0 interrupt 11

MIBSPI1 MIBSPI1 level 0 interrupt 12

LIN LIN level 0 interrupt 13 MIBADC1 MIBADC1 event group interrupt 14 MIBADC1 MIBADC1 sw group 1 interrupt 15

DCAN1 DCAN1 level 0 interrupt 16

SPI2 SPI2 level 0 interrupt 17

Reserved Reserved 18

CRC CRC Interrupt 19 ESM ESM Low level interrupt 20

SYSTEM Software interrupt (SSI) 21

CPU PMU Interrupt 22

GIO GIO interrupt B 23

N2HET1 N2HET1 level 1 interrupt 24

HET TU1 HET TU1 level 1 interrupt 25

MIBSPI1 MIBSPI1 level 1 interrupt 26

Channel

Submit Documentation Feedback

Page 96

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

Modules Interrupt Sources Default VIM Interrupt

LIN LIN level 1 interrupt 27 MIBADC1 MIBADC1 sw group 2 interrupt 28

DCAN1 DCAN1 level 1 interrupt 29

SPI2 SPI2 level 1 interrupt 30 MIBADC1 MIBADC1 magnitude compare interrupt 31 Reserved Reserved 32

DMA FTCA interrupt 33

DMA LFSA interrupt 34

DCAN2 DCAN2 level 0 interrupt 35 MIBSPI3 MIBSPI3 level 0 interrupt 37 MIBSPI3 MIBSPI3 level 1 interrupt 38

DMA HBCA interrupt 39 DMA BTCA interrupt 40

EMIF AEMIFINT3 41 DCAN2 DCAN2 level 1 interrupt 42 DCAN1 DCAN1 IF3 interrupt 44 DCAN3 DCAN3 level 0 interrupt 45 DCAN2 DCAN2 IF3 interrupt 46

Reserved Reserved 47 Reserved Reserved 48

SPI4 SPI4 level 0 interrupt 49

MIBADC2 MibADC2 event group interrupt 50 MIBADC2 MibADC2 sw group1 interrupt 51 Reserved Reserved 52

MIBSPI5 MIBSPI5 level 0 interrupt 53

SPI4 SPI4 level 1 interrupt 54 DCAN3 DCAN3 level 1 interrupt 55

MIBSPI5 MIBSPI5 level 1 interrupt 56 MIBADC2 MibADC2 sw group2 interrupt 57 Reserved Reserved 58 MIBADC2 MibADC2 magnitude compare interrupt 59

DCAN3 DCAN3 IF3 interrupt 60

FMC FSM_DONE interrupt 61

Reserved Reserved 62

N2HET2 N2HET2 level 0 interrupt 63

SCI SCI level 0 interrupt 64

HET TU2 HET TU2 level 0 interrupt 65

I2C I2C level 0 interrupt 66

USB Host OHCI_INT 67

USB Device USB_FUNC.IRQISOON 68 USB Device USB_FUNC.IRQGENION 69 USB Device USB_FUNC.IRQNONISOON 70 USB Device not (USB_FUNC.DSWAKEREQON) 71 USB Device USB_FUNC.USBRESETO 72

N2HET2 N2HET2 level 1 interrupt 73

SCI SCI level 1 interrupt 74

HET TU2 HET TU2 level 1 interrupt 75

www.ti.com

Table 4-32. Interrupt Request Assignments (continued)

Channel

Submit Documentation Feedback

Page 97

PRODUCTPREVIEW

RM46L852

www.ti.com

Table 4-32. Interrupt Request Assignments (continued)

Modules Interrupt Sources Default VIM Interrupt

Ethernet C0_MISC_PULSE 76

Ethernet C0_TX_PULSE 77

Ethernet C0_THRESH_PULSE 78

Ethernet C0_RX_PULSE 79

HWAG1 HWA_INT_REQ_H 80 HWAG2 HWA_INT_REQ_H 81

DCC1 DCC done interrupt 82 DCC2 DCC2 done interrupt 83

Reserved Reserved 84

PBIST Controller PBIST Done Interrupt 85

Reserved Reserved 86-87

HWAG1 HWA_INT_REQ_L 88 HWAG2 HWA_INT_REQ_L 89

ePWM1INTn ePWM1 Interrupt 90

ePWM1TZINTn ePWM1 Trip Zone Interrupt 91

ePWM2INTn ePWM2 Interrupt 92

ePWM2TZINTn ePWM2 Trip Zone Interrupt 93

ePWM3INTn ePWM3 Interrupt 94

ePWM3TZINTn ePWM3 Trip Zone Interrupt 95

ePWM4INTn ePWM4 Interrupt 96

ePWM4TZINTn ePWM4 Trip Zone Interrupt 97

ePWM5INTn ePWM5 Interrupt 98

ePWM5TZINTn ePWM5 Trip Zone Interrupt 99

ePWM6INTn ePWM6 Interrupt 100

ePWM6TZINTn ePWM6 Trip Zone Interrupt 101

ePWM7INTn ePWM7 Interrupt 102

ePWM7TZINTn ePWM7 Trip Zone Interrupt 103

eCAP1INTn eCAP1 Interrupt 104 eCAP2INTn eCAP2 Interrupt 105 eCAP3INTn eCAP3 Interrupt 106 eCAP4INTn eCAP4 Interrupt 107 eCAP5INTn eCAP5 Interrupt 108

eCAP6INTn eCAP6 Interrupt 109 eQEP1INTn eQEP1 Interrupt 110 eQEP2INTn eQEP2 Interrupt 111

Reserved Reserved 112-127

SPNS185 –SEPTEMBER 2012

Channel

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..126 can be used and are offset by 1 address in the VIM RAM.

Submit Documentation Feedback

Page 98

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise" interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt condition is indicated as soon as the device is powered up. This can be ignored if the EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used in the application, then the external slave memory must always drive the EMIF_nWAIT signal such that an interrupt is not caused due to the default pull-up on this signal.

The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels.

The application can change the mapping of interrupt sources to the interrupt channels via the interrupt channel control registers (CHANCTRLx) inside the VIM module.

www.ti.com

NOTE

Submit Documentation Feedback

Page 99

PRODUCTPREVIEW

RM46L852

www.ti.com

4.16 DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to:

• Transfer blocks of data between external and internal data memories

• Restructure portions of internal data memory

• Continually service a peripheral

4.16.1 DMA Features

• CPU independent data transfer

• One 64-bit master port that interfaces to the TMS570 Memory System.

• FIFO buffer(4 entries deep and each 64bit wide)

• Channel control information is stored in RAM protected by parity

• 16 channels with individual enable

• Channel chaining capability

• 32 peripheral DMA requests

• Hardware and Software DMA requests

• 8, 16, 32 or 64-bit transactions supported

• Multiple addressing modes for source/destination (fixed, increment, offset)

• Auto-initiation

• Power-management mode

• Memory Protection with four configurable memory regions

SPNS185 –SEPTEMBER 2012

Submit Documentation Feedback

Page 100

PRODUCTPREVIEW

RM46L852

SPNS185 –SEPTEMBER 2012

4.16.2 Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in Table 4-33. The application must ensure that only one of these DMA request sources is enabled at any time.

Modules DMA Request Sources DMA Request

MIBSPI1 MIBSPI1[1] MIBSPI1 MIBSPI1[0]

SPI2 SPI2 receive DMAREQ[2]

SPI2 SPI2 transmit DMAREQ[3] MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4] MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]

DCAN1 / MIBSPI5 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6]

MIBADC1 / MIBSPI5 MIBADC1 event / MIBSPI5[3] DMAREQ[7] MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8] MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9]

MIBADC1 / I2C / MIBSPI5 MIBADC1 G1 / I2C receive / MIBSPI5[4] DMAREQ[10] MIBADC1 / I2C / MIBSPI5 MIBADC1 G2 / I2C transmit / MIBSPI5[5] DMAREQ[11]

MIBSPI3 / USB Device / MibADC2 / MIBSPI5 MIBSPI3[1]

RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12] RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13]

MIBSPI3 / USB Device / MIBSPI5 MIBSPI3[0]

MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2 MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1 DMAREQ[16] MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2 MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2 DMAREQ[17]

RTI / USB Device / MIBSPI5 RTI DMAREQ2 / USB_FUNC.DMATXREQ_ON[1] / DMAREQ[18]

RTI / USB Device / MIBSPI5 RTI DMAREQ3 / USB_FUNC.DMARXREQ_ON[1] / DMAREQ[19]

N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 DMAREQ[20]

N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 DMAREQ[21]

MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10] DMAREQ[22] MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11] DMAREQ[23]

N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 DMAREQ[24]

N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 DMAREQ[25]

CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26] CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27]

LIN / USB Device / MIBSPI5 LIN receive / USB_FUNC.DMATXREQ_ON[2] / DMAREQ[28]

LIN / USB Device / MIBSPI5 LIN transmit / USB_FUNC.DMARXREQ_ON[2] / DMAREQ[29]

MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[14] / MIBSPI3[14] / SCI receive / DMAREQ[30]

Table 4-33. DMA Request Line Connection

(1) (2)

(1)

/ USB_FUNC.DMATXREQ_ON[0] / DMAREQ[14]

MibADC2 event / MIBSPI5[6]

(2)

/ USB_FUNC.DMARXREQ_ON[0] / DMAREQ[15]

MIBSPI5[7]

MIBSPI5[8]

MIBSPI5[9]

IF2

IF3

receive / MIBSPI5[12]

transmit / MIBSPI5[13]

MIBSPI5[14]

MIBSPI5[15]

MIBSPI5[1]

(1)

www.ti.com

DMAREQ[0] DMAREQ[1]

(1) SPI1, SPI3, SPI5 receive when configured in standard SPI mode (2) SPI1, SPI3, SPI5 transmit when configured in standard SPI mode

Submit Documentation Feedback

Texas Instruments RM46L852 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 RM46L852 16/32-Bit RISC Flash Microcontroller

1.1 Features

1.2 Applications

1.3 Description

1.4 Functional Block Diagram

2 Device Package and Terminal Functions

2.1 PGE QFP Package Pinout (144-Pin)

2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)

2.3 Terminal Functions

2.3.1 PGE Package

2.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

2.3.1.2 Enhanced High-End Timer Modules (N2HET) Table 2-2. PGE Enhanced High-End Timer Modules (N2HET)

2.3.1.3 Enhanced Capture Modules (eCAP)

2.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

2.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

2.3.1.6 General-Purpose Input / Output (GIO)

2.3.1.7 Controller Area Network Controllers (DCAN) Table 2-7. PGE Controller Area Network Controllers (DCAN)

2.3.1.8 Local Interconnect Network Interface Module (LIN)

2.3.1.9 Standard Serial Communication Interface (SCI)

2.3.1.10 Inter-Integrated Circuit Interface Module (I2C)

2.3.1.11 Standard Serial Peripheral Interface (SPI)

2.3.1.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

2.3.1.13 Ethernet Controller

2.3.1.14 USB Host Port Controller Interface

2.3.1.15 System Module Interface

2.3.1.16 Clock Inputs and Outputs

2.3.1.17 Test and Debug Modules Interface

2.3.1.18 Flash Supply and Test Pads

2.3.1.19 Supply for Core Logic: 1.2V nominal

2.3.1.20 Supply for I/O Cells: 3.3V nominal

2.3.1.21 Ground Reference for All Supplies Except VCCAD

2.3.2 ZWT Package

2.3.2.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

2.3.2.2 Enhanced High-End Timer Modules (N2HET)

2.3.2.3 Enhanced Capture Modules (eCAP)

2.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

2.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)

2.3.2.6 General-Purpose Input / Output (GIO)

2.3.2.7 Controller Area Network Controllers (DCAN)

2.3.2.8 Local Interconnect Network Interface Module (LIN)

2.3.2.9 Standard Serial Communication Interface (SCI)

2.3.2.10 Inter-Integrated Circuit Interface Module (I2C)

2.3.2.11 Standard Serial Peripheral Interface (SPI)

2.3.2.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

2.3.2.13 Ethernet Controller

2.3.2.14 USB Host Port Controller Interface

2.3.2.15 External Memory Interface (EMIF)

2.3.2.16 System Module Interface

2.3.2.17 Clock Inputs and Outputs

2.3.2.18 Test and Debug Modules Interface

2.3.2.19 Flash Supply and Test Pads

2.3.2.20 No Connects

2.3.2.21 Supply for Core Logic: 1.2V nominal

2.3.2.22 Supply for I/O Cells: 3.3V nominal

2.3.2.23 Ground Reference for All Supplies Except VCCAD

3 Device Operating Conditions

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range,

3.2 Device Recommended Operating Conditions

3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains

3.4 Wait States Required

3.5 Power Consumption Over Recommended Operating Conditions

3.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions

3.7 Output Buffer Drive Strengths

3.8 Input Timings

3.9 Output Timings

3.10 Low-EMI Output Buffers

4 System Information and Electrical Specifications

4.1 Device Power Domains

4.2 Voltage Monitor Characteristics

4.2.1 Important Considerations

4.2.2 Voltage Monitor Operation

4.2.3 Supply Filtering

4.3 Power Sequencing and Power On Reset

4.3.1 Power-Up Sequence

4.3.2 Power-Down Sequence

4.3.3 Power-On Reset: nPORRST