Texas Instruments RF430FRL152H, RF430FRL153H, RF430FRL154H Datasheet
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
RF430FRL15xH NFC ISO 15693 Sensor Transponder
1 Device Overview
1.1 Features
1
• ISO/IEC 15693, ISO/IEC 18000-3 (Mode 1)
Compliant RF Interface
• Power Supply System With Either Battery or
13.56-MHz H-Field Supply
• 14-Bit Sigma-Delta Analog-to-Digital Converter
(ADC)
• Internal Temperature Sensor
• Resistive Sensor Bias Interface
• CRC16 CCITT Generator
• MSP430™ Mixed-Signal Microcontroller
– 2KB of FRAM
– 4KB of SRAM
– 8KB of ROM
– Supply Voltage Range: 1.45 V to 1.65 V
– Low Power Consumption
• Active Mode (AM): 140 µA/MHz (1.5 V)
• Standby Mode (LPM3): 16 µA
– 16-Bit RISC Architecture
– Up to 2-MHz CPU System Clock
– Compact Clock System
• 4-MHz High-Frequency Clock
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
• 256-kHz Internal Low-Frequency Clock
Source
• External Clock Input
– 16-Bit Timer_A With Three Capture/Compare
Registers
– LV Port Logic
• VOLLower Than 0.15 V at 400 µA
• VOHHigher Than (V
– 0.15 V) at 400 µA
DDB
• Timer_A PWM Signal Available on All Ports
– eUSCI_B Module Supports 3-Wire and 4-Wire
SPI and I2C
– 32-Bit Watchdog Timer (WDT_A)
– ROM Development Mode (Map ROM Addresses
to SRAM to Enable Firmware Development)
– Full 4-Wire JTAG Debug Interface
• For Complete Module Descriptions, See the
RF430FRL15xH Family Technical Reference
Manual (SLAU506)
• For Application Operation and Programming, See
the RF430FRL15xH Firmware User's Guide
(SLAU603)
1.2 Applications
• Industrial Wireless Sensors • Medical Wireless Sensors
1.3 Description
The RF430FRL15xH device is a 13.56-MHz transponder chip with a programmable 16-bit MSP430™ lowpower microcontroller. The device features embedded universal FRAM nonvolatile memory for storage of
program code or user data such as calibration and measurement data. The RF430FRL15xH supports
communication, parameter setting, and configuration through the ISO/IEC 15693, ISO/IEC 18000-3
compliant RFID interface and the SPI or I2C interface. Sensor measurements are supported by the
internal temperature sensor and the onboard 14-bit sigma-delta analog-to-digital converter (ADC), and
digital sensors can be connected through SPI or I2C.
The RF430FRL15xH device is optimized for operation in fully passive (battery-less) or single-cell batterypowered (semi-active) mode to achieve extended battery life in portable and wireless sensing applications.
FRAM is a nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the
stability and reliability of flash, all at lower total power consumption.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
eUSCI_B0
SPI
I C
2
8KB
ROM
CPU and
Working
Registers
4W-JTAG
Reset
Int-Logic
VDDB
TMS, TCK,
TDI, TDO
P1.0 to P1.7
RST/NMI
Debug
support
ANT
1
ANT
2
VSS
VDDH
CLKIN
VDDSW
VDD2X
CP1
CP2
VDDD
4KB
RAM
2KB
FRAM
CRC
16 bit
Timer_A
3 CC
Registers
IO Port
8 I/Os
with
interrupt
capability
14-Bit
Sigma-
Delta
ADC
ISO
15693
Decode
and
Encode
Watchdog
WDTA
32/16 Bit
ISO
15693
Analog
Front End
Power
Supply
System
MAB
LF-OSC
HF-OSC
ACLK
SMCLK
MCLK
Clock
System
C
RES
L
RES
ADC0/ADC1/ADC2
TEMP1/TEMP2
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com
PART NUMBER PACKAGE BODY SIZE
RF430FRL152H VQFN (24) 4 mm x 4 mm
RF430FRL153H VQFN (24) 4 mm x 4 mm
RF430FRL154H VQFN (24) 4 mm x 4 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI web site at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
1.4 Functional Block Diagram
Figure 1-1 shows the block diagram of the RF430FRL15xH device.
Device Information
(1)
(2)
2 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
Table of Contents
1 Device Overview ......................................... 1 5.18 RFPMM, Power Supply Switch ..................... 19
1.1 Features .............................................. 1 5.19 RFPMM, Bandgap Reference....................... 19
1.2 Applications........................................... 1 5.20 RFPMM, Voltage Doubler........................... 19
1.3 Description............................................ 1 5.21 RFPMM, Voltage Supervision ...................... 19
1.4 Functional Block Diagram ............................ 2 5.22 SD14, Performance ................................. 20
2 Revision History ......................................... 4 5.23 SVSS Generator .................................... 20
3 Device Comparison ..................................... 5 5.24 Thermistor Bias Generator.......................... 21
4 Terminal Configuration and Functions.............. 6 5.25 Temperature Sensor ................................ 21
4.1 Pin Diagram .......................................... 6
4.2 Signal Descriptions ................................... 7
4.3 Pin Multiplexing....................................... 9
4.4 Connections for Unused Pins ........................ 9
5 Specifications........................................... 10
5.1 Absolute Maximum Ratings ........................ 10
5.2 ESD Ratings ........................................ 10
5.3 Recommended Operating Conditions............... 10
5.4 Recommended Operating Conditions, Resonant
Circuit................................................ 11 6.5 Memory.............................................. 26
5.5 Active Mode Supply Current Into V
External Current .................................... 11
5.6 Low-Power Mode Supply Current (Into V
Excluding External Current.......................... 11
5.7 Digital I/Os (P1, RST/NMI).......................... 12
5.8 High-Frequency Oscillator (4 MHz), HFOSC ....... 12
5.9 Low-Frequency Oscillator (256 kHz), LFOSC ...... 12
5.10 Wake-Up From Low-Power Modes ................. 13
5.11 Timer_A ............................................. 13
5.12 eUSCI (SPI Master Mode) Recommended
Operating Conditions................................ 14
5.13 eUSCI (SPI Master Mode) .......................... 14
5.14 eUSCI (SPI Slave Mode) ........................... 16
5.15 eUSCI (I
5.16 FRAM................................................ 18
5.17 JTAG ................................................ 18
2
C Mode)................................... 18
DDB
Excluding
)
DDB
5.26 RF13M, Power Supply and Recommended
Operating Conditions................................ 21
5.27 RF13M, ISO/IEC 15693 ASK Demodulator......... 21
5.28 RF13M, ISO/IEC 15693 Compliant Load Modulator 21
6 Detailed Description ................................... 22
6.1 CPU ................................................. 22
6.2 Instruction Set....................................... 22
6.3 Operating Modes.................................... 23
6.4 Interrupt Vector Addresses.......................... 24
6.6 Peripherals .......................................... 27
6.7 Port Schematics..................................... 33
6.8 Device Descriptors (TLV) ........................... 41
7 Applications, Implementation, and Layout ....... 42
8 Device and Documentation Support ............... 43
8.1 Device Support...................................... 43
8.2 Documentation Support ............................. 44
8.3 Related Links........................................ 44
8.4 Community Resources .............................. 45
8.5 Trademarks.......................................... 45
8.6 Electrostatic Discharge Caution..................... 45
8.7 Glossary............................................. 45
9 Mechanical Packaging and Orderable
Information .............................................. 45
9.1 Packaging Information .............................. 45
Copyright © 2012–2014, Texas Instruments Incorporated Table of Contents 3
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from November 13, 2014 to December 8, 2014 Page
• Corrected all instances of the title of the RF430FRL15xH Family Technical Reference Manual .......................... 1
• Corrected all instances of the title of the RF430FRL15xH Firmware User's Guide ......................................... 1
• Moved T
• Changed title of Section 5.2 to ESD Ratings.................................................................................... 10
to Absolute Maximum Ratings table ................................................................................ 10
stg
4 Revision History Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
www.ti.com
3 Device Comparison
Table 3-1 summarizes the available family members.
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
Table 3-1. Device Comparison
Device Timer ISO/IEC 15693 eUSCI_B SD14
RF430FRL152H 2 4 Yes Yes Yes Yes
RF430FRL153H 2 4 Yes Yes No Yes
RF430FRL154H 2 4 Yes Yes Yes No
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9,
or see the TI web site at www.ti.com.
FRAM SRAM
(KB) (KB)
(1)
13.56-MHz
Front End
Copyright © 2012–2014, Texas Instruments Incorporated Device Comparison 5
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
VSS
Exposed die
attached pad
ADC2/TEMP2
SVSS
ADC1/TEMP1
TST1
TST2
ADC0
VDD2X
P1.3/SPI_STE/TA0.2/ACLK/TA0CLK
P1.2/SPI_CLK/MCLK/TA0.0
RST/NMI
P1.1/SPI_SOMI/SCL/ACLK/TA0.2/CCI0.0
VDDD
VDDH
TCK/P1.4/TA0.1/SMCLK/CCI0.1
TDI/P1.5/TA0.2/MCLK/CCI0.1
TDO/P1.6/TA0.0/TA0.2/CCI0.2
TMS/P1.7/TA0.1/TA0.0/CCI0.2
ANT1
VDDB
ANT2
VDDSW
CP1
CP2
1
2
3
4
5
6
18
17
16
15
14
13
7 8 9 10 11 12
24 23 22 21 20 19
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the pin assignments on the 24-pin RGE package.
www.ti.com
Figure 4-1. 24-Pin RGE Package (Top View)
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Submit Documentation Feedback
6 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
4.2 Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Signal Descriptions
TERMINAL
NAME NO.
ANT1 1 I Antenna input 1
ANT2 2 I Antenna input 2
V
V
DDSW
DDB
3 Switched supply voltage
4 Battery supply voltage
CP1 5 Charge pump flying cap terminal 1
CP2 6 Charge pump flying cap terminal 2
V
DD2X
7 Voltage doubler output
P1.3 General-purpose digital I/O
SPI_STE SPI slave transmit enable
TA0.2 Timer_A TA0 OUT2 output
8 I/O
ACLK ACLK output (divided by 1, 2, 4, 8, 16, or 32)
TA0CLK Timer_A TA0 clock signal TA0CLK input
I/O
(1)
DESCRIPTION
P1.2 General-purpose digital I/O
SPI_CLK SPI clock
9 I/O
MCLK MCLK output
TA0.0 Timer_A TA0 OUT0 output
RST/NMI 10 I
Reset input active low
Non-maskable interrupt input
P1.1 General-purpose digital I/O
SPI_SOMI SPI slave out master in
SCL I2C clock
11 I/O
ACLK ACLK output (divided by 1, 2, 4, or 8 )
TA0.2 Timer_A TA0 OUT2 output
CCI0.0 Timer_A TA0 CCR0 capture: CCI0B input, compare
P1.0 General-purpose digital I/O
SPI_SIMO SPI slave in master out
SDA I2C data
12 I/O
SMCLK SMCLK output
TA0.1 Timer0_A3 OUT1 output
CCI0.0 Timer_A TA0 CCR0 capture: CCI0A input, compare
ADC0 13 I ADC input pin 0
TST2 14 Internal; connect to GND
SVSS 15 Sensor reference potential
TST1 16 Internal; connect to GND
ADC1 / TEMP1 17 ADC input pin 1 / Resistive bias pin 1
ADC2 / TEMP2 18 ADC input pin 2 / Resistive bias pin 2
(1) I = input, O = output
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 7
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME NO.
TMS JTAG test mode select
P1.7 General-purpose digital I/O
TA0.1 Timer_A TA0 OUT1 output
19 I/O
TA0.0 Timer_A TA0 OUT0 output
CCI0.2 Timer_A TA0 CCR2 capture: CCI2B input, compare
TDO JTAG test data output
P1.6 General-purpose digital I/O
TA0.0 Timer_A TA0 OUT0 output
20 I/O
TA0.2 Timer_A TA0 OUT2 output
CCI0.2 Timer_A TA0 CCR2 capture: CCI2A input, compare
TDI JTAG test data input
P1.5 General-purpose digital I/O
TA0.2 Timer_A TA0 OUT2 output
21 I/O
MCLK MCLK output
CCI0.1 Timer_A TA0 CCR1 capture: CCI1B input, compare
I/O
(1)
DESCRIPTION
www.ti.com
TCK JTAG test clock
P1.4 General-purpose digital I/O
TA0.1 Timer_A TA0 OUT1 output
22 I/O
SMCLK SMCLK output
CCI0.1 Timer_A TA0 CCR1 capture: CCI1A input, compare
CLKIN External clock input pin
V
DDH
V
DDD
V
SS
23 O Rectified voltage from RF-AFE
24 Digital supply voltage
Pad Ground reference, bonded to exposed pad
(2)
(2) VSS combines both digital ground (DVSS) and analog ground (AVSS)
8 Terminal Configuration and Functions Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
4.3 Pin Multiplexing
The GPIO port pins are multiplexed with other functions including analog peripherals and serial
communication modules. The pin functions are selected by a combination of register values and device
modes. For schematics of the port pins and details of the multiplexing for each, refer to Section 6.7.
4.4 Connections for Unused Pins
The correct termination of all unused pins is listed in Table 4-2.
Table 4-2. Connection of Unused Pins
Pin Potential Comment
TDI/TMS/TCK Open When used for JTAG function
RST/NMI VCCor V
Px.0 to Px.7 Open Set to port function, output direction
TDO Open Convention: leave TDO terminal as JTAG function
SS
10-nF capacitor to GND/V
SS
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 9
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
5 Specifications
www.ti.com
5.1 Absolute Maximum Ratings
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
Voltage applied at V
Voltage applied at V
Voltage applied to any pin (references to VSS) -0.3 V
Diode current at any device pin
Current derating factor when I/O ports are switched in parallel electrically and logically
Storage temperature range, T
referenced to VSS(V
DDB
referenced to VSS(V
ANT
(2)
(4) (5) (6)
stg
) -0.3 1.65 V
AMR
) -0.3 3.6 V
AMR
+ 0.3 V
DDB
±2 mA
(3)
0.9
-40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS.
(3) The diode current increases to ±4.5 mA when two pins are connected, it increases to ±6.75 mA when three pins are connected, and so
on.
(4) Soldering during board manufacturing must follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher
than classified on the device label on the shipping boxes or reels. If hand soldering is required for application prototyping, peak
temperature must not exceed 250°C for a total of 5 minutes for any single device.
(5) Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, T
(6) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
.
stg
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
5.2 ESD Ratings
VALUE UNIT
V
ESD
Electrostatic discharge (ESD)
performance
Human body model (HBM), per ANSI/ESDA/JEDEC JS001
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Low leakage pin: ADC0 has reduced ESD tolerance of ±500 V HBM.
(1)(2)
±2000 V
5.3 Recommended Operating Conditions
Typical data are based on V
V
DDB
V
SS
T
A
C
VDDB
C
VDDSW
C
FLY
C
VDD2X
C
VDDD
C
SVSS
f
SYSTEM
f
CLKIN
(1) Low equivalent series resistance (ESR) capacitor
(2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Supply voltage during program execution 1.45 1.65 V
Supply voltage (GND reference) 0 V
Operating free-air temperature 0 70 °C
Capacitor on V
Capacitor on V
Charge pump capacitor between CP1 and CP2.
Recommended ratio between C
Capacitor on V
Recommended ratio between C
Capacitor on V
Capacitor between SVSS and V
System frequency
External clock input frequency 32 kHz
= 1.5 V, TA= 25°C (unless otherwise noted)
DDB
(1)
DDB
(1)
DDSW
DD2x
DDD
.
(1)
(2) (3)
FLY
FLY
SS
and C
and C
(1)
VDD2X
VDD2X
is ≥ 1:10.
is ≥ 1:10.
MIN NOM MAX UNIT
100 nF
2.2 µF
(1)
(1)
10 nF
100 nF
1 µF
1 µF
2 MHz
10 Specifications Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
5.4 Recommended Operating Conditions, Resonant Circuit
MIN NOM MAX UNIT
f
c
V
ANT_peak
Z Impedance of LC circuit 6.5 15.5 kΩ
L
RES
C
RES
QT Tank quality factor 30
(1) See the RF13M parameter section.
Carrier frequency 13.56 MHz
Antenna input voltage 3.6 V
Coil inductance 2.66 µH
Resonance capacitance 51.8 – C
(1)
IN
pF
5.5 Active Mode Supply Current Into V
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER V
EXECUTION
MEMORY
Excluding External Current
DDB
(1)
Frequency (f
DDB
1 MHz 2 MHz UNIT
MCLK
= f
SMCLK
TYP MAX TYP MAX
I
AM, FRAM
I
AM, RAM
I
AM, ROM
(2)
(2)
(2)
FRAM 1.5 V 330 420 480 580 µA
RAM 1.5 V 220 300 250 320 µA
ROM 1.5 V 220 300 230 300 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) f
5.6 Low-Power Mode Supply Current (Into V
= 256 kHz, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
ACLK
) Excluding External Current
DDB
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
0ºC 20ºC 45ºC 70ºC
TYP MAX TYP MAX TYP MAX TYP MAX
I
LPM0
PARAMETER V
f
= off, f
MCLK
(2)
1 MHz, f
ACLK
CPUOFF = 1, SCG0 = 0,
SMCLK
= 32 kHz,
=
DDB
1.5 V 170 230 190 210 260 340 µA
SCG1 = 0, OSCOFF = 0
f
I
LPM3
= f
MCLK
f
(3)
= 16 kHz,
ACLK
CPUOFF = 1, SCG0 = 1,
SMCLK
= off,
1.5 V 12 20 13 16 25 65 µA
SCG1 = 1, OSCOFF = 0
f
I
LPM4
= f
MCLK
(4)
0 Hz
CPUOFF = 1, SCG0 = 1,
SMCLK
= f
ACLK
=
1.5 V 11 16 12 15 24 60 µA
SCG1 = 1, OSCOFF = 1
(1) Including current for WDT clocked by ACLK.
(2) CSS: SELM=SELS=HF_CLK, SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/4 (1MHz), DIVA=/8 (32kHz)
SD14: reset values
RFPMM: battery switch on (EN_BATSWITCH=1)
(3) CSS: SELM=HF_CLK, SELS=SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/32 (8kHz), DIVA=/16 (16kHz)
SD14: reset values
RFPMM: EN_BATSWITCH=1(battery switch enabled)
(4) CSS: SELM=HF_CLK, SELS=SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/32 (8kHz), DIVA=/16 (16kHz)
SD14: reset values
RFPMM: EN_BATSWITCH=1(battery switch enabled)
)
(1)
UNIT
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 11
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com
5.7 Digital I/Os (P1, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
V
V
V
I
I
I
t
R
R
R
C
OH
OL
IH
IL
OH
OL
LKG
INT
PULL
RST
EXT
EXT
High-level output voltage V
Low-level output voltage V
High-level input voltage V
Low-level input voltage V
High-level output current V
Low-level output current V
High-impedance leakage current V
External interrupt timing
(3)
Pullup or pulldown resistor 30 35 40 kΩ
= 1.5 V, IOH= -400 µA
DDB
= 1.5 V, IOL= 400 µA
DDB
= 1.5 V V
DDB
= 1.5 V V
DDB
= 1.45 V to 1.65 V for port P1 -400 µA
DDB
= 1.45 V to 1.65 V for port P1 400 µA
DDB
= 1.45 V to 1.65 V -100 100 nA
DDB
P1.x, V
V
DDB
For pulldown: VIN= V
= 1.45 V to 1.65 V 200 ns
DDB
=1.5 V, For pullup: VIN= VSS,
Pullup on RST/NMI 30 35 40 kΩ
External pullup resistor on RST
terminal (optional)
External capacitor on RST terminal 10 nF
(1)
for port P1 V
(2)
for port P1 0.15 V
for port P1
DDB
(1) The maximum total current IOH, for all outputs combined should not exceed 500 µA to hold the maximum voltage drop specified, limited
by low leakage switches.
(2) The maximum total current IOL, for all outputs combined should not exceed 500 µA to hold the maximum voltage drop specified.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t
INT
is met.
V
DDB
– 0.15
0.7 ×
V
DDB
0.3 ×
V
DDB
47 kΩ
5.8 High-Frequency Oscillator (4 MHz), HFOSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
HFOSC
Duty cycle 45% 50% 55%
t
START
±20% 3.04 3.8 4.56 MHz
1 µs
5.9 Low-Frequency Oscillator (256 kHz), LFOSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
LFO
Duty cycle 45% 50% 55%
t
START
trimmed ±5% 243 256 269 kHz
11 µs
12 Specifications Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
5.10 Wake-Up From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t
WAKE-UP LPM0
t
WAKE-UP LPM34
t
WAKE-UP RESET
PARAMETER TEST CONDITIONS V
Wake-up time from LPM0 to active
(1)
mode
Wake-up time from LPM3 or LPM4 to
active mode
Wake-up time from RST to active
mode.
(1)
V
(2)
stable 1.5 V 210 310 µs
DDB
DDB
1.5 V 3.2 6 µs
1.5 V 160 260 µs
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is fetched. This time includes the activation of the FRAM during wake-up. f
(2) The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is fetched. This time
includes the activation of the FRAM during wake-up. f
MCLK
= 2 MHz.
MIN TYP MAX UNIT
= 2 MHz.
MCLK
5.11 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f
TA
t
TA,cap
PARAMETER TEST CONDITIONS V
DDB
Internal: SMCLK, ACLK
Timer_A input clock frequency External: TACLK 1.5 V 4 MHz
Duty cycle = 50% ± 10%
Timer_A capture timing 1.5 V 20 ns
All capture inputs, Minimum pulse
duration required for capture
MIN TYP MAX UNIT
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 13
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com
5.12 eUSCI (SPI Master Mode) Recommended Operating Conditions
f
eUSCI
PARAMETER CONDITIONS V
eUSCI input clock frequency 1.5 V f
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
DDB
MIN TYP MAX UNIT
SYSTEM
MHz
5.13 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
UCSTEM = 0,
t
STE,LEAD
STE lead time, STE active to clock
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
t
STE,LAG
STE lag time, Last clock to STE UCxCLK
inactive cycles
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
t
STE,ACC
STE access time, STE active to SIMO
data out
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
t
STE,DIS
STE disable time, STE inactive to
SIMO high impedance
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
t
SU,MI
t
HD,MI
t
VALID,MO
t
HD,MO
(1) f
For the slave's parameters t
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
SOMI input data setup time 1.5 V 35 ns
SOMI input data hold time 1.5 V 0 ns
SIMO output data valid time
SIMO output data hold time
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
= max(t
SU,SI(Slave)
(2)
(3)
VALID,MO(eUSCI)
and t
UCLK edge to SIMO valid,
CL= 20 pF
CL= 20 pF 1.5 V 0 ns
+ t
VALID,SO(Slave)
SU,SI(Slave)
, t
SU,MI(eUSCI)
see the SPI parameters of the attached slave.
+ t
VALID,SO(Slave)
DDB
1.5 V 1
1.5 V 1
1.5 V 1
1.5 V 1
1.5 V 55
1.5 V 35
1.5 V 40
1.5 V 30
1.5 V 30 ns
).
in Figure 5-1 and Figure 5-2.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
1 and Figure 5-2.
MIN TYP MAX UNIT
(1)
UCxCLK
cycles
ns
ns
14 Specifications Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
CKPL = 0
CKPL = 1
t
LOW/HIGHtLOW/HIGH
1/f
UCxCLK
t
STE,LEAD
t
STE,LAG
t
STE,ACC
t
STE,DIS
UCMODEx = 01
UCMODEx = 10
STE
t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
CKPL = 0
CKPL = 1
t
LOW/HIGHtLOW/HIGH
1/f
UCxCLK
STE
t
STE,LEAD
t
STE,LAG
t
STE,ACC
t
STE,DIS
UCMODEx = 01
UCMODEx = 10
www.ti.com
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
Figure 5-1. SPI Master Mode, CKPH = 0
Figure 5-2. SPI Master Mode, CKPH = 1
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 15
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Submit Documentation Feedback
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com
5.14 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
t
STE,LEAD
t
STE,LAG
t
STE,ACC
t
STE,DIS
t
SU,SI
t
HD,SI
t
VALID,SO
t
HD,SO
(1) f
For the master's parameters t
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
STE lead time, STE active to clock 1.5 V 7 ns
STE lag time, Last clock to STE inactive 1.5 V 0 ns
STE access time, STE active to SOMI data out 1.5 V 65 ns
STE disable time, STE inactive to SOMI high
impedance
SIMO input data setup time 1.5 V 2 ns
SIMO input data hold time 1.5 V 5 ns
SOMI output data valid time
SOMI output data hold time
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
(2)
(3)
≥ max(t
VALID,MO(Master)
SU,MI(Master)
and t
VALID,MO(Master)
UCLK edge to SOMI valid,
CL= 20 pF
CL= 20 pF 1.5 V 4 ns
+ t
SU,SI(eUSCI)
, t
SU,MI(Master)
see the SPI parameters of the attached slave.
+ t
VALID,SO(eUSCI)
in Figure 5-3 and Figure 5-4.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-3
and Figure 5-4.
DDB
1.5 V 40 ns
1.5 V 30 ns
).
(1)
MIN TYP MAX UNIT
16 Specifications Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
LOW/HIGH
1/f
UCxCLK
t
LOW/HIGH
t
DIS
t
ACC
STE
t
STE,LEAD
t
STE,LAG
UCMODEx = 01
UCMODEx = 10
UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SIMO
t
HD,SIMO
t
VALID,SOMI
t
LOW/HIGH
1/f
UCxCLK
t
LOW/HIGH
t
DIS
t
ACC
STE
t
STE,LEAD
t
STE,LAG
UCMODEx = 01
UCMODEx = 10
www.ti.com
RF430FRL152H, RF430FRL153H, RF430FRL154H
SLAS834C –NOVEMBER 2012–REVISED DECEMBER 2014
Figure 5-3. SPI Slave Mode, CKPH = 0
Figure 5-4. SPI Slave Mode, CKPH = 1
Copyright © 2012–2014, Texas Instruments Incorporated Specifications 17
Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H
Submit Documentation Feedback
Loading...