TEXAS INSTRUMENTS PTH03060Y Technical data

(25,4 mm x 15,75 mm)

NOMINAL SIZE
1 in. x 0.62 in

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PTH03060Y

PTH05060Y, PTH12060Y

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SLTS222A–MARCH 2004 – REVISED OCTOBER 2005

10-A NON-ISOLATED DDR/QDR

MEMORY BUS TERMINATION MODULES

FEATURES

• VTTBus Termination Output • 57 W/in3Power Density
(Output Tracks the System V

• 10 A Output Current UL/cUL60950, EN60950, VDE

• 3.3-V, 5-V or 12-V Input Voltage • Point-of-Load Alliance (POLA™) Compatible

• DDR and QDR Compatible

• On/Off Inhibit (for VTTStandby)

• Undervoltage Lockout

• Operating Temperature: –40°Cto85°C

• Efficiencies up to 91%

• Output Overcurrent Protection (Non-Latching,

Auto-Reset)

DESCRIPTION

The PTHxx060Y are a series of ready-to-use switching regulator modules from Texas Instruments designed
specifically for bus termination in DDR and QDR memory applications. Operating from either a 3.3-V, 5-V or 12-V
input, the modules generate a VTToutput that will source or sink up to 10 A of current to accurately track their
V

input. VTTis the required bus termination supply voltage, and V

REF

and chipset bus receiver comparators. V

Both the PTHxx060Y series employs an actively switched synchronous rectifier output to provide state-of-the-art
stepdown switching conversion. The products are small in size (1 in × 0.62 in), and are an ideal choice where
space, performance, and high efficiency are desired, along with the convenience of a ready-to-use module.

Operating features include an on/off inhibit and output over-current protection (source mode only). The on/off
inhibit feature allows the VTTbus to be turned off to save power in a standby mode of operation. To ensure tight
load regulation, an output remote sense is also provided. Package options include both throughhole and surface
mount configurations.

REF

)

is usually set to half the V

REF

• Safety Agency Approvals:

is the reference voltage for the memory

REF

power supply voltage.

DDQ

V

IN

V

DDQ

1 k
1 %

1 k
1 %

C

IN

(Required)

Q

1

Standby

GND

CIN = Required Capacitor; 330µF (3.3 ± 5 V Input), 560 µF (12 V Input).
Co

= Required Low-ESR Electrolyitic Capacitor; 470 µF (3.3 ± 5 V Input), 940 µF (12 V Input).

1

= Ceramic Capacitance for Optimum Response to a 3 A (+ 1.5 A) Load Transient; 200 µF (3.3 ± 5 V Input), 400 µF (12 V Input).

Co

2

Co

= Distributed hf-Ceramic Decoupling Capacitors for VTT bus; as Recommended for DDR Memory Applications.

n

BSS138
(Optional)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

POLA is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

STANDARD APPLICATION

1

2

10 9 8

PTHxx060Y

(Top View)

3

7

6

54

Co
Low−ESR
(Required)

Co

1

Ceramic
(Optional)

V

REF

V

TT

Co

n

hf−Ceramic

V

TT

Termination Island

2

SSTL−2

Bus

Copyright © 2004–2005, Texas Instruments Incorporated

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PTH03060Y
PTH05060Y, PTH12060Y

SLTS222A–MARCH 2004 – REVISED OCTOBER 2005

ORDERING INFORMATION

PTHXX060Y (Base Part Number)

Input Voltage Part Number

PTH03060YAH Horizontal T/H Yes

3.3 V PTH03060YAS Standard SMD No

PTH03060YAZ Optional SMD Yes

PTH05060YAH Horizontal T/H Yes

5 V PTH05060YAS Standard SMD No

PTH05060YAZ Optional SMD Yes

PTH12060YAH Horizontal T/H Yes

12 V PTH12060YAS Standard SMD No

PTH12060YAZ Optional SMD Yes

(1) Add T to end of part number for tape and reel on SMD packages only.
(2) Reference the applicable package reference drawing for the dimensions and PC board layout.
(3) Lead (Pb) –free option specifies Sn/Ag pin solder material.
(4) Standard option specifies 63/37, Sn/Pb pin solder material.

(1)

DESCRIPTION Pb – free and Mechanical Package

RoHS

(4)

(4)

(4)

(2)

(3)

EUW

EUY

(3)

(3)

EUY

EUW

EUY

(3)

(3)

EUY

EUW

EUY

(3)

EUY

ENVIRONMENTAL AND ABSOLUTE MAXIMUM RATINGS

voltages are with respect to GND

UNIT

V

T

T

T

T

(1) For operation below 0°C, the external capacitors must have stable characteristics, use either a low ESR tantalum, Os-Con, or ceramic

(2) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated

Control input voltage –0.3 V to Vin+03 V

REF

Operating temperature Over VINrange –40°Cto85°C

A

range

Wave solder temperature Surface temperature of module body or pins PTHXX060YAH 260°C

wave

Solder reflow temperature Surface temperature of module body or pins

reflow

Storage temperature –40°Cto125°C

s

(5 seconds)

PTHXX060YAS 235°C

PTHXX060YAZ 260°C

Mechanical shock Per Mil-STD-883D, Method 2002.3 1 msec, 1/2 Sine, mounted 500 G

Mechanical vibration Mil-STD-883D, Method 2007.2 20-2000 Hz 20 G

Weight 3.7 grams

Flammability Meets UL 94V-O

capacitor.

maximum.

(1)

(2)

(2)

(2)

2

PTH03060Y

PTH05060Y, PTH12060Y

www.ti.com

SLTS222A–MARCH 2004 – REVISED OCTOBER 2005

ELECTRICAL SPECIFICATIONS

TA=25°C; nominal VIN;V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

O

V

IN

∆V

REF

|V

TT–VREF

η Efficiency I

V

r

trip Overcurrent threshold Reset, followed by auto recovery 20 A

I

o

t

tr

V

tr

UVLO Under-voltage lockout

V

IH

V

IL

I

inhibit Pin to GND 130 µA

IL

inh Input standby current Inhibit control (pin 4) to GND 10 mA

I

IN

f

s

C

IN

CO1, CO2 External output capacitance PTH03060Y/PTH05060Y 200

MTBF Reliability Per Bellcore TR-332 50 % stress, T

Output current Over ∆V

Input voltage range Over IOrange PTH05060Y 4.5 5.5 V

Tracking range for V

| Tracking tolerance to V

VoRipple (pk-pk) 20 MHz bandwidth 20 mVpp

Load transient response

Inhibit control (pin 4) V
Input high voltage

Inhibit control (pin 4) –0.2 0.6
Input low voltage

Inhibit control (pin 4)
Input low curent

Switching frequency Over VINand IOranges kHz

External input capacitance µF

=1.25V;CIN,CO1, and CO2 = typical values; and IO=IOmax (unless otherwise stated)

REF

range Continuous 0 ±10

REF

PTH03060Y 2.95 3.65

PTH12060Y 10.8 13.2

REF

REF

Over line, load and temperature –10 10 mV

0.55 1.8 V

PTH03060Y 86%

= 8 A PTH05060Y 86%

o

PTH12060Y 83%

15 A/µs load step, from:
–1.5 A to 1.5 A

Recovery time 30 µsec

VOover/undershoot 25 40 mV

PTH03060Y 2.45 2.8

Increasing PTH05060Y 4.3 4.45 V

V

IN

PTH12060Y 9.5 10.4

PTH03060Y 2.0 2.40

Dncreasing PTH05060Y 3.4 3.7 V

V

IN

PTH12060Y 8.8 9

–0.5 Open

IN

Referenced to GND

PTH03060Y/PTH05060Y 250 300 350

PTH12060Y 200 250 300

PTH03060Y/PTH05060Y 330

(3)

PTH12060Y 560

Capacitance value: Nonceramic PTH03060Y/PTH05060Y 470

PTH12060Y 940

Capacitance value: Ceramic µF

PTH12060Y 400

Equuivanent series resistance (non-ceramic) 4

=40°C, ground benign 6

A

(4)

(4)

(6)

(1)

(2)

(5)

5500

(5)

5500

(4)

300

(4)

600

A

V

V

µF

mΩ

6

Hrs

10

(1) Rating is conditional on the module being directly soldered to a 4-layer PCB with 1 oz. copper. See the SOA curves or contact the

factory for appropriate derating.

(2) This control pin has an internal pull-up to the input voltage VIN. If it is left open-circuit the module will operate when input power is

applied. A small low-leakage (<100 nA) MOSFET is recommended for control. For further information, consult the related application
note.

(3) An input capacitor is required for proper operation. The capacitor must be rated for a minimum of 300 mA rms (750 mA rms for 12-V

input) of ripple current.

(4) The minimum value of external output capacitance value ensures that VTT meets the specified transient performance requirements for

the memory bus terminations. Lower values of capacitance may be possible when the measured peak change in output current is
consistently less than 3 A.

(5) This is the calculated maximum. The minimum ESR limitation will often result in a lower value. Consult the capacitor application notes

for further guidance.

(6) This is the typcial ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 mΩ as the minimum when using max-ESR values

to calculate.

3

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PTH03060Y
PTH05060Y, PTH12060Y

SLTS222A–MARCH 2004 – REVISED OCTOBER 2005

TERMINAL

NAME NO.

V

IN

GND 1, 7

V

REF

V

TT

VoSense 5

Inhibit 3

N/C 4, 9, 10 No connect

DESCRIPTION

2 The positive input voltage power node to the module, which is referenced to common GND.

This is the common ground connection for the VINand VTTpower connections. It is also the 0-VDC reference
for the control inputs.

The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at V
the reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus

8 driver supply voltage (V

V

pin should not exceed 500 Ω. See the Typical DDR Application Diagram in the Application Information

REF

section for reference.

This is the regulated power output from the module with respect to the GND node, and the tracking
termination supply for the application data and address buses. It is precisely regulated to the voltage applied

6

to the module's V
module. Once active it will track the voltage applied at V

The sense input allows the regulation circuit to compensate for voltage drop between the module and the
load. For optimal voltage accuracy VoSense should be connected to VTT.

The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level
ground signal to this input turns off the output voltage, VTT. Although the module is inhibited, a voltage, V
will be present at the output terminals, fed through the DDR memory. When the Inhibit is active, the input
current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will
produce an output whenever a valid input source is applied. See the Typical DDR Application Diagram in the
Application Information section for reference.

Terminal Functions

÷ 2), using a resistor divider. The Thevenin impedance of the network driving the

DDQ

input, and is active active about 20 ms after a valid input source is applied to the

REF

REF

.

REF

is also

DDQ

1

7

PTHXX060

(Top View)

10 9 8

2

6

543

4

0

1

2

3

4

2468100

IL − Load Current − A

VIN = 3.3 V

VIN = 12 V

VIN = 5 V

− Power Dissipation − W
P

D

20

30

40

50

60

70

80

90

400 LFM

200 LFM

100 LFM

Nat Cinv

VIN = 12 V

24680

I

L

− Load Current − A

10

T

A

− Ambient Temperature −

5

C

PTH03060Y

PTH05060Y, PTH12060Y

www.ti.com

10 0

90

80

70

Efficiency − %

60

50

SLTS222A–MARCH 2004 – REVISED OCTOBER 2005

TYPICAL CHARACTERISTICS (V

=1.25 V)

REF

(1)(2)

EFFICIENCY OUTPUT RIPPLE POWER DISSIPATION

vs vs vs

LOAD CURRENT LOAD CURRENT LOAD CURRENT

Output Ripple − mV

60

50

40

30

20

10

VIN = 5 V

0

2

− Load Current − A

I

L

VIN = 3.3 V

VIN = 12 V

46 8100

VIN = 5 V

2468100

VIN = 3.3 V

VIN = 12 V

IL − Load Current − A

Figure 1. Figure 2. Figure 3.

PTH03060Y/PTH05060Y AT PTH12060Y ONLY; VIN=12V

NOMINAL V

TEMPERATURE DERATING vs LOAD CURRENT

IN

TEMPERATURE DERATING

vs LOAD CURRENT

90

80

C

5

70

60

50

40

− Ambient Temperature −
A

T

30

20

Nat Cinv

200 LFM

100 LFM

400 LFM

2468100

IL − Load Current − A

Figure 4. Figure 5.

(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the

converter. Applies to Figure 1, Figure 2, and Figure 3.

(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum

operating temperatures. Derating limits apply to modules soldered directly to a 4 in x 4 in double-sided PCB with 1 oz. copper. For
surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 4, and Figure 5.

5

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PTH03060Y
PTH05060Y, PTH12060Y

SLTS222A–MARCH 2004 – REVISED OCTOBER 2005

TYPICAL CHARACTERISTICS

TRANSIENT PERFORMANCE FOR ∆3-A LOAD CHANGE

PTH03060Y/PTH05060Y: SOURCE-SINK-SOURCE PTH12060Y: SOURCE-SINK-SOURCE TRANSIENT

TRANSIENT

50 ms/div

VTT − V

(50 mV/div)

(52A/div)

I

TT

REF

50 ms/div

VTT − V

(50 mV/div)

(2A/div)

I

TT

REF

Figure 6. Figure 7.

6