TEXAS INSTRUMENTS PCI1031 Technical data

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D

3.3-V Core Logic With Universal PCI
Interface Compatible and 3.3-V or 5-V PCI
Signaling Environments

D

Supports PCI Local Bus Specification 2.1

D

Mix-and-Match 5-V/3.3-V PC Card16 Cards

D

Supports T wo PC Card Slots With Hot
Insertion and Removal

D

1995 PC Card Standard Compliant

D

Low-Power Advanced Submicron CMOS
T echnology

D

Uses Serial Interface to Texas Instruments
(TI) TPS2206 Dual Power Switch

D

System Interrupts Can Be Programmed as
PCI-Style or ISA IRQ-Style Interrupts

D

ISA IRQ Interrupts Can Be Serialized Onto a
Single IRQSER Pin

D

Independent Read and Write Buffers for
Each Direction

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

D

Multifunction PCI Device With Separate
Configuration Spaces for Each Socket

D

Five PCI Memory Windows and T wo I/O
Windows Available to Each PC Card16
Socket

D

Exchangeable Card Architecture
(ExCA)-Compatible Registers Are Mapped
in Memory and I/O Space

D

TI Extension Registers Are Mapped in the
PCI Configuration Space

D

Intel 82365SL-DF Register Compatible

D

Supports 16-Bit Distributed Direct Memory
Access (DMA) on Both PC Card Sockets

D

Supports PC/PCI DMA on Both PC Card
Sockets

D

Supports Zoom Video Mode

D

Supports Ring Indicate

D

Packaged in a 208-Pin Thin Plastic Quad
Flatpack

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Block Diagram – 16-Bit PC Card Interface 3. . . . . . . . . .

Terminal Assignments – PCI-to-PC Card (16 Bit) 4. . . . . . . . . . . .

Signal Names/Pin Number Sort Tables 5. . . . . . . . . . . . . . . . . . . .

Terminal Functions 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Architecture 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card DMA and Distributed DMA 28. . . . . . . . . . . . . . . . . . . . . .

Ring Indicate 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Zoom Video 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Management 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Configuration Header Registers 35. . . . . . . . . . . . . . . . . . . . .

ExCA Registers 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CardBus Socket Registers 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Registers 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Absolute Maximum Ratings 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 89. . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions for PCI Interface 89. . . . . . . .

Recommended Operating Conditions for PC Cards A and B 90. . . .

Electrical Characteristics 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 92. . . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 93. . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 94. . . . . . . . . . . . . . . .

PC Card Cycle Timing 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Parameter Measurement Information 97. . . . . . . . . . . . . . . .

Mechanical Data 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Intel and MPIIX are trademarks of Intel Corp.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

description

The TI PCI1031 is a high-performance PCI-to-PC Card16 controller that supports two independent PC Card
sockets compliant with the1995 PC Card standard. The PCI1031 provides a set of features that makes it ideal
for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card standard
retains the 16-bit PC Card specification defined in PCMCIA release 2.1 and is capable of full 16-bit data transfers
at 33 MHz. The PCI1031 supports any combination of 16-bit and PC Cards in its two sockets, powered at 3.3 V
or 5 V, as required.

The PCI1031 is compliant with the PCI local bus specification revision 2.1, and its PCI interface can act as either
a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card
DMA transfers.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1031
is register compatible with the Intel 82365SL-DF PC Card interface controller. The PCI1031 internal datapath
logic allows the host to access 8- and 16-bit cards using full 32-bit PCI cycles for maximum performance.
Independent 32-bit write buffers allow fast-posted writes to improve system-bus utilization.

An advanced CMOS process is used to achieve low system-power consumption while operating at PCI clock
rates up to 33 MHz. Low-power modes allow the host power-management system to further reduce
power consumption.

All unused PCI1031 pins should be pulled high by a 43-kΩ resistor.

2

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PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

system block diagram – 16-bit PC Card interface

A simplified system block diagram using the PCI1031 is provided below. The PCI950 IRQ deseralizer and the
PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that
capability.

The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface
includes all address/data and control signals for 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in
16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.

The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
Other miscellaneous system interface terminals are available on the PCI1031 that include:

D

Multifunction IRQ terminals

D

SUSPEND, RI_OUT (power management control signals)

D

SPKROUT.

PCI Bus

PCI1031

INTA

INTB

TPS22xx

Power

Switch

PC Card

Socket A

PC Card

Socket B

External ZV Port

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed

video signals too the VGA controller.

3

PCI1031

68 68

23

23

IRQSER

3

PCI930

ZV Switch

PCI950

IRQSER

Deserializer

Zoom Video

19

Zoom Video

4

Interrupt

Controller

IRQ2–15

VGA

Controller

Audio

Sub-System

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

terminal assignments – PCI-to-PC Card (16 bit)

PDV PACKAGE

(TOP VIEW)

IRQ7/PCDMAREQ

IRQ9/IRQSER

IRQ10/CLKRUN

IRQ11/PCDMAGNT

IRQ12
IRQ14

IRQ15/RI_OUT

V

PCLK

RSTIN

GND

GNT

REQ

AD31
AD30

V

CCP

AD29
AD28

V

AD27
AD26
AD25
AD24

C/BE3

GND

IDSEL

AD23

AD22

AD21

AD20

V
AD19
AD18
AD17

AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP
PERR
SERR

V

PAR

C/BE1

AD15
AD14
AD13

GND

AD12

A_D10

A_D2

146

147

A_D9

144

145

CC

A_D1

V

143

A_D8

A_D0

142

141

A_CD2

A_WP(IOIS16)

140

139

A_A1

A_A0

A_BVD2(SPKR)

A_BVD1(STSCHG/RI)

A_WAIT

A_VS1

A_READY(IREQ)

A_A2

132

131

134

133

136

135

138

137

PCI1031 CorePCI

A_REG

GND

130

129

A_A3

128

A_INPACK

127

A_A4

A_A5

126

125

Card A

Card B

IRQ3/INTA

154

153

156

155

157
158
159
160
161
162
163
164

CC

165
166
167
168
169
170
171
172
173
174
175

CC

176
177
178
179
180
181
182
183
184
185
186

CC

187
188
189
190
191
192
193
194
195
196
197
198
199
200
201

CC

202
203
204
205
206
207
208

214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952

V

SPKROUT/SUSPEND

148

150

149

152

151

CCP

DATA

CLOCK

LATCH

GND

IRQ4/INTB

IRQ5

A_VS2

A_A6

A_RESET

122

124

123

CCA

A_A25

V

120

121

A_A7

119

A_A24

118

A_A12

A_A23

116

117

A_A15

A_A22

114

115

V

113

CC

112

A_A16

A_A21

111

A_A20

A_WE

110

109

A_A14

A_A19

108

107

A_A13

A_A18

106

105
104

103
102
101

100

51

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63

62
61

60
59
58
57
56
55
54
53

A_A8
A_A17
A_A9
A_IOWR
A_A11
A_IORD
A_OE
A_CE2
GND

A_A10
A_CE1
A_D15

A_D7
A_D14

A_D6
A_D13
A_D5
A_D12

V

CC

A_D4
A_D11
A_D3
A_CD1

B_D10
B_D2
B_D9
B_D1
B_D8

B_D0
GND
B_CD2
B_WP(IOIS16)
B_BVD1(STSCHG/RI)

B_BVD2(SPKR)
B_WAIT

B_READY(IREQ)
B_VS1

B_A0
B_A1
B_A2

V

CC

B_REG
B_A3
B_INPACK
B_A4
B_A5
B_RESET
B_A6
B_VS2
B_A25
B_A7

B_A24

CC

AD9

AD8

AD7

AD6

AD5

AD3

AD2

AD1

C/BE0

V

AD11

AD10

AD4

4

AD0

GND

B_D3

B_CD1

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B_D11

B_D4

B_D5

B_D12

GND

B_D6

B_D13

B_D7

B_D14

B_D15

B_CE1

B_A10

B_CE2

CC

V

B_OE

B_A11

B_IORD

B_IOWR

B_A9

CCB

V

B_A17

B_A8

B_A18

B_A19

B_A13

GND

B_A14

B_WE

B_A20

B_A16

B_A21

B_A15

B_A22

B_A23

B_A12

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Table 1. Signal Names Sorted Alphabetically – 16-Bit PC Card

SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME NO.

A_A0
A_A1
A_A2
A_A3
A_A4
A_A5
A_A6
A_A7
A_A8
A_A9
A_A10
A_A11
A_A12
A_A13
A_A14
A_A15
A_A16
A_A17
A_A18
A_A19
A_A20
A_A21
A_A22
A_A23
A_A24
A_A25
A_BVD1(STSCHG
A_BVD2(SPKR
A_CD1
A_CD2
A_CE1
A_CE2
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_INPACK
A_IORD
A_IOWR
A_OE

)

/RI)

133
132
131
128
126
125
123
119
104
102
95
100
117
106
108
115
112
103
105
107
109
111
114
116
118
121
138
137
82
140
94
97
141
144
146
83
85
88
90
92
142
145
147
84
87
89
91
93
127
99
101
98

A_READY(IREQ)
A_REG
A_RESET
A_VS1
A_VS2
A_WAIT
A_WE
A_WP(IOSI16)
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
B_A0
B_A1
B_A2
B_A3
B_A4
B_A5
B_A6
B_A7
B_A8
B_A9
B_A10
B_A11

135
130
124
134
122
136
110
139
15
14
12
11
10
9
8
6
4
3
2
1
208
206
205
204
191
190
189
188
186
185
184
183
179
178
177
176
174
173
171
170
67
66
65
62
60
59
57
54
39
36
29
34

B_A12
B_A13
B_A14
B_A15
B_A16
B_A17
B_A18
B_A19
B_A20
B_A21
B_A22
B_A23
B_A24
B_A25
B_BVD1(STSCHG
B_BVD2(SPKR)
B_CD1
B_CD2
B_CE1
B_CE2
B_D0
B_D1
B_D2
B_D3
B_D4
B_D5
B_D6
B_D7
B_D8
B_D9
B_D10
B_D11
B_D12
B_D13
B_D14
B_D15
B_INPACK
B_IORD
B_IOWR
B_OE
B_READY(IREQ)
B_REG
B_RESET
B_VS1
B_VS2
B_WAIT
B_WE
B_WP(IOSI16)
C/BE0
C/BE1
C/BE2
C/BE3

/RI)

52

CLOCK

41

DATA

43

DEVSEL

50

FRAME

48

GND

37

GND

40

GND

42

GND

45

GND

47

GND

49

GND

51

GND

53

GND

55

GND

72

GND

71

GNT

16

IDSEL

74

IRDY

28

IRQ3/INTA

30

IRQ4/INTB

76

IRQ5

78

IRQ7/PCDMAREQ

80

IRQ9/IRQSER

17

IRQ10/CLKRUN

19

IRQ11/PCDMAGNT

21

IRQ12

24

IRQ14

26

IRQ15/RI_OUT

77

LATCH

79

PAR

81

PCLK

18

PERR

20

REQ

23

RSTIN

25

SPKROUT/SUSPEND

27

STOP

61

SERR

33

TRDY

35

V
V
V
V
V
V
V
V
V
V
V
V
V
V

CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCB
CCP
CCP

32
69
63
58
68
56
70
46
73
5
203
192
180

PCI1031

151
152
197
193
13
22
44
75
96
129
153
167
181
194
207
168
182
195
154
155
156
157
158
159
160
161
162
163
150
202
165
199
169
166
149
198
200
196
7
31
64
86
113
143
164
175
187
201
120
38
148
172

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5

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Table 2. Signal Names Sorted by Terminal Number – 16-Bit PC Card

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

AD11
AD10
AD9
AD8
C/BE0
AD7
V

CC

AD6
AD5
AD4
AD3
AD2
GND
AD1
AD0
B_CD1
B_D3
B_D11
B_D4
B_D12
B_D5
GND
B_D13
B_D6
B_D14
B_D7
B_D15
B_CE1
B_A10
B_CE2
V

CC

B_OE
B_IORD
B_A11
B_IOWR
B_A9
B_A17
V

CCB

B_A8
B_A18
B_A13
B_A19
B_A14
GND
B_A20
B_WE
B_A21
B_A16
B_A22
B_A15
B_A23
B_A12

53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104

B_A24
B_A7
B_A25
B_VS2
B_A6
B_RESET
B_A5
B_A4
B_INPACK
B_A3
B_REG
V

CC

B_A2
B_A1
B_A0
B_VS1
B_READY(IREQ)
B_WAIT
B_BVD2(SPKR)
B_BVD1(STSCHG/RI)
B_WP(IOIS16
B_CD2
GND
B_D0
B_D8
B_D1
B_D9
B_D2
B_D10
A_CD1
A_D3
A_D11
A_D4
V

CC

A_D12
A_D5
A_D13
A_D6
A_D14
A_D7
A_D15
A_CE1
A_A10
GND
A_CE2
A_OE
A_IORD
A_A11
A_IOWR
A_A9
A_A17
A_A8

)

105

A_A18

106

A_A13

107

A_A19

108

A_A14

109

A_A20

110

A_WE

111

A_A21

112

A_A16

113

V

114

A_A22

115

A_A15

116

A_A23

117

A_A12

118

A_A24

119

A_A7

120

V

121

A_A25

122

A_VS2

123

A_A6

124

A_RESET

125

A_A5

126

A_A4

127

A_INPACK

128

A_A3

129

GND

130

A_REG

131

A_A2

132

A_A1

133

A_A0

134

A_VS1

135

A_READYIREQ)

136

A_WAIT

137

A_BVD2(SPKR)

138

A_BVD1(STSCHG

139

A_WP(IOIS16)

140

A_CD2

141

A_D0

142

A_D8

143

V

144

A_D1

145

A_D9

146

A_D2

147

A_D10

148

V

149

SPKROUT

150

LATCH

151

CLOCK

152

DATA

153

GND

154

IRQ3/INTA

155

IRQ4/INTB

156

IRQ5

CC

CCA

CC

CCP

/RI)

/SUSPEND

157

IRQ7/PCDMAREQ

158

IRQ9/IRQSER

159

IRQ10/CLKRUN

160

IRQ11/PCDMAGNT

161

IRQ12

162

IRQ14

163

IRQ15/RI_OUT

164

V

165

PCLK

166

RSTIN

167

GND

168

GNT

169

REQ

170

AD31

171

AD30

172

V

173

AD29

174

AD28

175

V

176

AD27

177

AD26

178

AD25

179

AD24

180

C/BE3

181

GND

182

IDSEL

183

AD23

184

AD22

185

AD21

186

AD20

187

V

188

AD19

189

AD18

190

AD17

191

AD16

192

C/BE2

193

FRAME

194

GND

195

IRDY

196

TRDY

197

DEVSEL

198

STOP

199

PERR

200

SERR

201

V

202

PAR

203

C/BE1

204

AD15

205

AD14

206

AD13

207

GND

208

AD12

CC

CCP

CC

CC

CC

6

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FUNCTION

FUNCTION

PCI system

TERMINAL

NAME NO.

PCLK 165 I

RSTIN

166 I

PCI address and data

TERMINAL

NAME NO.

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3
C/BE2
C/BE1
C/BE0

PAR 202 I/O

170
171
173
174
176
177
178
179
183
184
185
186
188
189
190
191
204
205
206
208

180
192
203

10
11
12
14
15

I/O

TYPE

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.

PCI reset. When the RSTIN signal is asserted low, the PCI1031 forces all output buffers to the high-impedance
state and resets all internal registers. When asserted, the PCI1031 is nonfunctional. After RSTIN
the PCI1031 returns to the default state. When the PCI1031 SUSPEND
from any RSTIN

I/O

TYPE

Address/data bus. AD31–AD0 are the multiplexed PCI address and data bus. During the address phase of a PCI
cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0

I/O

contain data.

1
2
3
4
6
8
9

Bus commands and byte enables. C/BE3–C/BE0 are multiplexed on the same PCI terminals. During the address
phase, C/BE3

I/O

5

The byte enables determine which byte lanes carry meaningful data. C/BE0
applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

Parity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI1031 calculates
even parity across the AD and C/BE

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Terminal Functions

reset (i.e., the PCI1031 internal register contents are preserved). See

–C/BE0 define the bus command. During the data phase, C/BE3–C/BE0 are used as byte enables.

buses and outputs the results on PAR, delayed by one clock.

mode is enabled, the device is protected

power management

applies to byte 0 (AD7–AD0), C/BE1

is deasserted,

.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

PCI1031

FUNCTION

FUNCTION

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Terminal Functions (Continued)

PCI interface control

TERMINAL

NAME NO.

DEVSEL

FRAME

GNT

IDSEL 182 I

IRDY

PERR

REQ

SERR

STOP

TRDY

197 I/O

193 I/O

168 I

195 I/O

199 I/O Parity error. PERR is driven by the PCI target during a write to indicate that a data parity error has been detected.
169 O Request. REQ asserted by the PCI1031 to request access to the PCI bus as a master.

200 O
198 I/O Stop. STOP is driven by the current PCI target to request the master to stop the current transaction.

196 I/O

I/O

TYPE

Device select. As a PCI target, the PCI1031 asserts DEVSEL to claim the current cycle. As a PCI master, the
PCI1031 monitors DEVSEL

Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access.
FRAME

is low (asserted) to indicate that a bus transaction is beginning. While FRAME is asserted, data

transfers continue. When FRAME
Grant. GNT is driven by the PCI arbiter to grant the PCI1031 access to the PCI bus after the current data

transaction is complete. If distributed DMA is not implemented, GNT
Initialization device select. IDSEL selects the PCI1031 during configuration accesses. IDSEL can be connected

to one of the upper 24 PCI address lines.
Initiator ready. IRDY indicates the bus master’s ability to complete the current data phase of the transaction.

IRDY

is used with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled
low (asserted). During a write, IRDY
indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are
low (asserted) at the same time. IRDY
the PCI bus is the target.

System error. SERR pulsed from the PCI1031 indicates an address parity error has occurred. If SERR is not
used, it must be pulled high with a 43-kΩ resistor.

T arget ready. TRDY indicates the ability of the PCI1031 to complete the current data phase of the transaction.
TRDY

is used with IRDY. A data phase is completed on any clock where both TRDY and IRDY are sampled
asserted. During a read, TRDY
indicates that the PCI1031 is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are
asserted together. TRDY
the PCI bus master.

until a target responds or a time-out occurs.

is an output when the PCI1031 is the PCI target and an input when the PCI1031 is

is sampled high (deasserted), the transaction is in the final data phase.

must be pulled high with a 43-kΩ resistor.

indicates that valid data is present on AD31–AD0. During a read, IRDY

is an output when the PCI1031 is the PCI bus master and an input when

indicates that valid data is present on AD31– AD0. During a write, TRDY

power supply

TERMINAL

NAME NO.

GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 Device ground terminals

V
V
V
V

CC
CCA
CCB
CCP

7, 31, 64, 86, 113, 143, 164, 175, 187, 201 Power-supply terminals for core logic (3.3 V)

120 Power-supply terminal for PC Card A (5 V or 3.3 V)

38 Power-supply terminal for PC Card B (5 V or 3.3 V)

148, 172 Power-supply terminals for PCI interface (5 V or 3.3 V)

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

FUNCTION

FUNCTION

interrupt

TERMINAL

NAME NO.

IRQ3/INTA
IRQ4/INTB

IRQ7/PCDMAREQ 157 O

IRQ9/IRQSER 158

IRQ10/CLKRUN 159 O

IRQ11/PCDMAGNT 160 I/O

IRQ5
IRQ12
IRQ14

IRQ15/RI_OUT 163 I/O

154
155

156
161
162

I/O

TYPE

O

O

I/O

O

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Terminal Functions (Continued)

Interrupt request 3 and interrupt request 4. IRQ3/INTA–IRQ4/INTB can be connected to either PCI
or ISA interrupts. IRQ3/INTA

. When configured for IRQ3 and IRQ4, IRQ3/INTA–IRQ4/INTB must be connected to the ISA

or INTB
IRQ programmable interrupt controller. When IRQ3/INTA
INTB

, IRQ3/INTA–IRQ4/INTB must be connected to available interrupts on the PCI bus.

Interrupt request 7. IRQ7/PCDMAREQ is software configurable and is used by the PCI1031 to
request PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When
IRQ7/PCDMAREQ
appropriate request (REQ

DMA

).

Interrupt request 9/serial IRQ. IRQ9/IRQSER is software configurable and indicates an interrupt
request from a PC Card to the PCI1031. When IRQ9/IRQSER is configured for IRQ9, it must be
connected to the system programmable interrupt controller. IRQSER allowa all IRQ signals to be
serialized onto one pin. IRQ9/IRQSER is configured via bits 2–1 in the device control register of the
TI extension registers (see

Interrupt requests 10. IRQ10/CLKRUN is software configurable and is used by the PCI1031 to
support the PCI CLKRUN
control register at offset 80h, IRQ10/CLKRUN

Interrupt request 11. IRQ11/PCDMAGNT is software configurable and is used by the PCI1031 to
accept a grant for PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When
IRQ11/PCDMAGNT
appropriate grant (GNT

Interrupt requests 5, 12, and 14. These signals are ISA interrupts. These terminals indicate an
interrupt request from one of the PC Cards. The interrupt mode is selected in the device control
register of the TI extension registers (see

Interrupt request 15. IRQ15/RI_OUT indicates an interrupt request from one of the PC Cards.
RI_OUT

allows the RI input from the 16-bit PC Card to be output to the system. IRQ15/RI_OUT is

configured in the card control register of the TI extension registers (see

is configured for PC/PCI DMA request (IRQ7), it must be connected to the

–IRQ4/INTB are software configurable as IRQ3 or INTA and as IRQ4

–IRQ4/INTB are configured for INTA and

) pin on the Intel Mobile Triton PCI I/O accelerator (MPIIX) (see

device control register

protocol. When configured as CLKRUN by setting bit 0 in the system

is configured for PC/PCI DMA grant (IRQ11), it must be connected to the

) pin on the Intel MPIIX controller (see

).

is an open drain output (see

PC/PCI DMA

device control register

).

system control register

).

card control register

PC/PCI

).

).

PC Card power switch

TERMINAL

NAME NO.

CLOCK 151 O

DATA 152 O Power switch data. DATA is used by the PCI1031 to serially communicate socket power control information.

LATCH 150 O

I/O

TYPE

Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. The frequency of
the clock is derived from dividing PCICLK by 36. The maximum frequency of CLOCK is 2 MHz (see

PC Card power control interface

Power switch latch. LATCH is asserted by the PCI1031 to indicate to the PC Card power switch that the data
on the DATA line is valid.

).

speaker control

TERMINAL

NAME NO.

SPKROUT/

SUSPEND

149 O

I/O

TYPE

Speaker. SPKROUT carries the digital audio signal from the PC Card. SUSPEND, when enabled, places
the PCI1031 in PCI suspend/resume (see
card control register (see

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

card control register

power management

) of the TI extension registers.

). SPKROUT/SUSPEND is configured in the

TPS2206

9

PCI1031

FUNCTION

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Terminal Functions (Continued)

16-bit PC Card address and data (slots A and B)

TERMINAL

NUMBER

NAME

†

Terminal name is preceded with A_. For example, the full name for terminal 121 is A_A25.

‡

Terminal name is preceded with B_. For example, the full name for terminal 55 is B_A25.

A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

SLOT

†

A

121

118
116
114

111
109
107
105
103

112

115
108
106

117
100

95
102
104

119
123
125
126
128
131
132
133

93
91
89
87

84
147
145
142

92

90

88

85

83
146
144
141

SLOT

I/O

TYPE

‡

B

55
53
51
49
47
45
42
40
37
48
50
43
41
52
34
29
36
39
54
57
59
60
62
65
66
67

27
25
23
20
18
81
79
77
26
24
21
19
17
80
78
76

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Terminal Functions (Continued)

16-bit PC Card interface control signals (slots A and B)

TERMINAL

NUMBER

NAME

BVD1

(STSCHG

BVD2(SPKR)

CD1
CD2

CE1
CE2

INPACK 127 61 I

IORD

IOWR

OE 98 32 O

†

Terminal name is preceded with A_. For example, the full name for terminal 138 is A_BVD1.

‡

Terminal name is preceded with B_. For example, the full name for terminal 72 is B_BVD1.

/RI)

SLOT

SLOT

†

A

138 72 I

137 71 I

82

1401674

94
97

99 33 O

101 35 O

I/O

TYPE

‡

B

Battery voltage detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1
is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both
BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high,
the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer

28
30

serviceable and the data in the memory PC Card is lost. See

configuration register
status register

Status change. STSCHG
or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI
Battery voltage detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2

is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both
BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the
battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer
serviceable and the data in the memory PC Card is lost. See

configuration register
status register

Speaker. SPKR
been configured for the 16-bit I / O interface. The audio signals from cards A and B can be
combined by the PCI1031 and output on SPKROUT

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, the PC Card asserts BVD2 to request a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on
the PC Card. When a PC Card is inserted into a socket, CD1

I

status, see
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address

bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address

O

bytes.
Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an I/O read cycle

at the current address.
DMA request. INPACK

16-bit PC Card that supports DMA. If used, the PC Card asserts INP ACK
for a DMA operation.

I/O read. IORD is asserted by the PCI1031 to enable 16-bit I/O PC Card data output during host
I/O read cycles.

DMA write. IORD
that supports DMA. The PCI1031 asserts IORD
memory.

I/O write. IOWR is driven low by the PCI1031 to strobe write data into 16-bit I/O PC Cards during
host I/O write cycles.

DMA read. IOWR is used as the DMA read strobe during DMA operations to a 16-bit PC Card
that supports DMA. The PCI1031 asserts IOWR
PC Card.

Output enable. OE is driven low by the PCI1031 to enable 16-bit memory PC Card data output
during host memory read cycles.

DMA terminal count. OE
PC Card that supports DMA. The PCI1031 asserts OE

ExCA interface status register

for enable bits. See

for the status bits for this signal.

is used to alert the system to a change in the READY, write protect,

is used by 16-bit modem cards to indicate ring detection.

for enable bits. See

for the status bits for this signal.

is an optional binary audio signal available only when the card and socket have

can be used as the DMA request signal during DMA operations to a

is used as the DMA write strobe during DMA operations from a 16-bit PC Card

is used as terminal count (TC) during DMA operations to a 16-bit

ExCA card status-change register

ExCA card status-change register

.

during DMA transfers from the PC Card to host

during DMA transfers from host memory to the

ExCA card status-change interrupt

ExCA card status-change interrupt

.

and CD2 are pulled low. For signal

to indicate TC for a DMA write operation.

and

ExCA interface

and

ExCA interface

to indicate a request

PCI1031

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

PCI1031

FUNCTION

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Terminal Functions (Continued)

16-bit PC Card interface control signals (slots A and B) (continued)

TERMINAL

NUMBER

NAME

READY(IREQ)

REG

RESET 124 58 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT 136 70 I

WE 110 46 O

WP(IOIS16) 139 73 I

VS1
VS2

†

Terminal name is preceded with A_. For example, the full name for terminal 135 is A_READY(IREQ).

‡

Terminal name is preceded with B_. For example, the full name for terminal 69 is B_READY(IREQ

SLOT

SLOT

†

A

135 69 I

130 63 O

134
1226856

I/O

TYPE

‡

B

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket
are configured for the memory-only interface. READY is driven low by the 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write command.
READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer
command.

Interrupt request. IREQ
on the 16-bit I/O PC Card requires service by the host software. IREQ
no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE
or IOWR active). Attribute memory is a separately accessed section of card memory and is
generally used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG is used as DMA acknowledge (DACK) during DMA operations to a
16-bit PC Card that supports DMA. The PCI1031 asserts REG
REG

is used with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the
memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE also
is used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports
DMA. The PCI1031 asserts WE to indicate TC for a DMA read operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)
function. The status of WP can be read from the ExCA interface status register.

I/O is 16 bits. WP applies to 16-bit I/O PC Cards. IOIS16
the address on the bus corresponds to an address to which the 16-bit PC Card responds, and
the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, the PC Card asserts WP to request a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used together, determine the
operating voltage of the 16-bit PC Card.

I/O

DMA request. VS1
a 16-bit PC Card that supports DMA. If used, the PC Card asserts VS1
for request a DMA operation.

is asserted by a 16-bit I/O PC Card to indicate to the host that a device

and VS2 can be used as the DMA request signal during DMA operations to

is high (deasserted) when

or WE active) and to the I/O space (IORD

to indicate a DMA operation.

is asserted by the 16-bit PC Card when

and VS2 to indicate a

).

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

architecture

This section provides an overview of the PCI1031 PCI-to-PC Card/CardBus controller, followed by detailed
descriptions of PCI and PC Card interfaces, the TPS2206 interface, and interrupt support. Both hardware
protocols and software programming models are discussed.

introduction to the PCI1031

The PCI1031 is a bridge between the PCI local bus and two PC Card sockets supporting 16-bit PC Cards, and
is compliant with the PCI local bus specification revision 2.1 and PCMCIA’s 1995 PC Card standard. The
PCI1031 PC Card interface recognizes and identifies PC Cards installed at power up or run-time. The PCI1031
includes support for 16-bit PC Card features such as multifunction cards, 3.3-V cards, and DMA, as well as
backward compatibility to the PCMCIA release 2.1-compliant PC Cards. The PCI1031 core is powered at 3.3 V
to provide low power dissipation, but can independently support either 3.3-V or 5-V signaling on the PCI and
PC Card interfaces.

Host software interacts with the PCI1031 through a variety of internal registers that provide status and control
information about the PC Cards currently in use and the internal operation of the PCI1031 itself. These internal
registers are accessed by application software either through the PCI configuration header, or through
programmable windows mapped into PCI memory or I/O address space. The PCI1031 uses a windows format
to pass cycles between PCI and PC Card address spaces. Host software must program the location and size
of these windows when the PCI1031 or PC Card is initialized.

PCI1031

The PCI1031 also communicates via a three-line serial protocol to the TI TPS2206 dual PCMCIA power switch.
The TPS2206 switches V
has indirect control over the TPS2206 by writing to internal PCI1031 registers.

The PCI1031 can notify the host system via interrupts when an event occurs that requires attention from the
host. Such events are either card status-change (CSC) events or functional interrupts from a PC Card. CSC
events occur within the PCI1031 or at the PC Card interface, and indicate a change in the status of the socket
(i.e., card insertion or removal). Functional interrupts originate from the PC Card application and are passed
from the card to the host system. Both CSC and functional interrupts can be individually masked and routed
to a variety of system interrupts. The PCI1031 can signal the system interrupt controller via PCI-style interrupts,
ISA IRQs, or with the serialized IRQ protocol.

The following sections describe in greater detail how the PCI1031 interacts at an electrical, protocol, and
software level at its PCI interface, PC Cards, TPS2206 PC Card power control, and interrupts.

and VPP supply voltage to the two PC Card sockets independently . Host software

CC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

PCI interface

This section describes the PCI interface of the PCI1031, how the device responds and participates in PCI bus
cycles, and how the major internal registers appear in the PCI address space. The PCI1031 provides all required
signals for PCI master/slave (initiator/target) devices, and can operate in either 5-V or 3.3-V PCI signaling
environments by connecting the two V

The PCI1031 is a true multifunction PCI device, with two different PCI functions residing within the device. PCI
function 0 is associated with PC Card socket A and PCI function 1 is associated with PC Card socket B. The
PCI1031 behaves in accordance to the PCI specification for multifunction devices. Functions 0 and 1 have
separately addressable PCI configuration headers, and can use PCI INTA and INTB, respectively.

The PCI1031 responds as a PCI target device to PCI bus cycles based on its decode of the address phase of
each cycle and internal register settings of the device. T able 3 lists the valid PCI bus cycles and their encoding
on the 4-bit C/BE bus during the address phase of a bus cycle. The most common PCI bus commands are read
and write cycles to one of the three PCI address spaces: memory, I/O, and configuration address spaces.

Table 3. PCI Command Definition

terminals to the desired switching level.

CCP

C/BE3–C/BE0

0000 Interrupt acknowledge
0001 Special cycle
0010 I/O read

0011 I/O write
0100 Reserved
0101 Reserved

0110 Memory read

0111 Memory write
1000 Reserved
1001 Reserved
1010 Configuration read

1011 Configuration write

1100 Memory read multiple

1101 Dual address cycle

1110 Memory read line

1111 Memory write and invalidate

COMMAND

The PCI1031 never responds as a PCI target device to the interrupt acknowledge, special cycle, dual address
cycle, or reserved commands, nor will it initiate them as a PCI master device. The remaining PCI commands
address one of the three PCI address spaces mentioned earlier, and each is described in the following three
sections. The PCI1031 accepts PCI cycles by asserting DEVSEL

as a medium-speed device.

The ability of the PCI1031 to respond to PCI memory or I/O bus cycles is dictated by register bits in the PCI
command register (see

PCI command

). This register is located in the PCI configuration header at offset 04h
and is required by the PCI local bus specification. Bits 0 and 1 of this register enable the PCI1031 to respond
to I/O and memory cycles, respectively . Host software must set these bits during initialization of the device. Bit 2
of this register enables/disables the bus-mastering capability of the PCI1031 on the PCI bus. Host software must
also set this bit during device initialization.

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

PCI configuration address space and bus hierarchy

The PCI local bus specification defines two types of PCI configuration read and write cycles: type 0 and type 1.
The PCI1031 decodes each type differently . Type 0 configuration cycles are intended for devices on the current
bus, while type 1 configuration cycles are intended for devices at a subordinate bus. The difference between
these two types of cycles is the encoding of the PCI address AD bus during the address phase of the cycle. The
address AD bus encoding during the address phase of a type 0 configuration cycle is shown in Figure 1. The
6-bit register number field represents an 8-bit address but with two lower bits masked to 0. This results in a
256-byte configuration address space (per PCI function) with a 32-bit (or double-word) granularity. Individual
byte addresses can be selected for read/write using the C/BE

31 11 10 8 721 0

Reserved

Figure 1. PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle

The PCI1031 claims type 0 configuration cycles only when IDSEL is asserted during the address phase of the
cycle, and the PCI function number encoded in the cycle is 0 or 1. If the function number is 2 or greater, the
PCI1031 accepts the command. If the command is a read, it returns all Fs. If the command is a write, the data
is dropped. The PCI1031 services valid type 0 configuration read or write cycles by accessing internal registers
from the appropriate configuration header. Table 12 shows a PCI configuration header in the PCI1031.

T able 12 can represent either PCI1031 function. Blocks with a dagger (
or in part, common between the two functions. Blocks without a dagger are registers that are separate and
distinct between the two functions. Refer to

PCI configuration header register

of the registers shown in Table 12.

signals during the data phase of the cycle.

Function

number

†

) represent registers that are, in whole

Register

number

0 0

for a complete description of all

Because type 1 configuration cycles are issued to devices on subordinate buses, the PCI1031 does not claim
type 1 configuration cycles. The address AD bus encoding during the address phase of a type 1 configuration
cycle is shown in Figure 2. The device number and bus number fields define the destination bus and device for
the cycle.

31 24 23 16 15 11 10 8 721 0

Reserved Bus number

Device

number

Function number

Register

number

0 1

Figure 2. PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle

If the type 1 configuration write cycle is decoded because of the values in the configuration registers 18h–1Ah,
the cycle is accepted but no information is passed through the PCI1031. In the case of a type 1 configuration
read cycle, the PCI1031 returns all 1s. Type 1 cycles to other than device 00h are claimed but are not passed
on. Reads return all 1s. Also, the PCI1031 never issues PCI configuration read or write cycles on the PCI bus
as a PCI bus master.

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15

PCI1031
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SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

PCI I/O address space

The PCI local bus specification defines an I/O address space accessed using 32-bit addresses, yielding a
4G-byte usable address space. The PCI1031 decodes PCI I/O cycles as a PCI target device only if host software
has enabled it to do so (see bit 0 of the
the address on the PCI address AD bus and claims the cycle if a hit is detected to a programmed I/O window.
Such a window can be mapped either to internal PCI1031 registers or to PC Card address space.

There are two instances where the PCI1031 maps internal registers to PCI I/O address space. The first is the
legacy 16-bit PC Card index/data registers (used to access the ExCA registers), and the second is DMA socket
registers (used to access registers in distributed DMA). In both cases, the locations of these windows are
programmed by base address registers in PCI configuration space. The legacy 16-bit PC Card base address
(see

PC Card 16-bit I/F legacy-mode base address

both PCI1031 functions 0 and 1. This base address locates a 2-byte window in I/O space anywhere in the 32-bit
I/O address space. The socket DMA base address register (see
configuration offset 98h, and is separate and distinct for functions 0 and 1. This base address locates a 16-byte
window in I/O space in the lower 64K bytes of PCI I/O address space. For a complete description of this base
address register and the socket DMA registers, see

The PCI1031 provides the ability for host software to program PCI I/O windows to PC Card address spaces.
These windows provide the bounds upon which the PCI1031 positively decodes I/O cycles from PCI to a
PC Card, and are the primary means for applications to communicate with PC Cards. See

windows, ExCA registers

, and

CardBus PC Cards and windows

PCI command register

) is located at configuration offset 44h, and is common to

socket DMA register

). If so enabled, the PCI1031 positively decodes

socket DMA register 1

1 and

DMA registers

) is located at

.

16-bit PC Cards and

.

PCI memory address space

The PCI local bus specification also defines a memory address space accessed using 32-bit addresses, yielding
a 4G-byte usable address space. The PCI1031 decodes PCI memory cycles as a PCI target device only if host
software has enabled it to do so (see bit 1 of the
decodes the address on the PCI address AD bus and claims the cycle if a hit is detected to a programmed
memory window. Such a window can be mapped either to internal PCI1031 registers or to PC Card
address space.

The only case where the PCI1031 maps internal registers to PCI memory address space is the CardBus/ExCA
registers that are mapped into a 4K-byte window for each socket. The location of these windows is programmed
by a base address register in PCI configuration space. The CardBus socket/ExCA base address (see

socket registers/ExCA registers base address register

and distinct from functions 0 and 1. Each base address locates a 4K-byte window in memory space anywhere
in the 32-bit memory address space. For a description of this base address register and the CardBus socket
registers, see

The PCI1031 enables host software to program PCI memory windows to PC Card address spaces. These
windows provide the bounds on which the PCI1031 positively decodes memory cycles from PCI to a PC Card
and are the primary means for applications to communicate with PC Cards (see
and

ExCA registers)

CardBus socket registers/ExCA registers base address register

. A memory read always disconnects after the first data phase.

PCI command register

) is located at configuration offset 10h and is separate

). If so enabled, the PCI1031 positively

.

16-bit PC Cards and windows

compliance to PCI local bus specification revision 2.1

The most significant additions to the PCI local bus specification revision 2.1 are the latency requirements on
PCI peripherals. Minimum response times are specified for a PCI device to respond with valid data. These
requirements are intended to improve throughput and reduce latencies on the PCI bus. The PCI1031 is fully
compliant with these guidelines.

CardBus

Other additions to revision 2.1 of the PCI local bus specification include the subsystem ID and subsystem vendor
ID registers in the PCI configuration header.

16

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PC Cards

The 1995 PC Card standard provides a hardware- and software-interface standard for connecting
credit-card-sized memory and I/O cards to personal computers. By implementing compliant card slots, PC
manufacturers allow customers to use industry-standard PCMCIA memory and I/O cards from many different
vendors. The 1995 PC Card standard defines 16-bit and 32-bit PC Cards. The 16-bit PC Cards are an extension
of the PCMCIA 2.1/JEIDA 4.1 standards and are sometimes referred to as 16-bit cards or as R2 cards. The
32-bit PC Cards are a newly defined architecture called CardBus cards, with all 60 signals on the PC Card
interface redefined for a synchronous, 32-bit bus environment patterned after PCI.

PC Card insertion/removal and recognition

Prior to the PCMCIA 1995 PC Card standard, only two types of PC Cards existed: 16-bit memory cards and
16-bit I/O cards. Both types of cards were designed for 5-V VCC supply , and could be hot-inserted into a fully
powered socket. Upon insertion, 16-bit I/O cards were required to use the memory card signaling conventions
until host software had read the card information structure (CIS) and switched the socket and card to an
I/O mode.

The 1995 PC Card standard introduced several features, such as CardBus and 3.3-V/5-V card support, which
have challenged the idea of hot insertion and introduced a new card recognition scheme. Both CardBus cards
and 16-bit PC Cards can now be designed for 3.3-V V
in card damage if such a card were inserted into a socket powered at 5 V. Similarly, the socket can no longer
automatically power a PC Card to 5-V VCC, so a method of detecting the voltage requirements and card type
is needed. The 1995 PC Card standard addresses this by describing an interrogation procedure that the socket
must initiate upon card insertion into a cold, unpowered socket.

supply , which of fers power savings, but could result

CC

PCI1031

This scheme uses the card CD1

, CD2, VS1 and VS2 signals (called CCD1, CCD2, CVS1, and CVS2 for
CardBus cards). A PC Card designer connects these four pins in a certain configuration, depending on the type
of card (16-bit or CardBus) and the supply voltage (5 V , 3.3 V, X.X V , and/or Y.Y V). The encoding scheme for
this is defined in the 1995 PC Card standard and in Table 4.

Table 4. PC Card Card Detect and Voltage Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE

Ground Ground Open Open 5 V 16-bit PC Card 5 V
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V
Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V
Ground Ground Open Ground LV 16-bit PC Card 3.3 V
Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V

Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V
Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V
Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V

Ground Ground Ground Open LV 16-bit PC Card X.X V
Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card X.X V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y .Y V
Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved

Ground Connect to CVS2 Connect to CCD1 Ground Reserved

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PC Card insertion/removal and recognition (continued)

Based on the information described in Table 4, the PCI1031 executes an algorithm upon card insertion that
alternatively drives the VS1
inserted. This process is completed without VCC ever being applied to the socket. Once the PCI1031 has
successfully determined the card type and voltage requirements, it updates the appropriate status bits in the
socket present state register (see
Host software must then read the CardBus socket registers to determine the card type and voltage requirements
and respond accordingly.

16-bit PC Cards and windows

The PCMCIA revision 1.0 defined the original 16-bit memory card, and the later PCMCIA revisions 2.0 and 2.1
defined the 16-bit I/O card. Both types of 16-bit PC Cards have the 16-bit datapaths and a 26-bit address bus
defined. Status and control signals differ between the two card types. The PCI1031 fully supports both types
of cards. The ExCA register set is implemented in the PCI1031, which provides the industry standard Intel
82365SL-DF programming model.

The 16-bit memory cards can have two types of memory address space: attribute memory and common
memory. The attribute memory address space contains the CIS, and common memory is the memory space
used by the application. The CIS is defined by PCMCIA and contains a variety of information about the card
capabilities and resource requirements. Host software reads and parses the CIS to set up the system resources
to use the card application. Both attribute and common memory are accessed with 26-bit addresses, resulting
in a total addressable memory address space of 64M bytes.

and VS2 pins to low and high levels to determine which of the card types has been

socket present state register

) and asserts a CSC interrupt to the host system.

The 16-bit I/O cards can possess attribute and common memory, but also have an I/O address space. This
address space is accessed via 16-bit I/O addresses, resulting in a 64K-byte I/O address space.

The PCI1031 provides a windowing mechanism to link the PCI address space to 16-bit PC Card address space.
Both of these memory and I/O windows are programmed by host software in the ExCA registers. The PCI1031
provides up to five memory windows per socket and two I/O windows per socket. Once enabled, the PCI1031
positively decodes and claims bus cycles that fall within these windows. Bus cycles to the PC Card are then
initiated to write data to the card (in the case of a PCI write cycle) or to read data from the card (in the case of
a PCI read cycle).

Memory and I/O windows to 16-bit PC Cards have several programmable options associated with them. Host
software can choose among these options by setting the appropriate bits in the appropriate ExCA registers.
These options include:

D

Window start address

D

Window end address

D

Window offset address

D

Page address (for 16-bit PC Card memory windows only)

D

Attribute or common memory access (for 16-bit PC Card memory windows only)

D

PC Card datapath width (8 bit or 16 bit)

D

Wait state timing (ISA bus timing or minimum)

D

Write protection (enable/disable writes to memory windows)

The start, end, offset, and page address define the bounds of the memory window in PCI and PC Card memory
address spaces. The page address is necessary to take into account the difference in addressable memory
between PCI (4G bytes) and 16-bit PC Cards (64M bytes). The 8-bit page address appended to the 26-bit start
and end addresses define the bounds of the window in PCI memory address space. When a PCI memory cycle
is decoded and claimed, the PCI1031 adds the offset address to the PCI address before passing the lower 26
bits to the PC Card. The memory windows need not be aligned between the two address spaces.

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ExCA registers

The PCI1031 is fully register compatible with the Intel 82365SL-DF PC Card interface controller. The ExCA
compatibility registers can be accessed indirectly via PCI I/O address space or directly via PCI memory address
space. For I/O access, the PCI1031 uses the same index and data I/O port scheme introduced by Intel. This
index/data window is located in PCI I/O space by the PC Card 16-bit I/F legacy base address (see

I/F legacy-mode base address

legacy-mode base address is shared by both sockets and the ExCA registers run contiguously from index
00h–3Fh for socket A and 40h–7Fh for socket B. Accesses to ExCA indices 80–FFh returns 0s when read.
Writes have no effect.

The compatibility registers can also be accessed directly through the CardBus socket/ExCA register window.
This window in PCI memory address space is located by the CardBus socket registers/ExCA base address
register (see
configuration space. The ExCA compatibility registers are directly mapped into this memory window, starting
at an offset of 800h from the bottom of this window . Each socket has a separate CardBus socket register/ExCA
registers base address register for accessing the ExCA registers. ExCA I/O windows are accessed on word
(16-bit) boundaries.

The ExCA registers provide bits to control many 16-bit PC Card functions. These functions include:

D

Explicit writeback/clear on read of interrupt flag mode selection

CardBus socket registers/ExCA registers base address register

), found at offset 44h in PCI configuration space. The PC Card 16-bit

), found at offset 10h in PCI

PC Card 16-bit

PCI1031

D

PC Card CSC and functional interrupt control

D

Interrupt mode select: level/edge interrupt modes

D

PC Card socket status information

D

ExCA registers configuration after PC Card removal – reset upon card removal or save the register values
upon card removal

D

Memory and I/O windows configuration for 16-bit PC Cards

T able 5 classifies the basic functionality of each register in the ExCA register set. The functional classifications
are: card status register, card control register, memory window, and I/O window. Some of the registers are
classified as both card status and card control since some bits within the register provide status information and
other bits provide card control.

When a 16-bit PC Card is installed in a socket, the entire ExCA register set associated with that socket is
enabled. Some status and control functions in the CardBus socket registers are maintained when a16-bit PC
Card is present, such as the socket power control register. Software is expected to use either ExCA or CardBus
socket registers to control socket power, but not both. The intent is to be fully backward compatible with present
card and socket services, but take advantage of the easy access of some of the newly defined registers in the

CardBus/ExCA socket registers.

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19

PCI1031
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SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

T able 5. ExCA Registers

REGISTER NAME STATUS CONTROL

Identification and revision X 00
Interface status X 01
Power control X 02
Interrupt and general control X 03
Card status change X 04
Card status-change interrupt configuration X 05
Address window enable X X 06
I/O window control X 07
I/O window 0 start-address low byte X 08
I/O window 0 start-address high byte X 09
I/O window 0 end-address low byte X 0A
I/O window 0 end-address high byte X 0B
I/O window 1 start-address low byte X 0C
I/O window 1 start-address high byte X 0D
I/O window 1 end-address low byte X 0E
I/O window 1 end-address high byte X 0F
Memory window 0 start-address low byte X 10
Memory window 0 start-address high byte X 11
Memory window 0 end-address low byte X 12
Memory window 0 end-address high byte X 13
Memory window 0 offset-address low byte X 14
Memory window 0 offset-address high byte X 15
Card detect and general control X X 16
Reserved 17
Memory window 1 start-address low byte X 18
Memory window 1 start-address high byte X 19
Memory window 1 end-address low byte X 1A
Memory window 1 end-address high byte X 1B
Memory window 1 offset-address low byte X 1C
Memory window 1 offset-address high byte X 1D
Global control X 1E
Reserved 1F
Memory window 2 start-address low byte X 20
Memory window 2 start-address high byte X 21
Memory window 2 end-address low byte X 22
Memory window 2 end-address high byte X 23
Memory window 2 offset-address low byte X 24
Memory window 2 offset-address high byte X 25
Reserved 26
Reserved 27

MEMORY
WINDOW

I/O

WINDOW

ExCA

OFFSET

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Table 5. ExCA Registers (Continued)

REGISTER NAME STATUS CONTROL

Memory window 3 start-address low byte X 28
Memory window 3 start-address high byte X 29
Memory window 3 end-address low byte X 2A
Memory window 3 end-address high byte X 2B
Memory window 3 offset-address low byte X 2C
Memory window 3 offset-address high byte X 2D
Reserved 2E
Reserved 2F
Memory window 4 start-address low byte X 30
Memory window 4 start-address high byte X 31
Memory window 4 end-address low byte X 32
Memory window 4 end-address high byte X 33
Memory window 4 offset-address low byte X 34
Memory window 4 offset-address high byte X 35
I/O window 0 offset-address low byte X 36
I/O window 0 offset-address high byte X 37
I/O window 1 offset-address low byte X 38
I/O window 1 offset-address high byte X 39
Reserved 3A
Reserved 3B
Reserved —
Reserved 3D
Reserved 3E
Reserved 3F
Memory window 0–4 page X N/A

MEMORY
WINDOW

I/O

WINDOW

ExCA

OFFSET

†

†

The memory window page register is mapped by the CardBus socket register/ExCA register base address register into PCI memory space.

TPS2206 PC Card power control interface

The attribute of PC Card technology that enables PC Cards to be inserted and removed in a system during run
time requires that power to the PC Card sockets be managed. The TI TPS2206 PC Card power switch performs
this duty by switching VCC and VPP to two card sockets under the control of the PCI1031. Another TI power
switch, the TPS2202A, also can be used. Both the TPS2206 and TPS2202A are pin compatible and provide
the same signaling interface to the PCI1031. The TPS2202A provides RESET and RESET

pins that allow the
socket VCC and VPP to be shut down via external control from either system reset or a power supervisory device
in the system. References in this document to the TPS2206 apply identically to the TPS2202A device.

The PCI1031 and TPS2206 communicate via a 3-line serial interface called P2C (PCMCIA peripheral control).
This serial interface is a significant savings in pin count over the 8-line signaling convention. The P2C signaling
is transparent to host software; the PCI1031 generates the proper signal protocols when its internal VCC/V
control registers are written. Figure 3 illustrates the protocol used to communicate from the PCI1031 to
the TPS2206.

PP

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21

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

TPS2206 PC Card power control interface (continued)

DATA

LATCH

CLOCK

D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 3. Serial-Interface Timing

The DA TA, LATCH, and CLOCK terminals on the PCI1031 are connected to the terminals of the same names
on the TPS2206. The PCI1031 generates the TPS2206 CLOCK signal by dividing the PCI CLK input by 36. A
PCI CLK frequency of 33 MHz results in a TPS2206 CLOCK frequency of approximately 1 MHz. To conserve
power, the PCI1031 switches the TPS2206 CLOCK signal only when transmitting information to the power
switch; otherwise, the PCI1031 stops the clock in a logic low state.

The encoding of the serial data stream is shown in Table 6. The ninth data bit, D8, is not shown. This bit (D8)
is the active low shutdown (SHDN

) bit. When D8 is reset to 0, the values of bits D0 through D7 are ignored and
the power switch removes all power to both PC Card sockets. The PCI1031 sets D8 to a logic high value at
all times.

Table 6. TPS2206 Control Logic

CONTROL SIGNALS

A

D0 D1

0 0 0 V 0 0 0 V 0 0 0 V 0 0 0 V
0 1 A V
1 0 12 V 1 0 3.3 V 1 0 12 V 1 0 5 V
1 1 Hi Z 1 1 0 V 1 1 Hi Z 1 1 0 V

V

PP

CC

D2 D3

0 1 5 V 0 1 B V

A

V

CC

D4 D5

B

V

PP

CC

D6 D7

0 1 3.3 V

V

B
CC

interrupts

Interrupts are an integral component in any computer architecture. The dynamic nature of PCMCIA and the
abundance of PC Card I/O applications mean that interrupts are an integral part of the PCI1031. The PCI1031
provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different
mechanisms for dealing with interrupts in this device are based on various specifications and industry
standards. The ExCA register set provides interrupt control for 16-bit PC Card functions.

The PCI1031 detects interrupts and/or events at the PC Card interface and notifies the host interrupt controller
via one of several interrupt signaling protocols. T o simplify the discussion and use of interrupts in the PCI1031,
PC Card interrupts are classified as either CSC interrupts or functional interrupts. Functional interrupts are
explicit requests for interrupt servicing directly from the PC Card. Such requests are communicated over a
dedicated PC Card signal defined for this purpose. CSC interrupts indicate a change in the state of the PC Card
(i.e., card removal or insertion, or power up complete). All sources of functional and CSC interrupts are
discussed in detail in the following sections, as well as any specific options to be configured by host software.

The method by which either type of PC Card interrupt is communicated to the host interrupt controller varies
from system to system. The PCI1031 offers system designers the choice of using PCI interrupt signaling,
traditional ISA IRQ signaling, serialized IRQ protocol, or PCI with ISA interrupts.

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y

16-bit I/O

All PC Cards

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

functional and CSC interrupts

Functional interrupts are defined as requests from a PC Card for interrupt service, and are indicated by asserting
specially defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards.
CSC interrupts are defined as events at the PC Card interface that are detected by the PCI1031 and can warrant
notification of host software for service. Such events include transitions on certain PC Card signals or card
removal/insertion. The specific examples of functional and CSC interrupts depend on the type of PC Card(s)
installed in the socket at any given time. The 16-bit interrupt sources differ between memory and I/O PC Cards.

Table 7 summarizes the sources of interrupts and the type of PC Card associated with them. The functional
interrupt events are valid only for 16-bit I/O Cards. Card insertion and removal events are independent of the
card type since the same card-detect signals are used in both cases and the PCI1031 cannot distinguish
between card types upon card insertion.

Table 7. PC Card Interrupt Events and Description

CARD TYPE EVENT TYPE SIGNAL DESCRIPTION

A transition on BVD1 indicates a change in the PC Card
battery conditions.

A transition on BVD2 indicates a change in the PC Card
battery conditions.

A transition on READY indicates a change in the ability of the
memory PC Card to accept or provide data.

The assertion of STSCHG indicates a status change on the
PC Card.

The assertion of IREQ indicates an interrupt request from
the PC Card.

A transition on either CD1 // CCD1 or CD2 // CCD2 indicates
an insertion or removal of a 16-bit // CardBus PC Card.

An interrupt is generated when a PC Card power up cycle
is complete.

16-bit memory

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card status

(STSCHG

Interrupt request

Card insertion

or removal

Power cycle complete CSC N/A

)

(IREQ)

CSC BVD1(STSCHG)

CSC BVD2(SPKR)

CSC READY(IREQ)

CSC BVD1(STSCHG)

Functional READY(IREQ)

CSC

CD1//CCD1,
CD2

//CCD2

PCI1031

The signal-naming convention for PC Card signals describes the function for 16-bit memory and I/O cards. The
16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The
16-bit I/O cards use two signal lines to signal interrupts: one to indicate a change in card status and another
dedicated to request interrupt servicing from the host. A 16-bit memory PC Card uses the BVD1 and BVD2
signals to indicate changes in battery conditions on the card, and it uses the READY signal to insert wait states
during memory card data transfers.

The PC Card standard describes the power-up sequence that must be followed by the PCI1031 when an
insertion event occurs and the host requests that the socket V

and VPP be powered. Upon completion of this

CC

power-up sequence, the PCI1031 interrupt scheme can be used to notify the host system denoted by “power
cycle complete” (see T able 7). This interrupt source is considered a PCI1031 internal event because it does not
depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket.

Host software can individually mask (disable) each of the potential CSC interrupt sources listed in Table 7 by
setting the appropriate bits in the PCI1031. By individually masking the interrupt sources listed in T able 7, host
software can control which events cause a PCI1031 interrupt. Host software has some control over which
system interrupt the PCI1031 asserts by programming the appropriate routing registers. The PCI1031 allows
host software to route PC Card CSC and functional interrupts to separate system interrupts. Interrupt routing
is specific to the interrupt signaling method used and is discussed in the following sections.

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PCI1031

y

16-bit I/O

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SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

functional and CSC interrupts (continued)

When an interrupt is signaled by the PCI1031, the interrupt service routine must be able to discern which of the
events in T able 8 caused the interrupt. This is of particular interest with CSC interrupts, where a variety of events
at the card interface can cause interrupts. Internal registers in the PCI1031 provide flags that report to the host
interrupt service routine which of the interrupt sources was the cause of an interrupt. By first reading these status
bits, the interrupt service routine can determine which action to take.

T able 8 describes the valid PC Card interrupt events and details the internal PCI1031 registers associated with
masking and reporting them.

Table 8. PC Card Interrupt Mask and Flag Registers

CARD TYPE EVENT MASK FLAG

Battery conditions

16-bit memory

All PC Cards Card insertion or removal Socket mask register, Bits 2 and 1

(BVD1, BVD2)

Wait states (READY) ExCA offset 05h/45h/805h, Bit 2 ExCA offset 04h/44h/804h, Bit 2

Change in card status

(STSCHG

Interrupt request (IREQ)

Power cycle complete

)

ExCA offset 05h/45h/805h, Bits 1 and 0 ExCA offset 04h/44h/804h, Bits 1 and 0

ExCA offset 05h/45h/805h, Bit 0

Always enabled
Always enabled PCI configuration offset 91h, Bit 0

ExCA offset 04h/44h/804h, Bit 0

Socket event register, Bits 2 and 1

ExCA offset 04h/44h/804h, Bit 3

There are various methods of clearing the interrupt flag bit. ExCA provides two methods to clear 16-bit
PC Card-related interrupt flags. One is a write of 1 to the bit in question, and the other is a read from the register .
This selection is made by bit 2 in ExCA offset 1Eh/5Eh/81Eh (see

high-byte register

).

ExCA I/O window 0–1 offset-address

There is a single exception to Table 8, when PCI interrupt signaling is used. The enable/disable bits for
functional and CSC interrupts are found in separate registers in PCI configuration register 91h, bits 4 and 3 (see

card control register

). Refer to the section on PCI interrupt signaling for details.

ISA IRQ interrupts

NOTE:

All unused interrupt pins should be pulled high by a 43-kΩ resistor.

Among the PCI1031 interrupt signaling schemes is the traditional ISA IRQ signaling, available in most x86 PCs.
Dedicated terminals on the PCI1031 can be used to assert 10 of the 15 ISA IRQs: IRQ3, IRQ4, IRQ5, IRQ7,
IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. These IRQs represent the common interrupts expected by
PC Card applications and several free IRQs for CSC routing.

In a system using ISA IRQs, the host software must first configure the PCI1031 to use ISA signaling by setting
bits 2–1 of PCI configuration register, offset 92h, to 01b (see

device control register

). The ten IRQ terminals
remain in the high-impedance state until the ExCA Card CSC and functional interrupt routing registers are set
to a valid state. The step-by-step series of events that host software must follow to successfully configure the
PCI1031 for ISA IRQ signaling follows. These steps assume that the system has powered up and RSTIN
(deasserted). In cases where only selected bits of a register are to be modified, host software must leave the
remaining register bits unchanged by reading the current contents of the register first, modifying the desired bits,
then writing the new value back to the respective PCI1031 register.

is high

24

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PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

ISA IRQ interrupts (continued)

1. Set bits 2–1 of PCI configuration register 92h (function 0) to 01b for interrupt mode selection.

2. Write to the upper four bits of ExCA register 05h/45h/805h for desired CSC routing for each socket (note
the restrictions placed on interrupt routing with ISA IRQ signaling; only ten IRQs are valid in this mode).

3. If a PC Card is installed in the socket and requires functional interrupts, write to the lower nibble of ExCA
register 03h/43h/803h for desired functional interrupt routing for the socket (note the restrictions placed on
interrupt routing with ISA IRQ signaling).

4. Using T able 9, write to the appropriate mask register bits to enable interrupt generation for desired events.

5. Upon card-removal events, host software should unroute any functional interrupts that were set for that
socket.

6. Upon card-insertion events, host software should reconfigure the mask and routing registers to support the
new card requirements.

PCI interrupts

NOTE:

PCI interrupts can be used with ISA interrupts. All unused INTA
high by a 43-kΩ resistor.

and INTB lines should be pulled

PCI1031

The PCI1031 also supports interrupt signaling compliant with the PCI local bus specification. Consistent with
this specification, the PCI1031 can use one PCI interrupt for each of its functions: INTA is used for PC Card
socket A interrupts, and INTB
dual-function pins with the ISA-mode interrupts IRQ3 and IRQ4. When the PCI1031 is configured for PCI
interrupt signaling, these pins behave as open-drain PCI interrupts. Systems that prefer a single interrupt line
from the PCI1031 can connect these two interrupt terminals together.

PCI configuration register offset 91h must be written in order to route CSC and functional interrupts from each
socket. The step-by-step series of events for host software to successfully configure the PCI1031 for PCI
signaling follows. These steps assume that the system has powered up and RSTIN is high (deasserted). In
cases where only selected bits of a register are to be modified, host software must leave the remaining register
bits unchanged by reading the current contents of the register first, modifying the desired bits, then writing the
new value back to the register.

1. Set bit 5 of PCI configuration register 91h (function 0) to a value of 1 (enabled).

2. Set bit 3 of PCI configuration register 91h (functions 0 and 1 separately) to route CSC interrupts to INTA
(for socket A) or INTB (for socket B).

3. If a PC Card is installed in the socket and requires functional interrupts, write to bit 4 of the PCI Card control
register 91h (for the socket) to route functional interrupts from the PC Card to INT A (for socket A) or INTB
(for socket B).

4. Using T able 8, write to the appropriate mask register bits to enable interrupt generation for desired events.

5. Upon card-removal events, host software should disable any functional interrupts generation.

6. Upon card insertion events, host software should reconfigure the mask and routing registers to support the
new card requirements.

is used for socket B. These pins are on the PCI1031 at pins 154 and 155 and are

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25

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

serialized IRQ signaling

The serialized interrupt protocol implemented in the PCI1031 uses a single PCI1031 terminal to communicate
all interrupt status information to the host interrupt controller. The protocol defines a serial packet consisting of
a start cycle, a stop cycle, and multiple interrupt cycles. All data in the packet is synchronous with PCLK. The
duration of the stop and interrupt cycles is a fixed number of clock periods, but the start cycle is variable (four
to eight clock periods). This allows the serial packet to retain coherence on either side of a PCI-to-PCI bridge.

Figures 4 and 5 illustrate how the serialized IRQ protocol works. Figure 4 shows the start cycle and the first
several IRQ sampling periods, and Figure 5 shows the final IRQ sampling periods and the stop cycle. The
intermediate IRQ sampling periods are not shown, but the sampling periods occur in ascending IRQ order:
IRQ0, IRQ1, SMI, IRQ3, IRQ4 . . . IRQ15, and IOCHK
illustrations, IRQ1 and IRQ15 are sampled deasserted. The stop cycle only can occur after the IOCHK period,
but can be extended to allow more sampling periods for platform-specific functions.

Start Cycle

. The IRQ signals are active high. In the following

IRQ0 IRQ1

SMI (IRQ2)

PCLK

IRQSER

Drive Source

PCLK

IRQSER

Drive Source

IRQx

H

Start

Host Controller

H = Host Control; R = Recovery; T = Turnaround; S = Sample

RT

S RT

None None

S RT

IRQ1

not

asserted

Figure 4. Serial-Interrupt Timing – Start Cycle and IRQ Sampling Periods

IRQ14 IRQ15

S

RT

None

H = Host Control; R = Recovery; T = Turnaround; S = Sample

S

IRQ15

not

asserted

RT

IOCHCK

S RT

None

STOP

H

Stop

Host Controller

RT

Figure 5. Serial-Interrupt Timing – Stop Cycle

S RT

None

In a system using the serialized IRQ protocol, the host software must configure the PCI1031 to use serialized
IRQs by setting bits 2–1 of the PCI configuration register at offset 92h to 10b. The step-by-step series of events
that host software must follow to successfully configure the PCI1031 for serialized IRQ signaling follows. These
steps assume that the system has powered up, PCI reset, and RSTIN

is high (deasserted). In cases where only
select bits of a register are to be modified, host software must leave the remaining register bits unchanged by
reading the current contents of the register first, modifying the desired bits, then writing the new value back to
the register.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

serialized IRQ signaling (continued)

1. Set bits 2–1 of PCI device control register 92h (function 0) to 10b.

2. Write to the upper nibble of ExCA register 05h/45h/805h for desired CSC routing for each socket (all 15 IRQs
are available for routing when serialized IRQ signaling has been selected).

3. If a PC Card is installed in the socket and requires functional interrupts, write to the lower nibble of ExCA
register 03h/43h/803h for desired functional interrupt routing for the socket.

4. Using T able 8, write to the appropriate mask register bits to enable interrupt generation for desired events.

5. On card-removal events, host software should unroute any functional interrupts that were set for that
socket.

6. Upon card-insertion events, host software should reconfigure the mask and routing registers to support the
new card requirements.

PCI clock run

PCI1031

The PCI1031 supports PCI clock run (CLKRUN
determine the status of CLK as an open-drain output to request the CLK to restart or to speed up. PCI CLKRUN
is enabled by setting bit 0 in the system control register (see
resource manager informs the PCI1031 that the PCI clock is stopped or slowed, the PCI1031 ensures that no
transactions are in progress for either of the two PC Card sockets before allowing the clock resource manager
to stop or slow the PCI clock. CLKRUN
information on configuring the clock run option.

CLKRUN configuration

Bits 1–0 in the TI extension registers at offset 80h are used to enable and configure CLKRUN. Bit 0 enables
CLKRUN. Bit 1, when set, keeps the PCI clock running in response to a PCI CLKRUN deassertion (see

control register

conditions for stopping/slowing the PCI clock

Before allowing the central resource to slow or stop the PCI clock, the following conditions are checked:

D

The PCI CLKRUN enable bit is set and the KEEP CLOCK bit is cleared (see

D

Neither socket is in the process of powering up or powering down.

D

The 16-bit resource managers are not busy.

D

The PCI master is not busy.

D

No socket interrogation is underway.

D

No card interrupts are pending.

conditions for restarting the PCI clock

The PCI clock restarts when any PC Card is installed in a socket or removed from a socket. For 16-bit cards,
if the PCI clock stops or slows, the PCI1031 requests that the clock be restarted under the following conditions:

).

shares the IRQ10 pin on the PCI1031. See

). CLKRUN is an optional signal that is used as an input to

system control register

). When the PCI clock

system control register

system control register, bit 1

for

system

).

D

A 16-bit I/O card asserts IREQ.

D

A 16-bit I/O card asserts STSCHG/RI.

D

A 16-bit DMA card asserts DREQ.

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27

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

PC Card DMA and distributed DMA

DMA is a concept with many different interpretations and implementations, depending on the context and
application. In fact, DMA support within the PCI1031 has different connotations, depending on whether the
subject is PCI or PC Card DMA. On the PC Card side, the PCI1031 supports the DMA protocol defined in the
1995 PC Card standard on both sockets. On the PCI side, the PCI1031 supports a distributed DMA protocol,
compliant with the distributed DMA on the PCIWay, revision 6.0, specification. It also supports PC/PCI DMA in
systems designed with the Intel MPIIX.

DMA on PCI is accomplished by compliance with the distributed DMA specification. The PCI1031 complies with
this specification as it applies to DMA devices, and implements two DMA channels; one per socket. Each DMA
channel is controlled by the host via a 16-byte window in PCI I/O address space. This window is mapped in
internal PCI1031 registers that are similar to the 8237 DMA controller programming model. By programming
these registers, the PCI1031 services DMA requests from PC Card applications by initiating PCI bus mastering
cycles to host memory address space.

DMA configuration

Host software must program the PCI1031 socket DMA registers 0 and 1 to set up the socket for DMA transfers.
These registers are found in the PCI configuration header, offsets 94h and 98h (see

DMA register 0

). Socket DMA register 0 applies to the PC Card portion of DMA transfers. Socket DMA register 1

applies to the PCI portion of DMA transfers and complies with the distributed DMA specification.

test register

and

socket

Socket DMA register 0 has only two significant bits. Bits1–0 encode the DREQ signal used by the PC Card. This
field must be programmed with a valid value before the PCI1031 initiates a DMA transfer. Socket DMA register 1
has 16 significant bits, and the encoding is shown in Table 9. The most important field in socket DMA register 1
is the base address that locates the DMA registers in PCI I/O address space. This is how the host communicates
and configures the DMA transfer process.

Table 9. Socket DMA Register 1

BIT TYPE FUNCTION

31–16 R Reserved. Bits 31–16 are read only and return 0s when read. Writes have no effect.

DMA base address. Bits 15–4 locate the socket DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O

15–4 R/W

3 R Nonlegacy extended addressing. This is not supported on the PCI1031 and always returns a 0.

2–1 R/W

0 R/W

address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O
address space. The lower four bits are hardwired to 0, forcing the window to a natural 16-byte boundary.

Transfer size. Bits 2–1 specify the width of the DMA transfer on the PCI interface. This field is encoded as:

00 = 8-bit transfer (default)
01 = 16-bit transfer
10 = Reserved
11 = Reserved

Decode enable. Enables the decoding of the DMA base address by the PCI1031. Bit 0 is encoded as:

0 = Disabled (default)
1 = Enabled

When host software initializes the PCI1031, the base address in socket DMA register 1 can be programmed,
but not enabled. When a particular DMA-capable PC Card is installed in the socket, host software can proceed
to program the DREQ

signaling option, the datapath width, and enable the DMA register decode in I/O space.
These options are specific to the PC Card and must be set when the card is configured, but not when the socket
is configured. After setting these options and enabling the DMA register decode, the DMA registers can be
programmed. The DMA register programming model is shown in Table 10.

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Reserved

Page

00h

Reserved

Reserved

04h

Reserved

08h

Multichannel mask

Reserved

Reserved

0Ch

DMA configuration (continued)

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

Table 10. DMA Registers

R/W REGISTER NAME

R

W

R

W

R NA

W Mode

R

W

Current address

Base address

Current word

Base word

NA Status

Request Command

NA

Master clear

DMA BASE

ADDRESS OFFSET

The DMA registers contain control and status information consistent with the 8237 DMA controller; however,
the register locations are reordered and expanded in some cases. Refer to

DMA registers

for a detailed
description of the individual bits contained in the DMA registers. While the DMA register definitions are identical
to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller
do not apply to distributed DMA in a PCI environment. In such cases, the PCI1031 implements these obsolete
register bits as read-only , nonfunctional bits. The reserved registers shown in T able 10 are implemented as read
only, and return 0s when read. Writes to reserved registers have no effect.

DMA transfers

The DMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be
completed after the PC Card is inserted and interrogated, as follows:

1. Set the proper DMA request (DREQ) signal assignment in the PCI configuration, offset 94h (bits 1–0).

2. Set the proper data width of the DMA transfer in the PCI configuration, offset 98h (bits 2–1).

3. Enable I/O window decoding of the DMA registers by setting bit 0 in the PCI configuration offset 98h.
These steps assume that host software has already powered the PC Card, interrogated its CIS, and set the

appropriate bits in the PCI1031 that identify the card as a 16-bit I/O PC Card. Also, both I/O access and bus
mastering must be enabled in the PCI command register. Host software can then program the DMA registers
with the transfer count, direction of the transfer, and memory location of the data. Once this programming is
complete, the PCI1031 awaits the assertion of DREQ

to initiate the transfer.

DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1031 accepts data 8 or 16 bits
at a time (depending on the programming of the data width register field), then requests access to the PCI bus
by asserting its REQ

signal. Once granted access to the bus and the bus returns to an idle state, the PCI1031
initiates a PCI memory write command to the current memory address and transfers the data in a single data
phase. After terminating the PCI cycle, the PCI1031 accepts the next byte(s) from the PC Card until the transfer
count expires.

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ,
the PCI1031 asserts its PCI REQ signal to request access to the PCI bus. Once access is granted and the bus
is idle, the PCI1031 initiates a PCI memory read operation to the current memory address and accepts 8 or
16 bits of data (depending on the programming of the socket DMA register 1 field). After terminating the PCI
cycle, the data is passed on to the PC Card. After terminating the PC Card cycle, the PCI1031 requests access
to the PCI bus again until the transfer count expires.

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29

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

DMA transfers (continued)

PCI I/O read and write cycles to the DMA registers are accepted and serviced during DMA transfers. If, while
a DMA transfer is in progress, the host resets the DMA channel, the PCI1031 asserts TC and ends the PC Card
cycle(s). TC is indicated in the DMA status register. At the PC Card interface, the PCI1031 supports demand
mode transfers. The PCI1031 asserts DACK the entire duration of the transfer unless DREQ is high
(deasserted) before TC. There is no performance penalty for long wait states during this mode of operation as
there is in the legacy ISA system, because the DMA channel is a dedicated resource localized at the
PC Card socket.

PC/PCI DMA

The PC/PCI DMA protocol provides a way for legacy I/O devices to do DMA transfers on the PCI bus in systems
equipped with the Intel MPIIX. The Intel MPIIX supports PC/PCI DMA expansion for docking station applications
where I/O devices require DMA transfers between the docking station PCI bus or extended I/O bus and a PCI
bus in the notebook docking computer.

In the PC/PCI DMA protocol, the PCI1031 acts as a PCI slave device. The Intel MPIIX DMA controller uses
request/grant pairs, REQ
as the PCI1031. The Intel MPIIX REQ and GNT pins correspond to the PCI1031 IRQ7 and IRQ11 pins,
respectively . Under the PC/PCI protocol, a PCI DMA slave device requests a DMA transfer using a serialized
protocol on REQ. The Intel MPIIX, as a bus master , arbitrates for the PCI bus. When the Intel MPIIX gets control
of the PCI bus, it asserts GNT
memory cycles on the PCI bus.

[A–B] and GNT[A–B], which are configured to support a PCI DMA slave device such

on the PCI1031 and, for the selected DMA channel, runs the DMA I/O cycles and

PC/PCI DMA is enabled for each PC Card16 slot by setting bit 19 in the respective system control register (see
T able 16). On power up, bit 19 is cleared, disabling PC/PCI DMA. Bit 3 of each PCI1031 system control register
is a global PC/PCI enable bit. When bit 3 is set, the PCI1031 can request a DMA transfer by asserting IRQ7
(REQ) and encoding the channel request information using the serialized protocol. When the Intel MPIIX gets
control of the PCI bus, it encodes the granted channel on the PCI1031 IRQ11 (GNT) pin. On power up, bit 3
is cleared and PC/PCI DMA is disabled. When the PCI1031 receives a GNT

signal, it looks at the DMA I/O

address to determine the type of transfer. The cycle types are as follows:

DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE

00h Normal 0 I/O read/write
04h Normal TC 1 I/O read/write
C0h Verify 0 I/O read
C4h Verify TC 1 I/O read

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