TEXAS INSTRUMENTS PCA9536 Technical data
4
5
GND
P3
3
P2 SCL
6
2
SDAP1
7
1
P0
V
CC
8
DGKPACKAGE
(TOP VIEW)
GND
P3
5
4
SCLP2
3 6
P1
2
SDA
7
V
CC
8
1
P0
B2B1
C2C1
D2D1
A2A1
YZP PACKAGE
(BOTTOMVIEW)
Seemechanicaldrawingsfordimensions.
4
5
GND
P3
3
P2 SCL
6
2
SDAP1
7
1
P0
V
CC
8
DPACKAGE
(TOP VIEW)
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
www.ti.com
1
FEATURES
2
• Available in the Texas Instruments NanoFree™ • No Glitch on Power Up
Package
• Power-Up With All Channels Configured as
• Low Standby Current Consumption of Inputs
1 μ A Max
• I2C to Parallel Port Expander
• Noise Filter on SCL/SDA Inputs
• Latched Outputs With High-Current Drive
• Operating Power-Supply Voltage Range of Maximum Capability for Directly Driving LEDs
2.3 V to 5.5 V
• Latch-Up Performance Exceeds 100 mA Per
• 5-V Tolerant I/O Ports JESD 78, Class II
• 400-kHz Fast I2C Bus • ESD Protection Exceeds JESD 22
• Input/Output Configuration Register – 2000-V Human-Body Model (A114-A)
• Polarity Inversion Register – 200-V Machine Model (A115-A)
• Internal Power-On Reset – 1000-V Charged-Device Model (C101)
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
PCA9536
DESCRIPTION/ORDERING INFORMATION
T
A
– 40 ° C to 85 ° C
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(3) DGK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
1
2 NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ORDERING INFORMATION
PACKAGE
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOIC – D PCA9536D PD536
VSSOP – DGK Reel of 2500 7C_
(1) (2)
ORDERABLE PART NUMBER
Reel of 3000 PCA9536YZPR 7CH
Reel of 2500
Tube of 75
PCA9536DR
PCA9536DRG4
PCA9536DG4
Reel of 250 PCA9536DT
PCA9536DGKR
PCA9536DGKRG4
Copyright © 2006 – 2007, Texas Instruments Incorporated
TOP-SIDE
MARKING
(3)
www.ti.com
6
I/O
Port
Shift
Register
4 Bits
Input
Filter
7
Power-On
Reset
Read Pulse
Write Pulse
8
4
GND
V
CC
SDA
SCL
I2C Bus
Control
P3−P0
PCA9536
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This 4-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V V
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock
(SCL), serial data (SDA)].
The PCA9536 features 4-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullup
to V
. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O
CC
configuration bits. If no signals are applied externally to the PCA9536, the voltage level is 1, or high, because of
the internal pullup resistors. The data for each input or output is stored in the corresponding Input Port or Output
Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All
registers can be read by the system master.
The system master can reset the PCA9536 in the event of a timeout or other improper operation by utilizing the
power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine.
The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current
consumption.
TERMINAL FUNCTIONS
NO. NAME DESCRIPTION
1 P0 P-port input/output. Push-pull design structure.
2 P1 P-port input/output. Push-pull design structure.
3 P2 P-port input/output. Push-pull design structure.
4 GND Ground
5 P3 P-port input/output. Push-pull design structure.
6 SCL Serial clock bus. Connect to V
7 SDA Serial data bus. Connect to V
8 V
CC
Supply voltage
CC
through a pullup resistor.
CC
through a pullup resistor.
operation. It
CC
LOGIC DIAGRAM
A. All I/Os are set to inputs at reset.
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Product Folder Link(s): PCA9536
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Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity
Pulse
Data From
Shift Register
Output Port
Register
Configuration
Register
Input Port
Register
Polarity
Inversion
Register
Polarity
Register Data
Input Port
Register Data
GND
ESD Protection
Diode
P0 to P3
V
CC
Output Port
Register Data
Q1
Q2
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
100 kW
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SIMPLIFIED SCHEMATIC OF P0 TO P3
PCA9536
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak
pullup (100 k Ω typ) to V
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either V
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1 ). After the Start condition, the device address byte
is sent, most-significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2 ).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1 ).
A. At power-on reset, all registers return to default values.
. The input voltage may be raised above V
CC
to a maximum of 5.5 V.
CC
or GND. The external voltage
CC
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SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9536
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
Figure 3. Acknowledgment on the I2C Bus
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1 0
Slave Address
R/W
Fixed
10000
0 0 0 0 B1 B000
PCA9536
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
Interface Definition
BYTE
I2C slave address H L L L L L H R/ W
Px I/O data bus P3 P2 P1 P0
7 (MSB) 6 5 4 3 2 1 0 (LSB)
Does not affect operation of the PCA9536
P7 P6 P5 P4
Device Address
Figure 4 shows the address byte of the PCA9536.
Figure 4. PCA9536 Address
BIT
The slave address equates to 65 (decimal) and 41 (hexadecimal).
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and
the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
B1 B0
0 0 0x00 Input Port Read byte 1111 XXXX
0 1 0x01 Output Port Read/write byte 1111 1111
1 0 0x02 Polarity Inversion Read/write byte 0000 0000
1 1 0x03 Configuration Read/write byte 1111 1111
COMMAND BYTE POWER-UP
(HEX) DEFAULT
REGISTER PROTOCOL
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PCA9536
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to instruct the I2C device that the
Input Port register will be accessed next.
Register 0 (Input Port Register)
BIT I3 I2 I1 I0
DEFAULT 1 1 1 1 X X X X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
BIT O3 O2 O1 O0
DEFAULT 1 1 1 1 1 1 1 1
I7 I6 I5 I4
Not Used
Register 1 (Output Port Register)
O7 O6 O5 O4
Not Used
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Register 2 (Polarity Inversion Register)
BIT N3 N2 N1 N0
DEFAULT 0 0 0 0 0 0 0 0
N7 N6 N5 N4
Not Used
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register)
BIT C3 C2 C1 C0
DEFAULT 1 1 1 1 1 1 1 1
C7 C6 C5 C4
Not Used
Power-On Reset
When power (from 0 V) is applied to V
V
has reached V
CC
. At that time, the reset condition is released and the PCA9536 registers and I2C/SMBus
POR
state machine initialize to their default states. After that, V
the operating voltage for a power-reset cycle.
, an internal power-on reset holds the PCA9536 in a reset condition until
CC
must be lowered to below 0.2 V and then back up to
CC
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SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave
ACK From Slave
ACK From Slave
1 98765432
Data 1101 0S 00 0 1 0 A 0000000 A A P
t
pv
Data to PortCommand ByteSlave Address
Data101 0S 00 0 1 0 A 1000000 A A P
SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data to RegisterCommand ByteSlave Address
PCA9536
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
Bus Transactions
Data is exchanged between the master and PCA9536 through write and read commands.
Writes
Data is transmitted to the PCA9536 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission (see Figure 6 and Figure 7 ).
Figure 6. Write to Output Port Register
<br/>
Figure 7. Write to Configuration or Polarity Inversion Registers
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01 0S 00 0 1 0 A A
Data from Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
ACK From
Slave
S 01 0 00 0 1
R/W
1 A Data
A
ACK From
Master
Data
Data from Register
NACK From Master
NA
P
Last Byte
ACK From
Slave
At this time, the master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
SCL
SDA
Start
Condition
R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 98765432
01 0S 00 0 1 0 A
Data 1 Data 4
A NA
P
Data 2 Data 3 Data 4
t
ph
t
ps
Data 5
PCA9536
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
Reads
The bus master first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the PCA9536 (see Figure 8 and Figure 9 ). After a restart, the value of the register
defined by the command byte matches the register being accessed when the restart occurred. Data is clocked
into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes
received in one read transmission, but when the final byte is received, the bus master must not acknowledge the
data.
Figure 8. Read From Register
<br/>
A. This figure assumes that the command byte previously has been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and the slave address call between the initial slave
address call and actual data transfer from the P-port (see Figure 8 ).
Figure 9. Read Input Port Register
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REMOTE 4-BIT I2C AND SMBus I/O EXPANDER
WITH CONFIGURATION REGISTERS
SCPS125E – APRIL 2006 – REVISED OCTOBER 2007
PCA9536
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
V
I
V
O
I
IK
I
OK
I
IOK
I
OL
I
OH
I
CC
θ
JA
T
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage range – 0.5 6 V
Input voltage range
Output voltage range
(2)
(2)
– 0.5 6 V
– 0.5 6 V
Input clamp current VI< 0 – 20 mA
Output clamp current VO< 0 – 20 mA
Input/output clamp current VO< 0 or VO> V
Continuous output low current VO= 0 to V
Continuous output high current VO= 0 to V
CC
CC
CC
Continuous current through GND – 200
Continuous current through V
CC
D package 97
Package thermal impedance
(3)
DGK package 172 ° C/W
YZP package 102
Storage temperature range – 65 150 ° C
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
± 20 mA
50 mA
– 50 mA
160
mA
Recommended Operating Conditions
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply voltage 2.3 5.5 V
High-level input voltage V
Low-level input voltage V
High-level output current P3 – P0 – 10 mA
Low-level output current P3 – P0 25 mA
Operating free-air temperature – 40 85 ° C
MIN MAX UNIT
SCL, SDA 0.7 × V
CC
P3 – P0 2 5.5
SCL, SDA – 0.5 0.3 × V
P3 – P0 – 0.5 0.8
5.5
CC
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