查询OPA3690供应商查询OPA3690供应商
OPERATIONAL AMPLIFIER With Disable
O
P
A
6
9
1
O
P
A
6
9
1
SBOS226A – DECEMBER 2001– REVISED SEPTEMBER 2002
Wideband, Current Feedback
OPA691
FEATURES
●
FLEXIBLE SUPPLY RANGE:
+5V to +12V Single-Supply
±
2.5V to ±6V Dual-Supply
●
UNITY-GAIN STABLE: 280MHz (G = 1)
● HIGH OUTPUT CURRENT: 190mA
● OUTPUT VOLTAGE SWING: ±4.0V
● HIGH SLEW RATE: 2100V/µs
● LOW dG/dφ: 0.07%/0.02°
● LOW SUPPLY CURRENT: 5.1mA
● LOW DISABLED CURRENT: 150µA
●
WIDEBAND +5V OPERATION: 190MHz (G = +2)
DESCRIPTION
The OPA691 sets a new level of performance for broadband
current feedback op amps. Operating on a very low 5.1mA
supply current, the OPA691 offers a slew rate and output
power normally associated with a much higher supply current. A new output stage architecture delivers a high output
current with minimal voltage headroom and crossover distortion. This gives exceptional single-supply operation. Using a
single +5V supply, the OPA691 can deliver a 1V to 4V output
swing with over 150mA drive current and 190MHz bandwidth. This combination of features makes the OPA691 an
ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver.
The OPA691’s low 5.1mA supply current is precisely trimmed
at 25°C. This trim, along with low drift over-temperature,
APPLICATIONS
● xDSL LINE DRIVER
● BROADBAND VIDEO BUFFERS
● HIGH-SPEED IMAGING CHANNELS
● PORTABLE INSTRUMENTS
● ADC BUFFERS
● ACTIVE FILTERS
● WIDEBAND INVERTING SUMMING
● HIGH SFDR IF AMPLIFIER
ensures lower maximum supply current than competing
products. System power may be further reduced by using the
optional disable control pin. Leaving this disable pin open, or
holding it HIGH, gives normal operation. If pulled LOW, the
OPA691 supply current drops to less than 150µA while the
output goes into a high impedance state. This feature may be
used for power savings.
OPA691 RELATED PRODUCTS
SINGLES DUALS TRIPLES
Voltage Feedback OPA690 OPA2690 OPA3690
Current Feedback OPA681 OPA2691 OPA3691
Fixed Gain OPA692 OPA3692
+5V
DIS
50Ω
V
1
50Ω
V
2
50Ω
V
3
50Ω
V
4
50Ω
V
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
50Ω
OPA691
30Ω
100Ω
–5V
RG-58
100MHz, –1dB Compression = 15dBm
200MHz RF Summing Amplifier
Copyright © 2001, Texas Instruments Incorporated
www.ti.com
VO = –(V1 + V2 + V3 + V4 + V5)
50Ω
ABSOLUTE MAXIMUM RATINGS
Power Supply .............................................................................. ±6.5VDC
Internal Power Dissipation
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±V
Storage Temperature Range: ID, IDBV ......................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (T
ESD Performance:
HBM .............................................................................................. 2000V
CDM.............................................................................................. 1500V
NOTES:: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Packages must be derated based on specified
Maximum T
must be observed.
J
(2)
............................ See Thermal Information
) ........................................................... +175°C
J
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
S
θ
JA
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
.
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD DESIGNATOR
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
OPA691ID SO-8 D –40°C to +85°C OPA691 OPA691ID Rails, 100
(1)
"" " ""OPA691IDR Tape and Reel, 2500
OPA691IDBV SOT23-6 DBV –40°C to +85°C OAFI OPA691IDBVT Tape and Reel, 250
"" " ""OPA691IDBVR Tape and Reel, 3000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
SPECIFIED
RANGE MARKING NUMBER MEDIA, QUANTITY
PIN CONFIGURATION
Top View SO
NC
Inverting Input
Noninverting Input
–V
1
2
3
4
S
NC = No Connection
8
7
6
5
DIS
+V
S
Output
NC
Top View SOT
Output
–V
Noninverting Input
1
2
S
3
654
6
+V
S
5
DIS
4
Inverting Input
OAFI
123
Pin Orientation/Package Marking
2
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OPA691
SBOS226A
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 402Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.
OPA691ID, IDBV
TYP MIN/MAX OVER-TEMPERATURE
0°C to –40°C to
PARAMETER CONDITIONS +25°C +25°C
(1)
70°C
(2)
+85°C
(2)
UNITS MAX
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (V
Bandwidth for 0.1dB Gain Flatness G = +2, V
Peaking at a Gain of +1 R
Large-Signal Bandwidth G = +2, VO = 5Vp-p 200 MHz typ C
= 0.5Vp-p) G = +1, RF = 453Ω 280 MHz typ C
O
G = +2, RF = 402Ω 225 200 190 180 MHz min B
G = +5, R
G = +10, R
= 453, VO = 0.5Vp-p 0.2 1 1.5 2 dB max B
F
= 261Ω 210 MHz typ C
F
= 180Ω 200 MHz typ C
F
= 0.5Vp-p 90 40 35 20 MHz min B
O
Slew Rate G = +2, 4V Step 2100 1400 1375 1350 V/µsminB
Rise-and-Fall Time G = +2, VO = 0.5V Step 1.6 ns typ C
G = +2, 5V Step 1.9 ns typ C
Settling Time to 0.02% G = +2, VO = 2V Step 12 ns typ C
0.1% G = +2, VO = 2V Step 8 ns typ C
Harmonic Distortion G = +2, f = 5MHz, V
2nd-Harmonic R
3rd-Harmonic RL = 100Ω –74 –72 –70 –68 dBc max B
L
R
L
= 2Vp-p
O
= 100Ω –70 –63 –60 –58 dBc max B
≥ 500Ω –79 –70 –67 –65 dBc max B
RL ≥ 500Ω –93 –87 –82 –78 dBc max B
Input Voltage Noise f > 1MHz 1.7 2.5 2.9 3.1 nV/√HZ max B
Noninverting Input Current Noise f > 1MHz 12 14 15 15 pA/√HZ max B
Inverting Input Current Noise f > 1MHz 15 17 18 19 pA/√HZ max B
Differential Gain G = +2, NTSC, VO = 1.4Vp, RL = 150Ω 0.07 % typ C
RL = 37.5Ω 0.17 % typ C
Differential Phase G = +2, NTSC, VO = 1.4Vp, RL = 150Ω 0.02 deg typ C
RL = 37.5Ω 0.07 deg typ C
DC PERFORMANCE
Open-Loop Transimpedance Gain (ZOL)
(4)
VO = 0V, RL = 100Ω 225 125 110 100 kΩ min A
Input Offset Voltage VCM = 0V ±0.5 ±2.5 ±3.2 ±3.9 mV max A
Average Offset Voltage Drift VCM = 0V ±12 ±20 µV/°CmaxB
Noninverting Input Bias Current VCM = 0V +15 +35 +43 +45 µAmaxA
Average Noninverting Input Bias Current Drift VCM = 0V –300 –300 nA/°CmaxB
Inverting Input Bias Current VCM = 0V ±5 ±25 ±30 ±40 µAmaxA
Average Inverting Input Bias Current Drift V
INPUT
Common-Mode Input Range
(5)
= 0V ±90 ±200 nA°/C max B
CM
±3.5 ±3.4 ±3.3 ±3.2 V min A
Common-Mode Rejection VCM = 0V 56 52 51 50 dB min A
Noninverting Input Impedance 100 || 2 kΩ || pF typ C
Inverting Input Resistance (RI)
Open-Loop 35 Ω typ C
OUTPUT
Voltage Output Swing No Load ±4.0
±3.8 ±3.7 ±3.6 V min A
100Ω Load ±3.9 ±3.7 ±3.6 ±3.3 V min A
Current Output, Sourcing VO = 0 +190 +160 +140 +100 mA min A
Current Output, Sinking VO = 0 –190 –160 –140 –100 mA min A
Short-Circuit Current VO = 0 ±250 mA typ C
Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ω typ C
DISABLE (Disabled LOW)
Power-Down Supply Current (+V
Disable Time VIN = 1V 400 ns typ C
)V
S
= 0 –150 –300 –350 –400 µAmaxA
DIS
Enable Time VIN = 1V 25 ns typ C
Off Isolation G = +2, 5MHz 70 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, RL = 150Ω, VIN = 0 ±50 mV typ C
Turn Off Glitch G = +2, RL = 150Ω, VIN = 0 ±20 mV typ C
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) V
= 0 75 130 150 160 µAmaxA
DIS
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Maximum Operating Voltage Range
±6 ±6 ±6VmaxA
Max Quiescent Current VS = ±5V 5.1 5.3 5.5 5.7 mA max A
Min Quiescent Current VS = ±5V 5.1 4.9 4.7 4.5 mA min A
Power-Supply Rejection Ratio (–PSRR) Input Referred 58 52 50 49 dB min A
TEMPERATURE RANGE
Specification: D, DBV
Thermal Resistance,
DSO-8 125 °C/W typ C
θ
JA
Junction-to-Ambient
–40 to +85
DBV SOT23-6 150 °C/W typ C
NOTES: (1) Junction temperature = ambient for 25°C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +10°C
at high temperature limit for over-temperature specifications. (3) Test levels: (A) 100% tested at 25°C. Over-temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V
voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
is the input common-mode
CM
MIN/
TEST
LEVEL
°C typ C
(3)
OPA691
SBOS226A
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3
ELECTRICAL CHARACTERISTICS: VS = +5V
Bolace limits are tested at +25°C.
RF = 453Ω, RL = 100Ω to VS/2, and G = +2, (see Figure 2 for AC performance only), unless otherwise noted.
OPA691ID, IDBV
TYP MIN/MAX OVER-TEMPERATURE
PARAMETER CONDITIONS +25°C +25°C
(1)
70°C
(2)
+85°C
(2)
UNITS MAX
0°C to –40°C to
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth (V
Bandwidth for 0.1dB Gain Flatness G = +2, V
Peaking at a Gain of +1 R
Large-Signal Bandwidth G = +2, V
Slew Rate G = +2, 2V Step 850 600 575 550 V/µsminB
= 0.5Vp-p) G = +1, RF = 499Ω 210 MHz typ C
O
G = +2, R
G = +5, RF = 340Ω 180 MHz typ C
G = +10, R
= 649Ω, VO < 0.5Vp-p 0.2 1 2.5 3.0 dB max B
F
= 453Ω 190 168 160 140 MHz min B
F
= 180Ω 155 MHz typ C
F
< 0.5Vp-p 90 40 30 25 MHz min B
O
= 2Vp-p 210 MHz typ C
O
Rise-and-Fall Time G = +2, VO = 0.5V Step 2.0 ns typ C
Settling Time to 0.02% G = +2, V
G = +2, V
0.1% G = +2, V
Harmonic Distortion G = +2, f = 5MHz, V
2nd-Harmonic R
R
3rd-Harmonic RL = 100Ω to VS/2 –71 –68 –67 –65 dBc max B
= 2V Step 2.3 ns typ C
O
= 2V Step 14 ns typ C
O
= 2V Step 10 ns typ C
O
= 2Vp-p
= 100Ω to VS/2 –66 –58 –57 –56 dBc max B
L
≥ 500Ω to VS/2 –73 –65 –63 –62 dBc max B
L
O
RL ≥ 500Ω to VS/2 –77 –72 –70 –69 dBc max B
Input Voltage Noise f > 1MHz 1.7 2.5 2.9 3.1 nV/√Hz typ B
Noninverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz typ B
Inverting Input Current Noise f > 1MHz 15 17 18 19 pA/√Hz typ B
DC PERFORMANCE
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage V
Average Offset Voltage Drift V
Noninverting Input Bias Current V
Average Noninverting Input Bias Current Drift V
Inverting Input Bias Current V
Average Inverting Input Bias Current Drift V
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
(4)
VO = VS/2, RL = 100Ω to VS/2 200 100 90 80 kΩ min A
= 2.5V ±0.5 ±3 ±3.6 ±4.3 mV max A
CM
= 2.5V ±12 ±20 µV/°CmaxB
CM
= 2.5V +20 +40 +46 +56 µAmaxA
CM
= 2.5V –250 –250 nA/°CmaxB
CM
= 2.5V ±5 ±20 ±25 ±35 µAmaxA
CM
= 2.5V ±112 ±250 nA/°Cmax B
CM
(5)
(5)
1.5 1.6 1.7 1.8 V max A
3.5 3.4 3.3 3.2 V min A
VCM = VS/2 54 50 49 48 dB min A
Noninverting Input Impedance 100 || 2 kΩ || pF typ C
Inverting Input Resistance (RI)
Open-Loop 38 Ω typ C
OUTPUT
Most Positive Output Voltage No Load 4 3.8 3.7 3.5 V min A
R
= 100Ω to VS/2 3.9 3.7 3.6 3.4 V min A
Least Positive Output Voltage No Load 1 1.2 1.3 1.5 V max A
Current Output, Sourcing V
Current Output, Sinking V
Short-Circuit Current V
Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ω typ C
L
= 100Ω to VS/2 1.1 1.3 1.4 1.6 V max A
R
L
= VS/2 +160 +120 +100 +80 mA min A
O
= VS/2 –160 –120 –100 –80 mA min A
O
= VS/2 250 mA typ C
O
DISABLE (Disabled LOW)
Power-Down Supply Current (+V
Off Isolation G = +2, 5MHz 65 dB typ C
)V
S
= 0 –150 –300 –350 –400 µAmaxA
DIS
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, R
Turn Off Glitch G = +2, R
Enable Voltage 3.3 3.5 3.6 3.7 V min A
= 150Ω, VIN = VS /2 ±50 mV typ C
L
= 150Ω, VIN = VS /2 ±20 mV typ C
L
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) V
= 0 75 130 150 160 µA typ C
DIS
POWER SUPPLY
Specified Single-Supply Operating Voltage 5 V typ C
Max Single-Supply Operating Voltage 12 12 12 V max A
Max Quiescent Current V
Min Quiescent Current V
Power-Supply Rejection Ratio (–PSRR) Input Referred 55 dB typ C
= +5V 4.5 4.8 5.0 5.2 mA max A
S
= +5V 4.5 4.1 4.0 3.8 mA min A
S
TEMPERATURE RANGE
Specification: D, DBV
Thermal Resistance,
DSO-8 125 °C/W typ C
θ
JA
Junction-to-Ambient
–40 to +85
DBV SOT23-6 150 °C/W typ C
NOTES: (3) Test levels: (A) 100% tested at 25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (1) Junction temperature = ambient for 25°C specifications. (2) Junction temperature = ambient at low temperature limit: junction
temperature = ambient +10°C at high temperature limit for over-temperature specifications. (3) Test levels: (A) 100% tested at 25°C. Over-temperature limits by
characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node.
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.
V
CM
MIN/
TEST
LEVEL
°C typ C
(3)
4
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OPA691
SBOS226A
TYPICAL CHARACTERISTICS: VS = ±5V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Frequency (25MHz/div)
0 250MHz125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (0.5dB/div)
G = +2, RL = 100Ω
4Vp-p
7Vp-p
1Vp-p
2Vp-p
G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1).
1
SMALL-SIGNAL FREQUENCY RESPONSE
0
–1
–2
–3
–4
–5
–6
Normalized Gain (1dB/div)
–7
VO = 0.5Vp-p
–8
0 250MHz125MHz
SMALL-SIGNAL PULSE RESPONSE
+400
+300
+200
+100
0
–100
–200
Output Voltage (100mV/div)
–300
–400
G = +1, RF = 453Ω
G = +5, RF = 261Ω
G = +10, RF = 180Ω
Frequency (25MHz/div)
Time (5ns/div)
G = +2,
R
F
G = +2
V
= 0.5Vp-p
O
= 402Ω
+4
LARGE-SIGNAL PULSE RESPONSE
+3
+2
+1
0
–1
–2
Output Voltage (1V/div)
–3
–4
Time (5ns/div)
G = +2
V
= 5Vp-p
O
dG/dP (%/°)
OPA691
SBOS226A
0.2
0.18
0.16
0.14
+5
Video
In
402Ω
OPA691
–5
402Ω
Optional 1.3kΩ
Pull-Down
Video
Loads
0.12
0.1
0.08
0.06
0.04
0.02
COMPOSITE VIDEO dG/dP
0
12
Number of 150Ω Loads
No Pull-Down
With 1.3kΩ Pull-Down
dG
dG
dP
dP
34
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–45
V
= 0
–50
DIS
–55
–60
–65
–70
–75
DISABLED FEEDTHROUGH vs FREQUENCY
–80
Reverse
–85
Feedthrough (5dB/div)
–90
–95
–100
Forward
10.3 10 100
Frequency (MHz)
5
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1).
–60
–65
–70
–75
–80
–85
–90
Harmonic Distortion (dBc)
–95
–100
–50
–60
–70
–80
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2Vp-p
f = 5MHz
2nd-Harmonic
3rd-Harmonic
100 1000
Load Resistance (Ω)
HARMONIC DISTORTION vs FREQUENCY
dBc = dB Below Carrier
VO = 2Vp-p
R
= 100Ω
L
2nd-Harmonic
3rd-Harmonic
–60
–65
–70
–75
Harmonic Distortion (dBc)
–80
–85
–65
–70
–75
HARMONIC DISTORTION vs SUPPLY VOLTAGE
2nd-Harmonic
3rd-Harmonic
2.5 3 3.5 4 4.5 65.55
Supply Voltage (V)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
RL = 100Ω
f = 5MHz
VO = 2Vp-p
R
f = 5MHz
2nd-Harmonic
3rd-Harmonic
= 100Ω
L
–90
Harmonic Distortion (dBc)
–100
0.1 1 10 20
Frequency (MHz)
HARMONIC DISTORTION vs NONINVERTING GAIN
–50
VO = 2Vp-p
R
= 100Ω
L
f = 5MHz
–60
–70
–80
Harmonic Distortion (dBc)
–90
110
2nd-Harmonic
3rd-Harmonic
Gain (V/V)
–80
Harmonic Distortion (dBc)
–85
0.1 1 5
Output Voltage Swing (Vp-p)
–50
–60
–70
–80
Harmonic Distortion (dBc)
–90
HARMONIC DISTORTION vs INVERTING GAIN
VO = 2Vp-p
R
= 100Ω
L
f = 5MHz
R
= 402Ω
F
110
2nd-Harmonic
3rd-Harmonic
Inverting Gain (V/V)
6
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OPA691
SBOS226A
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
9
6
3
0
–3
–6
–9
Frequency (25MHz/div)
0 250MHz125MHz
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
OPA691
R
S
V
IN
V
O
C
L
1kΩ
402Ω
402Ω
1kΩ is optional.
CL = 22pF
CL = 10pF
CL = 47pF
CL = 100pF
G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1).
INPUT VOLTAGE AND CURRENT NOISE DENSITY
100
Inverting Input Current Noise (15pA/√Hz)
10
Noninverting Input Current Noise (12pA/√Hz)
Current Noise (pA/√Hz)
Voltage Noise (nV/√Hz)
Voltage Noise (1.7nV/√Hz)
1
100 1k 10k 100k 1M 10M
Frequency (Hz)
70
RECOMMENDED R
vs CAPACITIVE LOAD
S
60
50
40
(Ω)
S
R
30
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
–30
dBc = dB below carriers
50MHz
–40
–50
–60
10MHz
–70
–80
3rd-Order Spurious Level (dBc)
–90
Load Power at Matched 50Ω Load
–8 –6 –4 –20246810
Single-Tone Load Power (dBm)
20MHz
20
10
0
1101001k
65
60
55
50
45
40
35
30
25
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
20
1k 10k 100k 1M 10M 100M
OPA691
SBOS226A
Capacitive Load (pF)
CMRR AND PSRR vs FREQUENCY
–PSRR
Frequency (Hz)
+PSRR
CMRR
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120
OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE
100
80
∠ Z
|ZOL|
OL
60
40
20
Transimpedance Gain (20dBΩ/div)
0
10k 100k 1M 10M 100M 1G
Frequency (Hz)
0
–40
–80
–120
–160
–200
–240
7
Transimpedance Phase (40°/div)
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
30
20
10
0
–10
–20
–30
DISABLE/ENABLE GLITCH
Time (20ns/div)
Output Voltage (10mV/div)
6.0
4.0
2.0
0
V
DIS
(2V/div)
V
DIS
Output Voltage
(0V Input)
VIN = 0V
G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted (see Figure 1).
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
10
Sourcing Output Current
8
Sinking Output Current
6
4
Supply Current (2mA/div)
2
0
–50 –25 0 25 50 75 100 125
Quiescent Supply Current
Ambient Temperature (°C)
TYPICAL DC DRIFT OVER TEMPERATURE
2
1.5
1
Noninverting Input Bias Current (IB+)
0.5
0
–0.5
–1
Input Offset Voltage (mV)
–1.5
Inverting Input
Bias Current (I
)
B–
Input Offset
Voltage (V
–2
–50 –25 0 25 50 75 100 125
Ambient Temperature (°C)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
250
200
5
4
3
1W Internal
Power Limit
Output Current Limit
2
150
100
Output Current (50mA/div)
50
0
1
(V)
0
O
V
–1
–2
–3
–4
Output Current Limit
–5
25Ω
Load Line
50Ω Load Line
100Ω Load Line
1W Internal
Power Limit
–150–200–250–300 –50–100 0 +100+50 +200+150 +250 +300
I
(mA)
O
CLOSED-LOOP OUTPUT IMPEDANCE
Z
402Ω
vs FREQUENCY
O
40
30
20
10
0
–10
–20
Input Bias Currents (µA)
–30
)
OS
–40
10
50Ω
+5
OPA691
1
–5
402Ω
0.1
Output Impedance (Ω)
0.01
10k 100M100k 1M 10M
Frequency (Hz)
2.0
1.6
1.2
0.8
0.4
Output Voltage (400mV/div)
0
8
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
V
DIS
Output Voltage
VIN = +1V
Time (200ns/div)
6.0
4.0
(2V/div)
2.0
DIS
V
0
www.ti.com
OPA691
SBOS226A
TYPICAL CHARACTERISTICS: VS = +5V
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
G = +2
V
O
= 2Vp-p
9
6
3
0
–3
–6
–9
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (25MHz/div)
0 250MHz125MHz
Normalized Gain to Capacitive Load (dB)
CL = 22pF
CL = 10pF
CL = 47pF
CL = 100pF
OPA691
453Ω
453Ω
57.6Ω 806Ω
806Ω
1kΩ
V
I
+5V
0.1µF
V
O
R
S
C
L
0.1µF
1kΩ is optional.
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Frequency (25MHz/div)
0 250MHz125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (0.5dB/div)
VO = 0.5Vp-p
VO = 2Vp-p
G = +2
R
L
= 100Ω to 2.5V
VO = 1Vp-p
G = +2, RF = 453Ω, and RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2).
1
SMALL-SIGNAL FREQUENCY RESPONSE
0
–1
–2
–3
–4
–5
–6
Normalized Gain (1dB/div)
–7
VO = 0.5Vp-p
–8
0 250MHz125MHz
Frequency (25MHz/div)
SMALL-SIGNAL PULSE RESPONSE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
Output Voltage (100mV/div)
2.2
2.1
G = +5,
= 340Ω
R
F
Time (5ns/div)
G = +10,
= 180Ω
R
F
G = +1,
= 499Ω
R
F
G = +2,
= 453Ω
R
F
G = +2
V
= 0.5Vp-p
O
60
50
40
(Ω)
30
S
R
20
10
0
1 10 100
OPA691
SBOS226A
RECOMMENDED R
Capacitive Load (pF)
vs CAPACITIVE LOAD
S
www.ti.com
9
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
G = +2, RF = 453Ω, and RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2).
–60
–65
–70
–75
Harmonic Distortion (dBc)
–80
–60
–65
–70
–75
Harmonic Distortion (dBc)
–80
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2Vp-p
f
= 5MHz
2nd-Harmonic
3rd-Harmonic
100 1000
Resistance (Ω)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
RL = 100Ω to 2.5V
f = 5MHz
0.1 1 3
Output Voltage Swing (Vp-p)
2nd-Harmonic
3rd-Harmonic
–50
–60
–70
–80
Harmonic Distortion (dBc)
–90
–30
–40
–50
–60
–70
–80
–90
3rd-Order Spurious Level (dBc)
–100
–14 –12 –10 –8 –6 –4 –20 2
HARMONIC DISTORTION vs FREQUENCY
VO = 2Vp-p
R
= 100Ω to 2.5V
L
2nd-Harmonic
3rd-Harmonic
0.1 1 10 20
Frequency (MHz)
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50Ω Load
Single-Tone Load Power (dBm)
10
www.ti.com
OPA691
SBOS226A
APPLICATIONS INFORMATION
OPA691
+5V
DIS
VS/2
806Ω
100ΩV
O
V
I
+V
S
57.6Ω
806Ω
R
F
453Ω
R
G
453Ω
0.1µF
0.1µF
6.8µF
+
0.1µF
WIDEBAND CURRENT FEEDBACK OPERATION
The OPA691 gives the exceptional AC performance of a
wideband current feedback op amp with a highly linear, high
power output stage. Requiring only 5.1mA quiescent current,
the OPA691 will swing to within 1V of either supply rail and
deliver in excess of 160mA at room temperature. This low
output headroom requirement, along with supply voltage
independent biasing, gives remarkable single (+5V) supply
operation. The OPA691 will deliver greater than 200MHz
bandwidth driving a 2Vp-p output into 100Ω on a single +5V
supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the
output current goes through zero. The OPA691 achieves a
comparable power gain with much better linearity. The primary advantage of a current feedback op amp over a voltage
feedback op amp is that AC performance (bandwidth and
distortion) is relatively independent of signal gain. For similar
AC performance at low gains, with improved DC accuracy,
consider the high slew rate, unity-gain stable, voltage feedback OPA690.
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V
Electrical Characteristic tables and Typical Characteristic
curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground and the output impedance is set to
50Ω with a series output resistor. Voltage swings reported in
the specifications are taken directly at the input and output
pins while load powers (dBm) are defined at a matched 50Ω
load. For the circuit of Figure 1, the total effective load will be
100Ω || 804Ω = 89Ω. The disable control line (
typically left open to ensure normal amplifier operation. One
optional component is included in Figure 1. In addition to the
usual power-supply de-coupling capacitors to ground, a
0.1µF capacitor is included between the two power-supply
DIS
) is
pins. In practical PC board layouts, this optional added
capacitor will typically improve the 2nd-harmonic distortion
performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Electrical
Characteristic tables and Typical Characteristic curves.
Though not a “rail-to-rail” design, the OPA691 requires minimal input and output voltage headroom compared to other
very wideband current feedback op amps. It will deliver a
3Vp-p output swing on a single +5V supply with greater than
150MHz bandwidth. The key requirement of broadband singlesupply operation is to maintain input and output signal
swings within the usable voltage ranges at both the input and
the output. The circuit of Figure 2 establishes an input
midpoint bias using a simple resistive divider from the +5V
supply (two 806Ω resistors). The input signal is then ACcoupled into this midpoint voltage bias. The input voltage can
swing to within 1.5V of either supply pin, giving a 2Vp-p input
signal range centered between the supply pins. The input
impedance matching resistor (57.6Ω) used for testing is
adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain
resistor (R
) is AC-coupled, giving the circuit a DC gain of
G
+1—which puts the input DC bias voltage (2.5V) on the
output as well. The feedback resistor value has been adjusted from the bipolar supply condition to re-optimize for a
flat frequency response in +5V, gain of +2, operation (see
Setting Resistor Values to Optimize Bandwidth). Again, on a
single +5V supply, the output voltage can swing to within 1V
of either supply pin while delivering more than 120mA output
current. A demanding 100Ω load to a mid-point bias is used
in this characterization circuit. The new output stage used in
the OPA691 can deliver large bipolar output currents into this
mid-point load with minimal crossover distortion, as shown by
the +5V supply, 3rd-harmonic distortion plots.
+5V
+V
–V
S
S
+
OPA691
402Ω
–5V
R
F
6.8µF
+
DIS
O
50ΩV
0.1µF
50Ω Load
FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification
www.ti.com
and Test Circuit.
11
0.1µF 6.8µF
50Ω Source
V
I
50Ω
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-
OPA691
SBOS226A
tion and Test Circuit.
R
402Ω
0.1µF
G
SINGLE-SUPPLY ADC INTERFACE
Most modern, high performance ADCs (such as the Texas
Instruments ADS8xx and ADS9xx series) operate on a single
+5V (or lower) power supply. It has been a considerable
challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies
exceeding 5MHz. The high slew rate, exceptional output
swing, and high linearity of the OPA691 make it an ideal
single-supply ADC driver. Figure 3 shows an example input
interface to a very high performance, 10-bit, 60MSPS CMOS
converter.
The OPA691 in the circuit of Figure 3 provides > 180MHz
bandwidth operating at a signal gain of +4 with a 2Vp-p
output swing. One of the primary advantages of the current
feedback internal architecture used in the OPA691 is that
high bandwidth can be maintained as the signal gain is
increased. The noninverting input bias voltage is referenced
to the midpoint of the ADC signal range by dividing off the top
and bottom of the internal ADC reference ladder. With the
gain resistor (R
) AC-coupled, this bias voltage has a gain of
G
+1 to the output, centering the output voltage swing as well.
Tested performance at a 20MHz analog input frequency and
a 60MSPS clock rate on the converter gives > 58dBc SFDR.
WIDEBAND INVERTING SUMMING AMPLIFIER
Since the signal bandwidth for a current feedback op amp may
be controlled independently of the noise gain (NG, which is
normally the same as the noninverting signal gain), very
broadband inverting summing stages may be implemented
using the OPA691. The circuit on the front page of this data
sheet shows an example inverting summing amplifier where
the resistor values have been adjusted to maintain both
maximum bandwidth and input impedance matching. If each
RF signal is assumed to be driven from a 50Ω source, the NG
for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The total
feedback impedance (from V
to the inverting error current) is
O
the sum of R
+ (RI • NG) where RI is the impedance looking
F
into the inverting input from the summing junction (see the
Setting Resistor Values to Optimize Performance section).
Using 100Ω feedback (to get a signal gain of –2 from each
input to the output pin) requires an additional 30Ω in series
with the inverting input to increase the feedback impedance.
With this resistor added to the typical internal R
= 35Ω, the
I
total feedback impedance is 100Ω + (65Ω • 6) = 490Ω, which
is equal to the required value to get a maximum bandwidth flat
frequency response for NG = 6. Tested performance shows
more than 200MHz small-signal bandwidth and a –1dBm
compression of 15dBm at the matched 50Ω load through
100MHz.
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple “Wired-OR
Video Multiplexer” can be easily implemented using the
OPA691, see Figure 4.
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable
characteristic of the OPA691 ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that presented in Figure 4. Since both inputs may
be on for a short period during the transition between
channels, the outputs are combined through the output
impedance matching resistors (82.5Ω in this case). When
one channel is disabled, its feedback network forms part of
the output impedance and slightly attenuates the signal in
getting out onto the cable. The gain and output matching
resistor have been slightly increased to get a signal gain of
+1 at the matched load and provide a 75Ω output impedance
to the cable. The video multiplexer connection (see Figure 4)
+5V
R
F
360Ω
R
120Ω
0.1µF
G
OPA691
+2.5V DC Bias
2Vp-p
DIS
0.1µF
0.5Vp-p
FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver.
12
www.ti.com
50Ω
2kΩ
2kΩ
Clock
22pF
+3.5V
0.1µF
+1.5V
0.1µF
+5V
Input
Input
CM
REFT
REFB
ADS823
10-Bit
60MSPS
OPA691
SBOS226A
also ensures that the maximum differential voltage across
the inputs of the unselected channel do not exceed the rated
±1.2V maximum for standard video signal levels.
The section on Disable Operation shows the turn-on and
turn-off switching glitches using a grounded input for a single
channel is typically less than ±50mV. Where two outputs are
switched (see Figure 6), the output line is always under the
+5V
V
DIS
Video 1
2kΩ
75Ω
control of one amplifier or the other due to the “make-beforebreak” disable timing. In this case, the switching glitches for
two 0V inputs drop to < 20mV.
4-CHANNEL FREQUENCY CHANNELIZER
The circuit of Figure 5 is a 4-channel multiplexer. In this
circuit the OPA691 provides the drive for all 4 channels.
+5V
DIS
OPA691
Video 2
FIGURE 4. 2-Channel Video Multiplexer.
75Ω
75Ω
+5V
OPA691
–5V
75Ω
–5V
402Ω340Ω
402Ω340Ω
+5V
OPA691
75Ω
2kΩ
#1
75Ω
#2
75Ω
#3
75Ω
–5V
402Ω
402Ω
DIS
+5V
OPA691
–5V
402Ω
+5V
OPA691
–5V
402Ω
+5V
OPA691
–5V
402Ω
DIS 1
DIS 2
DIS 3
59Ω
R
59Ω
R
59Ω
R
O
O
O
82.5Ω
82.5Ω
75Ω Cable
RG-59
75Ω Cable
RG-59
75Ω Load
V
OUT
75Ω
FIGURE 5. 4-Channel Frequency Channelizer.
OPA691
SBOS226A
402Ω
+5V
#4
75Ω
OPA691
402Ω
402Ω
www.ti.com
–5V
DIS 4
59Ω
R
O
13
Each channel includes a bandpass filter. Each bandpass
filter is set for a different frequency band. This allows the
channelizing part of this circuit. The role of the channelizers
OPA691s is to provide impedance isolation. This is done
through the use of four matching resistances (59Ω in this
case). These matching resistors ensure that the signals will
combine during the transition between channels. They have
been used to get a gain of +1 at the load.
This circuit may be used with a different number of channels.
Its limitation comes from the drive requirement for each
channel as well as the minimum acceptable return loss.
The output resistor value (R
) to keep a gain of +1 at the load
O
depends on the number of channels. For the OPA691 with a
gain of 2 using R
= 402Ω and RG = 402Ω, Equation 1 is:
F
(1)
–
n
•
75 1 804
ΩΩ
[]
R
=
O
+
(
)
2
•+
1
241200
ΩΩ
•
75 1 804
[]
Ω
–
+
n
(
)
–
1
SINGLE-SUPPLY “IF” AMPLIFIER
The high bandwidth provided by the OPA691 while operating
on a single +5V supply lends itself well to IF amplifier
applications. One of the advantages of using an op amp like
the OPA691 as an IF amplifier is that precise signal gain is
achieved along with much lower 3rd-order intermodulation
versus quiescent power dissipation. In addition, the OPA691
in the SOT23-6 package offers a very small package with a
power shutdown feature for portable applications. One concern with using op amps for an IF amplifier is their relatively
high noise figures. It is sometimes suggested that an optimum source resistance can be used to minimize op amp
noise figures. Adding a resistor to reach this optimum value
may improve the noise figure, but will actually decrease the
signal-to-noise ratio. A more effective way to move towards
an optimum source impedance is to bring the signal in
through an input transformer. Figure 6 shows an example
that is particularly useful for the OPA691.
+5V
Power-supply
decoupling not shown.
5kΩ
5kΩ1µF
OPA691
50Ω Source
V
I
1:2
0.1µF
R
200Ω
G
R
600Ω
V
FIGURE 6. Low-Noise, Single-Supply IF Amplifier.
F
O
= 3V/V (9.54dB)
V
I
DIS
50Ω
50Ω Load
V
O
Bringing the signal in through a step-up transformer to the
inverting input gain resistor has several advantages for the
OPA691. First, the decoupling capacitor on the noninverting
input eliminates the contribution of the noninverting input current
noise to the output noise. Secondly, the noninverting input noise
voltage of the op amp is actually attenuated if reflected to the
input side of R
. Using the 1:2 (turns ratio) step-up transformer
G
reflects the 50Ω source impedance at the primary through to the
secondary as a 200Ω source impedance (and the 200Ω R
resistor is reflected through to the transformer primary as a 50Ω
input matching impedance). The noise gain to the amplifier
output is then 1 + 600/400 = 2.5V/V. Taking the op amp’s
2.2nV/
√Hz
input voltage noise times this noise gain to the
output, then reflecting this noise term to the input side of the R
resistor, divides it by 3. This gives a net gain of 0.833 for the
noninverting input voltage noise when reflected to the input
point for the op amp circuit. This is further reduced when
referred back to the transformer primary.
The relatively low-gain IF amplifier circuit of Figure 6 gives a
12dB noise figure at the input of the transformer. Increasing
the R
resistor to 600Ω (once RG is set to 200Ω for input
F
impedance matching) will slightly reduce the bandwidth.
Measured results show 150MHz small-signal bandwidth for
the circuit of Figure 6 with exceptional flatness through
30MHz. Although the OPA691 does not show an intercept
characteristic for the 2-tone, 3rd-order intermodulation distortion, it does hold a very high Spurious-Free Dynamic Range
(SFDR) through high output powers and frequencies. The
maximum single-tone power at the matched load for the
single-supply circuit of Figure 6 is 1dBm (this requires a
2.8Vp-p swing at the output pin of the OPA691 for the 2-tone
envelope). Measured 2-tone SFDR at this maximum load
power for the circuit of Figure 6 exceeds 55dBc for frequencies to 20MHz.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA691 in its two
package styles. All of these are available free as an
unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown
in the table below.
BOARD LITERATURE
PRODUCT PACKAGE NUMBER NUMBER
OPA691ID SO-8 DEM-OPA68xU SBOU009
OPA691IDBV SOT23-6 DEM-OPA6xxN SBOU010
To request any of these boards, check the Texas Instruments web site at www.ti.com.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and RF
PART REQUEST
G
G
14
www.ti.com
OPA691
SBOS226A
amplifier circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A SPICE
model for the OPA691 is available through the TI web site
(www.ti.com). These models do a good job of predicting
small-signal AC and transient performance under a wide
variety of operating conditions. They do not do as well in
predicting the harmonic distortion or dG/dφ characteristics.
These models do not attempt to distinguish between the
package types in their small-signal AC performance.
OPERATING SUGGESTIONS
R
, the buffer output impedance, is a critical portion of the
I
bandwidth control equation. The OPA691 is typically about 35Ω.
A current feedback op amp senses an error current in the
inverting node (as opposed to a differential input error voltage for a voltage feedback op amp) and passes this on to the
output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop
transimpedance response. This is analogous to the openloop voltage gain curve for a voltage feedback op amp.
Developing the transfer function for the circuit of Figure 7
gives Equation 1:
SETTING RESISTOR VALUES TO
OPTIMIZE BANDWIDTH
A current feedback op amp like the OPA691 can hold an
almost constant bandwidth over signal gain settings with the
proper adjustment of the external resistor values. This is
shown in the Typical Characteristic curves; the small-signal
bandwidth decreases only slightly with increasing gain. Those
curves also show that the feedback resistor has been changed
for each gain setting. The resistor “values” on the inverting
side of the circuit for a current feedback op amp can be
treated as frequency response compensation elements while
their “ratios” set the signal gain. Figure 7 shows the smallsignal frequency response analysis circuit for the OPA691.
V
I
α
V
O
R
I
i
ERR
R
G
FIGURE 7. Recommended Feedback Resistor versus Noise Gain.
The key elements of this current feedback op amp model are:
α → Buffer gain from the noninverting input to the inverting input
→ Buffer output impedance
R
I
→ Feedback error current signal
i
ERR
Z(s) → Frequency dependent open-loop transimpedance gain from i
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however,
set the CMRR for a single op amp differential amplifier configuration. For a buffer gain α < 1.0, the CMRR =
–20 • log (1– α) dB.
R
Z
(S) iERR
F
ERR
to V
αα1
RR
FI
+
1
V
O
=
V
I
R
F
+
R
G
R
Z
1
S
()
F
R
G
++
=
NG
+
RRNG
FI
+
1
=+
NG
1
This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z
were infinite over all frequencies, the
(S)
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation:
Z
S
()
=
+
RRNG
FI
Loop Gain
If 20 • log (RF + NG • RI) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z
to equal the denominator of Equation 2 at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier’s closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage feedback op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG).
The OPA691 is internally compensated to give a maximally flat frequency response for R
= 402Ω at NG = 2 on
F
±5V supplies. Evaluating the denominator of Equation 2
(which is the feedback transimpedance) gives an optimal
target of 472Ω. As the signal gain changes, the contribution of the NG • R
will change, but the total can be held constant by adjust-
O
ing R
. Equation 4 gives an approximate equation for
F
optimum R
F
term in the feedback transimpedance
I
over signal gain:
RNGR
= 472Ω –
FI
(2)
Z
S
R
F
R
G
(3)
rolls off
(S)
(4)
OPA691
SBOS226A
www.ti.com
15
As the desired signal gain increases, this equation will
eventually predict a negative R
to this adjustment can also be set by holding R
. A somewhat subjective limit
F
to a
G
minimum value of 20Ω. Lower values will load both the buffer
stage at the input and the output stage if R
gets too low—
F
actually decreasing the bandwidth. Figure 8 shows the recommended R
operation. The values for R
versus NG for both ±5V and a single +5V
F
versus gain shown here are
F
approximately equal to the values used to generate the
Typical Characteristics. They differ in that the optimized
values used in the Typical Characteristics are also correcting
for board parasitics not considered in the simplified analysis
leading to Equation 3. The values shown in Figure 8 give a
good starting point for design where bandwidth optimization
is desired.
600
500
400
+5V
(e.g., integrators, transimpedance, and some filters) should
consider the unity-gain stable voltage feedback OPA680,
since the feedback resistor is the compensation element for a
current feedback op amp. Wideband inverting operation (and
especially summing) is particularly suited to the OPA691. See
Figure 9 for a typical inverting configuration where the I/O
impedances and signal gain from Figure 1 are retained in an
inverting circuit configuration.
+5V
Power-supply
decoupling
not shown.
50Ω Load
50Ω
V
I
50Ω
Source
R
188Ω
R
M
68.1Ω
DIS
V
OPA691
G
374Ω
O
R
F
300
200
Feedback Resistor (Ω)
100
0
02010 155
±5V
Noise Gain
FIGURE 8. Feedback Resistor vs Noise Gain.
The total impedance going into the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting a
series resistor between the inverting input and the summing
junction will increase the feedback impedance (denominator
of Equation 2), decreasing the bandwidth. This approach to
bandwidth control is used for the inverting summing circuit on
the front page. The internal buffer output impedance for the
OPA691 is slightly influenced by the source impedance
looking out of the noninverting input terminal. High source
resistors will have the effect of increasing R
, decreasing the
I
bandwidth. For those single-supply applications which develop a midpoint bias at the noninverting input through high
valued resistors, the decoupling capacitor is essential for
power-supply noise rejection, noninverting input noise current shunting, and to minimize the high frequency value for
R
in Figure 7.
I
INVERTING AMPLIFIER OPERATION
Since the OPA691 is a general-purpose, wideband current
feedback op amp, most of the familiar op amp application
circuits are available to the designer. Those applications that
require considerable flexibility in the feedback element
–5V
FIGURE 9. Inverting Gain of –2 with Impedance Matching.
In the inverting configuration, two key design considerations
must be noted. The first is that the gain resistor (R
G
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long
PC board trace, or other transmission line conductor), it is
normally necessary to add an additional matching resistor to
ground. R
by itself is normally not set to the required input
G
impedance since its value, along with the desired gain, will
determine an R
which may be non-optimal from a frequency
F
response standpoint. The total input impedance for the
source becomes the parallel combination of R
and RM.
G
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and will have slight effect on
the bandwidth through Equation 1. The values shown in
Figure 9 have accounted for this by slightly decreasing R
(from Figure 1) to re-optimize the bandwidth for the noise
gain of Figure 9 (NG = 2.73) In the example of Figure 9, the
R
value combines in parallel with the external 50Ω source
M
impedance, yielding an effective driving impedance of
50Ω || 68Ω = 28.8Ω. This impedance is added in series with
R
for calculating the noise gain—which gives NG = 2.73.
G
This value, along with the R
of Figure 9 and the inverting
F
input impedance of 35Ω, are inserted into Equation 3 to get
a feedback transimpedance nearly equal to the 472Ω opti-
mum value.
Note that the noninverting input in this bipolar supply inverting application is connected directly to ground. It is often
suggested that an additional resistor be connected to ground
)
F
16
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OPA691
SBOS226A
on the noninverting input to achieve bias current error cancellation at the output. The input bias currents for a current
feedback op amp are not generally matched in either magnitude or polarity. Connecting a resistor to ground on the
noninverting input of the OPA691 in the circuit of Figure 9 will
actually provide additional gain for that input’s bias and noise
currents, but will not decrease the output DC error since the
input bias currents are not matched.
OUTPUT CURRENT AND VOLTAGE
The OPA691 provides output voltage and current capabilities
that are unsurpassed in a low-cost monolithic op amp. Under
no-load conditions at 25°C, the output voltage typically swings
closer than 1V to either supply rail; the +25°C swing limit is
within 1.2V of either rail. Into a 15Ω load (the minimum tested
load), it is tested to deliver more than ±160mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA691’s output drive capabilities,
noting that the graph is bounded by a “Safe Operating Area”
of 1W maximum internal power dissipation. Superimposing
resistor load lines onto the plot shows that the OPA691 can
drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the
output capabilities or the 1W dissipation limit. A 100Ω load
line (the standard test circuit load) shows the full ±3.9V
output swing capability, as shown in the Typical Specifications.
The minimum specified output voltage and current overtemperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, decreasing their V
’s (increasing the available output voltage
BE
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the available output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA691. The circuit acts to limit the maximum
source or sink current to approximately 250mA.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA691 can be very susceptible to decreased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended R
ver-
S
sus Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA691. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA691 output pin
(see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA691 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels,
the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2ndharmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network—in the noninverting configuration (see Figure 1) this
is the sum of R
is just R
F
capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than
the expected 2x rate while the 3rd-harmonic increases at a
little less than the expected 3x rate. Where the test power
doubles, the 2nd-harmonic increases by less than the expected 6dB while the 3rd-harmonic increases by less than
the expected 12dB. This also shows up in the 2-tone,
3rd-order intermodulation spurious (IM3) response curves.
The 3rd-order spurious levels are extremely low at low output
power levels. The output stage continues to hold them low
even as the fundamental power reaches very high levels. As
the Typical Characteristics show, the spurious intermodulation
powers do not increase as predicted by a traditional intercept
model. As the fundamental power level increases, the
+ RG, while in the inverting configuration it
F
. Also, providing an additional supply decoupling
OPA691
SBOS226A
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17
dynamic range does not decrease significantly. For two
tones centered at 20MHz, with 10dBm/tone into a matched
50Ω load (i.e., 2Vp-p for each tone at the load, which requires
8Vp-p for the overall 2-tone envelope at the output pin), the
Typical Characteristics show 48dBc difference between the
test-tone power and the 3rd-order intermodulation spurious
levels. This exceptional performance improves further when
operating at lower frequencies.
NOISE PERFORMANCE
Wideband current feedback op amps generally have a higher
output noise than comparable voltage feedback op amps. The
OPA691 offers an excellent balance between voltage and
current noise terms to achieve low output noise. The inverting
current noise (15pA/
solutions while the input voltage noise (1.7nV/
than most unity-gain stable, wideband, voltage feedback op
amps. This low input voltage noise was achieved at the price
of higher noninverting input current noise (12pA/
as the AC source impedance looking out of the noninverting
node is less than 100Ω, this current noise will not contribute
significantly to the total output noise. The op amp input voltage
noise and the two input current noise terms combine to give
low output noise under a wide variety of operating conditions.
Figure 10 shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/
or pA/
√Hz
.
R
S
E
RS
√4kTR
S
4kT
R
G
FIGURE 10. Op Amp Noise Analysis Model.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 5 shows the general form for the
output noise voltage using the terms shown in Figure 10.
2
E E I R kTR NG I R kTR NG
=+
O
NI BN
√Hz
) is significantly lower than earlier
E
NI
I
BN
(
)
SS
OPA691
R
G
2
+
44
I
BI
R
F
√4kTR
4kT = 1.6E –20J
at 290°K
2
+
(
BI F F
√Hz
√Hz
F
2
)
+
) is lower
). As long
√Hz
E
O
(5)
Dividing this expression by the noise gain (NG = (1 + R
F/RG
will give the equivalent input-referred spot noise voltage at
the noninverting input, as shown in Equation 6.
(6)
E E I R kTR
NNIBN
2
=+
(
2
++
4
)
SS
IR
BI F F
NG
kTR
4
+
NG
2
Evaluating these two equations for the OPA691 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 8.0nV/
noise voltage of 4.0nV/
noise voltage is higher than the 1.7nV/
√Hz
and a total equivalent input spot
√Hz
. This total input-referred spot
√Hz
specification for
the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. If the feedback resistor is reduced in high
gain configurations (as suggested previously), the total inputreferred voltage noise given by Equation 5 will approach just
the 1.7nV/
gain of +10 using R
noise of 2.1nV/
√Hz
of the op amp itself. For example, going to a
= 180Ω will give a total input-referred
F
√Hz
.
DC ACCURACY AND OFFSET CONTROL
A current feedback op amp like the OPA691 provides exceptional bandwidth in high gains, giving fast pulse settling but
only moderate DC accuracy. The Typical Specifications show
an input offset voltage comparable to high-speed voltage
feedback amplifiers. However, the two input bias currents are
somewhat higher and are unmatched. Whereas bias current
cancellation techniques are very effective with most voltage
feedback op amps, they do not generally reduce the output DC
offset for wideband current feedback op amps. Since the two
input bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out of each
input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case
+25°C input offset voltage and the two input bias currents,
gives a worst-case output offset range equal to:
± (NG • V
where NG = noninverting signal gain
= ± (2 • 2.5mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA)
= ±5mV + 1.75mV ± 10.05mV
= –13.3mV → +16.8mV
A fine-scale, output offset null, or DC operating point adjust-
ment, is sometimes required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most simple adjustment techniques do not correct for
temperature drift. It is possible to combine a lower speed,
precision op amp with the OPA691 to get the DC accuracy
of the precision op amp along with the signal bandwidth of
the OPA691. See Figure 11 for a noninverting G = +10 circuit
that holds an output offset voltage less than ±7.5mV overtemperature with > 150MHz signal bandwidth.
This DC-coupled circuit provides very high signal bandwidth
using the OPA691. At lower frequencies, the output voltage
is attenuated by the signal gain and compared to the original
) + (IBN • RS/2 • NG) ± (IBI • RF)
OS(MAX)
))
18
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OPA691
SBOS226A
input voltage at the inputs of the OPA237 (this is a low-cost,
precision voltage feedback op amp with 1.5MHz gain bandwidth product). If these two don’t agree (due to DC offsets
introduced by the OPA691), the OPA237 sums in a correction current through the 2.86kΩ inverting summing path.
Several design considerations will allow this circuit to be
optimized. First, the feedback to the OPA237’s noninverting
input must be precisely matched to the high-speed signal
gain. Making the 2kΩ resistor to ground an adjustable resistor would allow the low and high frequency gains to
be precisely matched. Secondly, the crossover frequency
region where the OPA237 passes control to the OPA691
must occur with exceptional phase linearity. These two
issues reduce to designing for pole/zero cancellation in the
overall transfer function. Using the 2.86kΩ resistor will nominally satisfy this requirement for the circuit in Figure 11.
Perfect cancellation over process and temperature is not
possible. This initial resistor setting and precise gain matching, however, will minimize long-term pulse settling tails.
+5V
Power supply
V
I
de-coupling not shown
+5V
1.8kΩ
2.86kΩ
OPA237
–5V
2kΩ
OPA691
–5V
20Ω
180Ω
18kΩ
DIS
V
O
FIGURE 11. Wideband, DC Connected Composite Circuit.
DISABLE OPERATION
The OPA691 provides an optional disable feature that may
be used to reduce system power. If the
unconnected, the OPA691 will operate normally. To disable,
the control pin must be asserted LOW. Figure 12 shows a
simplified internal circuit for the disable control feature.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the 15kΩ
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1’s emitter. As V
additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 75µA). At this point, any
further current pulled out of V
DIS
holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the disable mode are only
those required to operate the circuit of Figure 12. Additional
circuitry ensures that turn-on time occurs faster than turn-off
time (make-before-break).
DIS
control pin is left
is pulled LOW,
DIS
goes through those diodes
+V
S
15kΩ
Q1
25kΩ 110kΩ
I
V
DIS
S
Control
–V
S
FIGURE 12. Simplified Disable Control Circuit.
When disabled, the output and input nodes go to a high
impedance state. If the OPA691 is operating in a gain of +1,
this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R
+ RG) will appear as the impedance looking back into the
F
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R
+ RG) giving relatively poor input-to-
F
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 13
shows these glitches for the circuit of Figure 1 with the input
signal set to 0V. The glitch waveform at the output pin is
plotted along with the
The transition edge rate (dV/dT) of the
DIS
pin voltage.
DIS
control line will
influence this glitch. For the plot of Figure 12, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the V
DIS
pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2kΩ series resistor between the logic gate
and the
using just the parasitic input capacitance on the
DIS
input pin will provide adequate bandlimiting
DIS
pin
while still ensuring an adequate logic level swing.
6.0
4.0
(2V/div)
2.0
0
DIS
V
30
20
10
0
–10
Output Voltage (10mV/div)
–20
–30
V
DIS
Output Voltage
(0V Input)
Time (20ns/div)
FIGURE 13. Disable/Enable Glitch.
OPA691
SBOS226A
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19
THERMAL ANALYSIS
Due to the high output power capability of the OPA691,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation, as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T
The total internal power dissipation (P
quiescent power (P
output stage (P
) and additional power dissipated in the
DQ
) to deliver load power. Quiescent power is
DL
) is given by TA + PD •
J
) is the sum of
D
θ
JA
simply the specified no-load supply current times the total
supply voltage across the part. P
will depend on the
DL
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
DL
2
= V
/(4 • RL) where R
S
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
using an
J
OPA691IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 20Ω load to +2.5V DC:
P
= 10V • 5.7mA + 52/(4 • (20Ω || 804Ω)) = 377mΩ
D
Maximum T
= +85°C + (0.377W • (150°C/W) = 141.5°C
J
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower junction temperatures. Remember, this is a
worst-case internal power dissipation—use your actual signal and load to computer P
. The highest possible internal
DL
dissipation will occur if the load requires current to be forced
into the output for positive output voltages or sourced from
the output for negative output voltages. This puts a high
current through a large internal voltage drop in the output
transistors. The “Output Voltage and Current Limitations” plot
shown in the Typical Characteristics includes a boundary for
1W maximum internal power dissipation under these conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA691 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling capaci-
.
tor across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These
may be placed somewhat farther from the device and may be
shared among several devices in the same area of the PC
board.
c) Careful selection and placement of external components will preserve the high-frequency performance of
L
the OPA691. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal-film and carbon composition, axially-leaded
resistors can also provide good high-frequency performance.
Again, keep their leads and PC board trace length as short
as possible. Never use wirewound type resistors in a highfrequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resistors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of
the board between the output and inverting input pins. The
frequency response is primarily determined by the feedback
resistor value as described previously. Increasing its value
will reduce the bandwidth, while decreasing it will give a more
peaked frequency response. The 402Ω feedback resistor
used in the Electrical Characteristic tables at a gain of +2 on
±5V supplies is a good starting point for design. Note that a
453Ω feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current
feedback op amp requires a feedback resistor even in the
unity-gain follower configuration to control stability.
d) Connections to other wideband devices on the board
may be made with short, direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
plot of recommended R
versus Capacitive Load. Low para-
S
sitic capacitive loads (< 5pF) may not need an R
OPA691 is nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB signal
loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an ECL
from the
S
since the
S
20
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OPA691
SBOS226A
design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on
board, and in fact, a higher impedance environment will
improve distortion, as shown in the Distortion versus Load
plots. With a characteristic board trace impedance defined
based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA691
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device:
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capability of the OPA691 allows multiple destination devices to be
handled as separate transmission lines, each with their own
series and shunt terminations. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only. Treat
the trace as a capacitive load in this case and set the series
resistor value as shown in the plot of R
versus Capacitive
S
Load. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due
to the voltage divider formed by the series output into the
terminating impedance.
e) Socketing a high-speed part like the OPA691 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA691
onto the board.
INPUT AND ESD PROTECTION
The OPA691 is built using a very high speed complementary
bipolar process. The internal junction breakdown voltages
are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table. All device pins have limited ESD protection
using internal diodes to the power supplies, as shown in
Figure 14.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply parts
driving into the OPA691), current-limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
+V
CC
External
Pin
–V
CC
FIGURE 14. Internal ESD Protection.
Internal
Circuitry
OPA691
SBOS226A
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21
PACKAGE DRAWINGS
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8 5
1 4
A
0.069 (1,75) MAX
0.020 (0,51)
0.014 (0,35)
0.157 (4,00)
0.150 (3,81)
0.010 (0,25)
0.004 (0,10)
0.244 (6,20)
0.228 (5,80)
0.010 (0,25)0.050 (1,27)
0.008 (0,20) NOM
Gage Plane
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
8
0.197
(5,00)
0.189
(4,80)
14
0.344
(8,75)
0.337
(8,55)
16
0.394
(10,00)
0.386
(9,80)
4040047/E 09/01
22
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OPA691
SBOS226A
PACKAGE DRAWINGS (Cont.)
DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE
0,95
1,45
0,95
3,00
2,80
46
31
0,05 MIN
6X
0,50
0,25
1,70
1,50
0,20
3,00
2,60
Seating Plane
M
0,15 NOM
Gage Plane
0,25
0 –8
0,10
0,55
0,35
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
4073253-5/G 01/02
OPA691
SBOS226A
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23
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
OPA691ID ACTIVE SOIC D 8 100 None CU SNPB Level-3-235C-168 HR
OPA691IDBVR ACTIVE SOT-23 DBV 6 3000 None CU NIPDAU Level-3-220C-168 HR
OPA691IDBVT ACTIVE SOT-23 DBV 6 250 None CU NIPDAU Level-3-220C-168 HR
OPA691IDR ACTIVE SOIC D 8 2500 None CU SNPB Level-3-235C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(2)
Lead/Ball Finish MSL Peak Temp
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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