Texas Instruments MSP430P112IDW, MSP430C112IDW, MSP-EVK430A110, MSP430C111IDW, MSP-EVK430X110 Datasheet

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MSP430x11x

MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low Supply Voltage Range 2.5 V – 5.5 V

Ultra Low-Power Consumption

Low Operation Current, 330 µA at 1 MHz,3 V

Two Power Saving Modes: – Standby Mode: 1.5 µA – RAM Retention Off Mode: 0.1 µA

Wake-up From Standby Mode in 6 µs Maximum

16-Bit RISC Architecture, 200 ns Instruction Cycle Time

Basic Clock Module Configurations: – Various Internal Resistors – Single External Resistor – 32 kHz Crystal – High Frequency Crystal – Resonator – External Clock Source

Single Slope A/D Converter With External Components

16-Bit Timer With 3 Capture/Compare Registers

Serial Onboard Programming

Program Code Protection by Security Fuse

Family Members Include: MSP430C111: 2k Byte ROM,128 Byte RAM MSP430C112: 4k Byte ROM, 256 Byte RAM MSP430P1 12: 4k Byte OTP, 256 Byte RAM

EPROM Version Available for Prototyping: – PMS430E112: 4k Byte EPROM, 256 Byte

RAM

Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package, 20-Pin Ceramic Dual-In-Line (CDIP) Package (EPROM Only)

description

The T exas Instruments MSP430 series is an ultra low-power microcontroller family consisting of several devices featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16 bit integrated registers on the CPU, and the constant generator, the MSP430 achieves maximum code efficiency. The digitallycontrolled oscillator provides fast wake-up from all low-power modes to active mode in less than 6 ms.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The MSP430x1 1x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

TEST/VPP

VCC

P2.5/R

OSC

VSS

Xout/TCLK

Xin

RST

/NMI

P2.0/ACLK

P2.1/INCLK

P2.2/TA0

P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1

DW PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

MSP430x11x MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

SOWB 20-Pin

(DW)

CDIP

20-Pin

(JL)

MSP430C111IDW

–

40°C to 85°C

MSP430C112IDW

MSP430P112IDW

25°C

—

PMS430E112JL

functional block diagram

Oscillator

System Clock

ACLK SMCLK

2/4 kB ROM

4 kB OTP

’C’: ROM

128/256B

RAM

Power-on-

Reset

I/O Port

8 I/O’s, All With

Interrupt

CPU

Incl. 16 Reg.

Test

JTAG

Bus

Conv.

MAB, 16 Bit

MDB, 16 Bit

MAB, 4 Bit

MDB, 8 Bit

MCB

XIN XOut

RST/NMI P1.0–7

DCOR ACLK

P2.0–5

Rosc

TEST/VPP

’P’: OTP

Outx

Timer_A

3 CC Register

CCR0/1/2

Watchdog

Timer

15/16 Bit

MCLK

’E’: EPROM

x = 0, 1, 2

ACLK

SMCLK

Outx CCIxA

CCIxB

TACLK or INCLK

INCLK

Out0

CCI0B CCI1B

JTAG

CCIxA

TACLK

SMCLK

I/O Port 2

6 I/O’s All With

Capabililty

Interrupt

Capabililty

MSP430x11x

MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal T ACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0A input, Compare: Out0 output P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1A input, Compare: Out1 output P1.3/TA2 16 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI2A input, Compare: Out2 output P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/T est clock, input terminal for device programming

and test

P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, Compare: Out0 output/test mode select, input terminal for

device programming and test. P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/Timer_A, Compare: Out1 output/test data input terminal. P1.7/TA2/TDO/TDI 20 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output/test data output terminal or data input

during programming. P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/TA0 10 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0B input, Compare: Out0 output P2.3/TA1 11 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1B input, Compare: Out1 output P2.4/TA2 12 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output P2.5/R

OSC

3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency RST/NMI 7 I Reset or nonmaskable interrupt input TEST/VPP 1 I Select of test mode for JTAG pins on Port1/programming voltage input during EPROM programming VCC 2 Supply voltage VSS 4 Ground reference Xin 6 I Input terminal of crystal oscillator Xout/TCLK 5 I/O Output terminal of crystal oscillator or test clock input

detailed description

processing unit

The processing unit is based on a consistent, and orthogonally designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development and distinguished by ease of programming. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operations.

MSP430x11x MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

CPU

All sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor.

Four registers are reserved for special use as a program counter, a stack pointer , a status register, and a constant generator. The remaining twelve registers are available as general-purpose registers.

Peripherals are connected to the CPU using a data address and control buses and can be handled easily with all instructions for memory manipulation.

instruction set

The instructions set for this register-register architecture provides a powerful and easy-to-use assembly language. The instruction set consists of 51 instructions with three formats and seven addressing modes. T able 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 → R5 Single operands, destination only e.g. CALL R8 PC → (TOS), R8 → PC

Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0

Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B. Examples: Instructions for word operation Instructions for byte operation

MOV EDE,TONI MOV.B EDE,TONI ADD #235h,&MEM ADD.B #35h,&MEM PUSH R5 PUSH.B R5 SWPB R5 —

Table 2. Address Mode Descriptions

ADDRESS MODE s d SYNTAX EXAMPLE OPERATION

Register √ √ MOV Rs, Rd MOV R10, R11 R10 → R11 Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2 + R5) → M(6 + R6) Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) → M(TONI) Absolute √ √ MOV &MEM, &TCDAT M(MEM) → M(TCDAT) Indirect √ MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab + R6) Indirect autoincrement √ MOV @Rn+, RM MOV @R10+, R11 M(R10) →R11, R10 + 2 → R10 Immediate √ MOV #X, TONI MOV #45, TONI #45 → M(TONI)

NOTE: s = source d = destination Rs/Rd = source register/destination register Rn = register number

Program Counter

General-Purpose Register

PC/R0

Stack Pointer

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

General-Purpose Register

General-Purpose Register R14

General-Purpose Register

R15

MSP430x11x

MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

instruction set (continued)

Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide

indirect

addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control.

operation modes and interrupts

The MSP430 operating modes support various advanced requirements for ultra low-power and ultra low-energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The advanced requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the

RETI

instruction to the mode that was selected before the interrupt event. The different requirements of the CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use of different clock signals (see Figure 1):

Auxiliary clock ACLK (from LFXTCLK/crystal’s frequency), used by the peripheral modules

Main system clock MCLK, used by the CPU and system

Subsystem clock SMCLK, used by the peripheral modules.

DIVA

XIN

High Frequency XT Oscillator, XTS=1

ACLK

OSCOff XTS

Low Power LF Oscillator, XTS = 0

/1, /2, /4, /8

DIVM

/1, /2, /4, /8, Off

SELM CPUOff

Auxiliary Clock

MCLK

Main System Clock

DIVS

/1, /2, /4, /8, Off

SELS SCG1

SMCLK

Sub-System Clock

XOUT

SMCLKGEN

LFXTCLK

MCLKGEN

ACLKGEN

DCOMOD

DCOCLK

Digital Controlled Oscillator (DCO)

Modulator (MOD)

Generator

DCO MODR

sel

SCG0

DCOR

The DCO-Generator is connected to pin P2.5/R

OSC

if DCOR control bit is set.

The port pin P2.5/R

OSC

is selected if DCOR control bit is reset (initial state).

P2.5

P2.5/R

OSC

Figure 1. Clock Signals

MSP430x11x MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operation modes and interrupts (continued)

Two clock sources, LFXTCLK and DCOCLK, can be used to drive the MSP430 system. The LFXTCLK is defined by connecting a low power, low frequency crystal to the oscillator , by connecting a high frequency crystal to the oscillator, or by applying an external clock source. The high frequency crystal oscillator is used if the control bit XTS is set. The crystal oscillator may be switched off when the LFXTCLK oscillator is not needed for the present operation mode. The DCOCLK is active and the frequency is selected or adjusted by the software. The DCOCLK is inactive or stopped when it is not used by the CPU or peripheral modules. The dc-generator can be stopped when SCG0 is reset and DCOCLK is not needed. The dc-generator defines the basic DCO frequency and can be defined by one external resistor or it is adjusted in eight steps with the integrated resistors.

NOTE:

The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to ensure proper start of program execution. The software then defines the final system clock, via control bit manipulation.

low-power consumption capabilities

The various operating modes are controlled by the software through controlling the operation of the internal clock system. This clock system provides many combinations of hardware and software capabilities to run the application with the lowest power consumption and with optimized system costs:

Use the internal clock (DCO) generator without any external components.

Select an external crystal or ceramic resonator for lowest frequency or cost.

Select and activate the proper clock signals (LFXTCLK and/or DCOCLK) and clock pre-divider function.

Apply an external clock source.

Four of the control bits that influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR. The four bits that control the CPU and the system clock generator are SCG1, SCG0, OscOff, and CPUOff:

status register R2

Reserved For Future

Enhancements

15 9 8 7 0

V SCG1 SCG0 OscOff

CPUOff GIE N Z C

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

6543 21

The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the data on the stack. That allows the program to resume execution in another power operating mode after the return from interrupt (RETI).

SCG1: The clock signal SMCLK, used for peripherals, is enabled when the bit is reset or disabled if the

bit is set.

SCG0: The dc-generator is active when it is reset. The DCO can be deactivated only if the SCG0 bit is

set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed by the

dc-generator defines the basic frequency of the DCOCLK. It is a dc current.

NOTE:

When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly . The delay is in the µs-range. See device parameters for the specified values.

MSP430x11x

MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

status register R2 (continued)

OscOff: The LFXT crystal oscillator is active when the OscOff bit is reset. The LFXT oscillator can only be

deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to start a crystal oscillation needs consideration when the oscillator off option is used. Mask programmable (ROM) devices can disable this feature so that the oscillator can never be switched

off by software. CPUOff: The clock signal MCLK, used for the CPU, is active when the bit is reset or stopped if it is set. DCOCLK: The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit

is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:

1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).

2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the ROM with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up, external reset, watchdog

WDTIFG (see Note1)

Reset 0FFFEh 15, highest

NMI, oscillator fault

NMIIFG, OFIFG (see Note 1)

(non)-maskable,

(non)-maskable

0FFFCh 14 0FFFAh 13

0FFF8h 12

0FFF6h 11 Watchdog Timer WDTIFG maskable 0FFF4h 10 Timer_A CCIFG0 (see Note 2) maskable 0FFF2h 9

Timer_A

CCIFG1, CCIFG2, TAIFG

(see Notes 1 and 2)

maskable 0FFF0h 8

0FFEEh 7

0FFECh 6

0FFEAh 5

0FFE8h 4 I/O Port P2 (eight flags – see Note 3)

P2IFG.0 to P2IFG.7 (see Notes 1 and 2)

maskable 0FFE6h 3

I/O Port P1 (eight flags)

P1IFG.0 to P1IFG.7 (see Notes 1 and 2)

maskable 0FFE4h 2

0FFE2h 1

0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module

3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0–5) are implemented on the 11x devices.

MSP430x11x MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1

7654 0

OFIE WDTIE

321

rw-0 rw-0 rw-0

Address 0h

NMIIE

WDTIE: Watchdog Timer enable signal OFIE: Oscillator fault enable signal NMIIE: Non-maskable interrupt enable signal

interrupt flag register 1

7654 0

OFIFG WDTIFG

321

rw-0 rw-1 rw-0

Address 02h NMIIFG

WDTIFG: Set on overflow or security key violation

OR Reset on V

power-on or reset condition at RST/NMI-pin OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI-pin

Legend rw:

rw-0:

Bit can be read and written. Bit can be read and written. It is reset by PUC SFR bit is not present in device.

MSP430x11x

MIXED SIGNAL MICROCONTROLLERS

SLAS196B– DECEMBER 1998 – REVISED APRIL 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

memory organization

Int. Vector

2 kB ROM

128B RAM

16b Per.

8b Per.

SFR

FFFFh FFE0h

FFDFh

F800h

027Fh 0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430C111

Int. Vector

4 kB

EPROM

256B RAM

16b Per.

8b Per.

SFR

FFFFh FFE0h

FFDFh

02FFh

0200h

01FFh

0100h 00FFh 0010h 000Fh

0000h

MSP430P112 PMS430E112

Int. Vector

4 kB ROM

256B RAM

16b Per.

8b Per.

SFR

FFFFh FFE0h

FFDFh

F000h

02FFh

0200h 01FFh 0100h

00FFh 0010h 000Fh 0000h

MSP430C112

F000h

peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled easily with instructions for memory manipulation.

digital I/O

There are two eight-bit I/O ports, Port P1 and Port P2 – implemented (1 1x parts only have six Port P2 I/O signals available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of digital input/output to the application:

• All individual I/O bits are programmable independently.

• Any combination of input, output, and interrupt conditions is possible.

• Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of

Port P2.

• Provides read/write access to all registers with all instructions.

The seven registers are:

• Input register 8 bits at Port P1/P2 contains information at the pins

• Output register 8 bits at Port P1/P2 contains output information

• Direction register 8 bits at Port P1/P2 controls direction

• Interrupt edge select 8 bits at Port P1/P2 input signal change necessary for interrupt

• Interrupt flags 8 bits at Port P1/P2 indicates if interrupt(s) are pending

• Interrupt enable 8 bits at Port P1/P2 contains interrupt enable bits

• Selection (Port or Mod.) 8 bits at Port P1/P2 determines if pin(s) have port or module function

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