Texas Instruments MSP430G2231 User Manual

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MSP430G2231 Automotive Mixed-Signal Microcontroller

1 Features 2 Applications

• Qualified for Automotive Applications

• Low Supply-Voltage Range: 1.8 V to 3.6 V

• Ultra-Low-Power Consumption – Active Mode: 220 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA

• Five Power-Saving Modes

• Ultra-Fast Wakeup From Standby Mode in Less Than 1 µs

• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time

• Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With One

Calibrated Frequency

– Internal Very Low Power Low-Frequency (LF)

Oscillator – 32-kHz Crystal – External Digital Clock Source

• 16-Bit Timer_A With Two Capture/Compare Registers

• Universal Serial Interface (USI) Supports SPI and I2C

• Brownout Detector

• 10-Bit 200-ksps Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold, and Autoscan

• Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse

• On-Chip Emulation Logic With Spy-Bi-Wire Interface

• For Family Members Details, See Device

Characteristics

• Available Packages – 14-Pin Plastic Small-Outline Thin Package

(TSSOP) (PW)

– 16-Pin QFN Package (RSA)

• For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144) document, or see the TI web site at www.ti.com.

• Low-Cost Sensor Systems

3 Description

The Texas Instruments MSP430™ family of ultra-lowpower microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430G2231 devices are ultra-low-power mixed signal microcontrollers with a built-in 16-bit timer and ten I/O pins. The MSP430G2231 devices have a 10-bit A/D converter and built-in communication capability using synchronous protocols (SPI or I2C). For configuration details, see

Table 1.

Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.

Device Information

ORDER NUMBER BODY SIZE

MSP430G2231IRSARQ1 RSA (16) 4 mm x 4 mm MSP430G2231IPW4RQ1 PW (14) 5 mm x 4.4 mm

(1) For the most current part, package, and ordering information,

see the Package Option Addendum at the end of this

PACKAGE (PIN)

MSP430G2231-Q1

(1)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Clock

System

Brownout

Protection

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15-Bit

Timer0_A2

2 CC

Registers

16-MHz

CPU

incl. 16

Registers

Emulation

2BP

JTAG

Interface

SMCLK

ACLK

MDB

MAB

Port P1

8 I/O

Interrupt

capability

pullup/down

resistors

P1.x

Spy-Bi-

Wire

XIN

XOUT

RAM

128B

Flash

2KB

ADC

10-Bit

8 Ch.

Autoscan

1 ch DMA

P2.x

Port P2

2 I/O

Interrupt

capability

pullup/down

resistors

USI

Universal

Serial Interface SPI, I2C

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4 Functional Block Diagram

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Figure 1. Functional Block Diagram

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Table of Contents

1 Features ................................................................. 1

2 Applications .......................................................... 1

3 Description ............................................................ 1

4 Functional Block Diagram ................................... 2

5 Revision History ................................................... 4

6 Device Characteristics ......................................... 4

7 Terminal Configuration and Functions ............... 5

7.1 14-Pin PW Package (Top View) .............................. 5

7.2 16-Pin RSA Package (Top View) ............................. 5

7.3 Terminal Functions .................................................. 6

8 Detailed Description ............................................. 7

8.1 CPU .......................................................................... 7

8.2 Instruction Set .......................................................... 7

8.3 Operating Modes ..................................................... 8

8.4 Interrupt Vector Addresses ...................................... 9

8.5 Special Function Registers (SFRs) ........................ 10

8.6 Memory Organization ............................................. 11

8.7 Flash Memory ........................................................ 11

8.8 Peripherals ............................................................. 12

9 Specifications ...................................................... 16

9.1 Absolute Maximum Ratings ................................... 16

9.2 Recommended Operating Conditions .................... 16

9.3 Active Mode Supply Current Into VCCExcluding

External Current ...................................................... 17

9.4 Typical Characteristics – Active Mode Supply Current

(Into VCC) ................................................................ 17

9.5 Low-Power Mode Supply Currents (Into VCC)

Excluding External Current ..................................... 18

9.6 Typical Characteristics, Low-Power Mode Supply

Currents .................................................................. 18

9.7 Schmitt-Trigger Inputs – Ports Px .......................... 19

9.8 Leakage Current – Ports Px .................................. 19

9.9 Outputs – Ports Px ................................................. 19

9.10 Output Frequency – Ports Px .............................. 19

9.11 Typical Characteristics – Outputs ........................ 20

9.12 POR, BOR ........................................................... 21

9.13 Main DCO Characteristics ................................... 23

9.14 DCO Frequency ................................................... 23

9.15 Calibrated DCO Frequencies – Tolerance ........... 24

9.16 Wakeup From Lower-Power Modes (LPM3,

LPM4) – Electrical Characteristics .......................... 24 11.6 Glossary ............................................................... 44

9.17 Typical Characteristics – DCO Clock Wakeup Time

From LPM3, LPM4 .................................................. 24

9.18 Crystal Oscillator, Xt1, Low-Frequency Mode ..... 25

9.19 Internal Very-Low-Power Low-Frequency Oscillator

(VLO) ...................................................................... 25

9.20 Timer_A ................................................................ 25

9.21 USI, Universal Serial Interface ............................. 26

9.22 Typical Characteristics – USI Low-Level Output

Voltage On SDA and SCL ...................................... 26

9.23 10-Bit ADC, Power Supply and Input Range

Conditions ............................................................... 27

9.24 10-Bit ADC, Built-In Voltage Reference ............... 28

9.25 10-Bit ADC, External Reference .......................... 29

9.26 10-Bit ADC, Timing Parameters ........................... 29

9.27 10-Bit ADC, Linearity Parameters ........................ 29

9.28 10-Bit ADC, Temperature Sensor and Built-In V

................................................................................. 30

9.29 Flash Memory ...................................................... 30

9.30 RAM ..................................................................... 31

9.31 JTAG and Spy-Bi-Wire Interface .......................... 31

9.32 JTAG Fuse ........................................................... 31

MID

10 I/O Port Schematics ........................................... 32

10.1 Port P1 Pin Schematic: P1.0 To P1.2, Input/Output

With Schmitt Trigger ............................................... 32

10.2 Port P1 Pin Schematic: P1.3, Input/Output With

Schmitt Trigger ........................................................ 34

10.3 Port P1 Pin Schematic: P1.4, Input/Output With

Schmitt Trigger ........................................................ 35

10.4 Port P1 Pin Schematic: P1.5, Input/Output With

Schmitt Trigger ........................................................ 36

10.5 Port P1 Pin Schematic: P1.6, Input/Output With

Schmitt Trigger ........................................................ 37

10.6 Port P1 Pin Schematic: P1.7, Input/Output With

Schmitt Trigger ........................................................ 38

10.7 Port P2 Pin Schematic: P2.6, Input/Output With

Schmitt Trigger ........................................................ 39

10.8 Port P2 Pin Schematic: P2.7, Input/Output With

Schmitt Trigger ........................................................ 40

11 Device and Documentation Support ................ 41

11.1 Device Support .................................................... 41

11.2 Documentation Support ....................................... 43

11.3 Community Resources ......................................... 43

11.4 Trademarks .......................................................... 44

11.5 Electrostatic Discharge Caution ........................... 44

12 Mechanical, Packaging, and Orderable

Information .......................................................... 44

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5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

REVISION DESCRIPTION

SLAS787 Product Preview release

SLAS787A Production Data release

Formatting and document organization changes throughout.

SLAS787B

Removed all information related to operation at 105°C. Removed all device variants except for MSP430G2231. Added Device and Documentation Support and Mechanical, Packaging, and Orderable Information.

6 Device Characteristics

Table 1 shows the features of the MSP430G2231 device.

Table 1. Family Members

Device BSL EEM Timer_A USI Clock I/O

MSP430G2231 - 1 2 128 1x TA2 1 8 LF, DCO, VLO 10

Flash RAM ADC10 Package

(KB) (B) Channel Type

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16-QFN

14-TSSOP

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P1.5/TA0.0/SCLK/A5/TMS

P1.6/TA0.1/SDO/SCL/TDI/TCLK

P1.7/SDI/SDA/TDO/TDI

RST/NMI/SBWTDIO

TEST/SBWTCK

XOUT/P2.7

XIN/P2.6/TA0.1

DVSS

DVCC

P1.0/TA0CL K/ACL K/A0

P1.1/TA0.0/A1

P1.2/TA0.1/A2

DVCC

P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK

P1.7/A7/SDI/SDA/TDO/TDI

RST/NMI/SBWTDIO

TEST/SBW TCK

XOUT/P2.7

XIN/P2.6/TA0.1

DVSS

P1.0/TA0CLK/ACLK/A0

P1.1/TA0.0/A1

P1.2/TA0.1/A2

P1.3/ADC10CLK/A3/VREF-/VEREF-

P1.5/TA0.0/A5/SCLK/TMS

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7 Terminal Configuration and Functions

7.1 14-Pin PW Package (Top View)

NOTE: See port schematics in I/O Port Schematics for detailed I/O information.

7.2 16-Pin RSA Package (Top View)

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NOTE: See port schematics in I/O Port Schematics for detailed I/O information.

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7.3 Terminal Functions

Table 2. Terminal Functions

TERMINAL

NAME

P1.0/ General-purpose digital I/O pin TA0CLK/ Timer0_A, clock signal TACLK input ACLK/ ACLK signal output A0 ADC10 analog input A0

P1.1/ General-purpose digital I/O pin TA0.0/ 3 2 I/O Timer0_A, capture: CCI0A input, compare: Out0 output A1 ADC10 analog input A1

P1.2/ General-purpose digital I/O pin TA0.1/ 4 3 I/O Timer0_A, capture: CCI1A input, compare: Out1 output A2 ADC10 analog input A2

P1.3/ General-purpose digital I/O pin ADC10CLK/ ADC10, conversion clock output A3/ ADC10 analog input A3 VREF-/VEREF ADC10 negative reference voltage

P1.4/ General-purpose digital I/O pin SMCLK/ SMCLK signal output A4/ 6 5 I/O ADC10 analog input A4 VREF+/VEREF+/ ADC10 positive reference voltage TCK JTAG test clock, input terminal for device programming and test

P1.5/ General-purpose digital I/O pin TA0.0/ Timer0_A, compare: Out0 output A5/ 7 6 I/O ADC10 analog input A5 SCLK/ USI: clock input in I2C mode; clock input/output in SPI mode TMS JTAG test mode select, input terminal for device programming and test

P1.6/ General-purpose digital I/O pin TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output A6/ ADC10 analog input A6 SDO/ USI: Data output in SPI mode SCL/ USI: I2C clock in I2C mode TDI/TCLK JTAG test data input or test clock input during programming and test

P1.7/ General-purpose digital I/O pin A7/ ADC10 analog input A7 SDI/ 9 8 I/O USI: Data input in SPI mode SDA/ USI: I2C data in I2C mode TDO/TDI

XIN/ Input terminal of crystal oscillator P2.6/ 13 12 I/O General-purpose digital I/O pin TA0.1 Timer0_A, compare: Out1 output

XOUT/ Output terminal of crystal oscillator P2.7 General-purpose digital I/O pin

RST/ Reset NMI/ 10 9 I Nonmaskable interrupt input SBWTDIO Spy-Bi-Wire test data input/output during programming and test

TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. SBWTCK Spy-Bi-Wire test clock input during programming and test

DVCC 1 15, 16 NA Supply voltage DVSS 14 13, 14 NA Ground reference QFN Pad - Pad NA QFN package pad connection to VSSrecommended.

(1) TDO or TDI is selected via JTAG instruction. (2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

(1)

this pad after reset.

NO. I/O DESCRIPTION

PW RSA

2 1 I/O

5 4 I/O

8 7 I/O

JTAG test data output terminal or test data input during programming and test

12 11 I/O

11 10 I

(2)

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Program Counter

PC/R0

Stack Pointer SP/R1

Status Register

SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R15

General-Purpose Register

R14

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8 Detailed Description

8.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

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Instruction Set (continued)

8.2 Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.

Table 3 shows examples of the three types of

instruction formats, and Table 4 shows the address modes.

Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) -- --> M(TONI)

Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11

(1) S = source, D = destination

INSTRUCTION FORMAT SYNTAX OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5 ---> R5

Single operands, destination only CALL R8 PC -->(TOS), R8--> PC

Relative jump, un/conditional JNE Jump-on-equal bit = 0

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6)

Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)

Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)

Immediate ✓ MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI)

Table 3. Instruction Word Formats

Table 4. Address Mode Descriptions

(1)

M(R10) -- --> R11 R10 + 2-- --> R10

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8.3 Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active

• Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled

• Low-power mode 1 (LPM1) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – DCO's dc generator is disabled if DCO not used in active mode

• Low-power mode 2 (LPM2) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc generator remains enabled – ACLK remains active

• Low-power mode 3 (LPM3) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc generator is disabled – ACLK remains active

• Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK and SMCLK are disabled – DCO's dc generator is disabled – Crystal oscillator is stopped

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8.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

Power-Up PORIFG

External Reset RSTIFG

Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest

Flash key violation KEYV

PC out-of-range

(1)

(2)

NMI NMIIFG (non)-maskable

Oscillator fault OFIFG (non)-maskable 0FFFCh 30

Flash memory access violation ACCVIFG

(2)(3)

Watchdog Timer+ WDTIFG maskable 0FFF4h 26

Timer_A2 TACCR0 CCIFG Timer_A2 TACCR1 CCIFG, TAIFG

ADC10 ADC10IFG

USI USIIFG, USISTTIFG

I/O Port P2 (two flags) P2IFG.6 to P2IFG.7

I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7

(6)

See

(4)

(2)(4)

(4)(5)

(2)(4) (2)(4) (2)(4)

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges. (2) Multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. (4) Interrupt flags are located in the module. (5) MSP430G2x31 only (6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

SYSTEM WORD

INTERRUPT ADDRESS

(non)-maskable

0FFFAh 29 0FFF8h 28 0FFF6h 27

maskable 0FFF2h 25 maskable 0FFF0h 24

0FFEEh 23

0FFECh 22 maskable 0FFEAh 21 maskable 0FFE8h 20 maskable 0FFE6h 19 maskable 0FFE4h 18

0FFE2h 17

0FFE0h 16

0FFDEh to

0FFC0h

15 to 0, lowest

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8.5 Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend rw: Bit can be read and written.

rw-0,1: Bit can be read and written. It is reset or set by PUC. rw-(0,1): Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in

OFIE Oscillator fault interrupt enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable

Address 7 6 5 4 3 2 1 0

01h

interval timer mode.

Table 7. Interrupt Flag Register 1 and 2

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

OFIFG Flag set on oscillator fault. PORIFG Power-On Reset interrupt flag. Set on VCCpower-up. RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCCpower-up. NMIIFG Set via RST/NMI pin

Address 7 6 5 4 3 2 1 0

03h

Reset on VCCpower-on or a reset condition at the RST/NMI pin in reset mode.

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8.6 Memory Organization

Table 8. Memory Organization

MSP430G2231

Memory Size 2KB Main: interrupt vector Flash 0xFFFF to 0xFFC0 Main: code memory Flash 0xFFFF to 0xF800

Information memory Size 256 Byte

RAM Size 128B

Peripherals 16-bit 01FFh to 0100h

Flash 010FFh to 01000h

027Fh to 0200h

8-bit 0FFh to 010h 8-bit SFR 0Fh to 00h

8.7 Flash Memory

The flash memory can be programmed using the Spy-Bi-Wire or JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory.

• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.

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8.8 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

8.8.1 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

• Main clock (MCLK), the system clock used by the CPU.

• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

Table 9. DCO Calibration Data (Provided From Factory In Flash Information

Memory Segment A)

DCO FREQUENCY SIZE ADDRESS

1 MHz

CALIBRATION

CALBC1_1MHZ byte 010FFh

CALDCO_1MHZ byte 010FEh

8.8.2 Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

8.8.3 Digital I/O

There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt condition is possible.

• Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.

• Read/write access to port-control registers is supported by all instructions.

• Each I/O has an individually programmable pull-up/pull-down resistor.

8.8.4 WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

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8.8.5 Timer_A2

Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 10. Timer_A2 Signal Connections – Device With ADC10

INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER

PW RSA PW RSA

2 - P1.0 1 - P1.0 TACLK TACLK

2 - P1.0 1 - P1.0 TACLK INCLK 3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1

4 - P1.2 3 - P1.2 TA1 CCI1A 4 - P1.2 3 - P1.2 8 - P1.6 7 - P1.6 TA1 CCI1B 8 - P1.6 7 - P1.6

DEVICE INPUT MODULE MODULE

SIGNAL INPUT NAME BLOCK

ACLK ACLK

SMCLK SMCLK

ACLK (internal) CCI0B 7 - P1.5 6 - P1.5

VSS GND VCC VCC

VSS GND 13 - P2.6 12 - P2.6 VCC VCC

Timer NA

CCR0 TA0

CCR1 TA1

OUTPUT

SIGNAL

8.8.6 USI

The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C.

8.8.7 ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

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8.8.8 Peripheral File Map

Table 11. Peripherals With Word Access

MODULE REGISTER DESCRIPTION OFFSET

ADC10 ADC data transfer start address ADC10SA 1BCh

ADC control 0 ADC10CTL0 01B0h ADC control 1 ADC10CTL0 01B2h ADC memory ADC10MEM 01B4h

Timer_A Capture/compare register TACCR1 0174h

Capture/compare register TACCR0 0172h Timer_A register TAR 0170h Capture/compare control TACCTL1 0164h Capture/compare control TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh

Flash Memory Flash control 3 FCTL3 012Ch

Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h

Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

NAME

Table 12. Peripherals With Byte Access

MODULE REGISTER DESCRIPTION OFFSET

ADC10 ADC analog enable ADC10AE0 04Ah

ADC data transfer control 1 ADC10DTC1 049h ADC data transfer control 0 ADC10DTC0 048h

USI USI control 0 USICTL0 078h

USI control 1 USICTL1 079h USI clock control USICKCTL 07Ah USI bit counter USICNT 07Bh USI shift register USISR 07Ch

Basic Clock System+ Basic clock system control 3 BCSCTL3 053h

Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h

Port P2 Port P2 resistor enable P2REN 02Fh

Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h

NAME

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

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SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

Table 12. Peripherals With Byte Access (continued)

MODULE REGISTER DESCRIPTION OFFSET

Port P1 Port P1 resistor enable P1REN 027h

Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h

Special Function SFR interrupt flag 2 IFG2 003h

SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

NAME

Product Folder Links: MSP430G2231-Q1

Supply voltage range, during flash memory programming

Supply voltage range, during program execution

Legend:

16 MHz

System Frequency - MHz

12 MHz

6 MHz

1.8 V Supply Voltage - V

3.3 V

2.7 V

2.2 V

3.6 V

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9 Specifications

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9.1 Absolute Maximum Ratings

Voltage applied at VCCto V Voltage applied to any pin

(2)

(1)

–0.3 V to 4.1 V

–0.3 V to VCC+ 0.3 V

Diode current at any device pin ±2 mA

Storage temperature range, T

(3)

stg

Unprogrammed device –55°C to 150°C Programmed device –55°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

9.2 Recommended Operating Conditions

Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)

MIN NOM MAX UNIT

SYSTEM

Supply voltage V

Supply voltage 0 V Operating free-air temperature I version –40 85 °C

Processor frequency (maximum MCLK frequency)

(1)(2)

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

During program execution 1.8 3.6 During flash programming 2.2 3.6

VCC= 1.8 V, Duty cycle = 50% ± 10%

VCC= 2.7 V, Duty cycle = 50% ± 10%

VCC= 3.3 V, Duty cycle = 50% ± 10%

dc 6

dc 12 MHz

dc 16

Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V

of 2.2 V.

Figure 2. Safe Operating Area

Product Folder Links: MSP430G2231-Q1

0.0

1.0

2.0

3.0

4.0

5.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC− Supply Voltage − V

Active Mode Current − mA

DCO

= 1 MHz

DCO

= 8 MHz

DCO

= 12 MHz

DCO

= 16 MHz

0.0

1.0

2.0

3.0

4.0

0.0 4.0 8.0 12.0 16.0

DCO

− DCO Frequency − MHz

Active Mode Current − mA

TA= 25 °C

TA= 85 °C

VCC= 2.2 V

VCC= 3 V

TA= 25 °C

TA= 85 °C

MSP430G2231-Q1

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SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.3 Active Mode Supply Current Into VCCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

AM,1MHz

PARAMETER TEST CONDITIONS T

= f

Active mode (AM) current (1 MHz)

DCO

ACLK

Program executes in flash,

= f

MCLK

= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

= 1 MHz, 2.2 V 220

SMCLK

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

load capacitance is chosen to closely match the required 9 pF.

3 V 300 370

(1)(2)

MIN TYP MAX UNIT

9.4 Typical Characteristics – Active Mode Supply Current (Into VCC)

Figure 3. Active Mode Current vs Supply Voltage, TA= 25°C Figure 4. Active Mode Current vs DCO Frequency

Product Folder Links: MSP430G2231-Q1

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

-40

I – Low-Power Mode Current – µA

LPM3

Vcc = 3.6 V

T – Temperature – °C

Vcc = 1.8 V

Vcc = 3 V

Vcc = 2.2 V

-20

40 60 80

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

-40

I – Low-Power Mode Current – µA

LPM4

Vcc = 3.6 V

T – Temperature – °C

Vcc = 1.8 V

Vcc = 3 V

Vcc = 2.2 V

-20

40 60 80

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LPM0,1MHz

PARAMETER TEST CONDITIONS T

= 0 MHz,

MCLK

= f

= 1 MHz,

DCO

= 32768 Hz,

Low-power mode 0 (LPM0) current

(3)

SMCLK

ACLK

BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 65 µA DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

LPM2

Low-power mode 2 (LPM2) current

(4)

= f

MCLK

= 1 MHz,

DCO

= 32768 Hz,

ACLK

BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 22 µA DCOCTL = CALDCO_1MHZ,

SMCLK

= 0 MHz,

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

= f

LPM3,LFXT1

Low-power mode 3 f (LPM3) current

(4)

DCO ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

= f

MCLK

= 32768 Hz,

SMCLK

= 0 MHz,

25°C 2.2 V 0.7 1.5 µA OSCOFF = 0 f

= f

LPM3,VLO

Low-power mode 3 f current, (LPM3)

(4)

DCO ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

= f

MCLK

from internal LF oscillator (VLO),

SMCLK

= 0 MHz,

25°C 2.2 V 0.5 0.7 µA OSCOFF = 0 f

= f

LPM4

Low-power mode 4 f (LPM4) current

(5)

MCLK

= 0 Hz,

= f

DCO ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1

= 0 MHz, 25°C 2.2 V 0.1 0.5 µA

SMCLK

85°C 2.2 V 0.8 1.5 µA

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included.

MIN TYP MAX UNIT

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(1) (2)

9.6 Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 5. LPM3 Current vs Temperature

Figure 6. LPM4 Current vs Temperature

Product Folder Links: MSP430G2231-Q1

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SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.7 Schmitt-Trigger Inputs – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V R C

Positive-going input threshold voltage V

IT+

Negative-going input threshold voltage V

IT–

Input voltage hysteresis (V

hys

Pullup/pulldown resistor 3 V 20 35 50 kΩ

Pull

Input capacitance VIN= VSSor V

IT+

– V

) 3 V 0.3 1 V

IT–

For pullup: VIN= V For pulldown: VIN= V

3 V 1.35 2.25

3 V 0.75 1.65

MIN TYP MAX UNIT

0.45 V

0.25 V

0.75 V

0.55 V

5 pF

9.8 Leakage Current – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

lkg(Px.y)

PARAMETER TEST CONDITIONS V

High-impedance leakage current

(1) (2)

3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

MIN MAX UNIT

9.9 Outputs – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V V

High-level output voltage I

Low-level output voltage I

(1) The maximum total current, I

specified.

(OHmax)

and I

= –6 mA

(OHmax)

= 6 mA

(OLmax)

, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

(1)

3 V VCC– 0.3 V 3 V VSS+ 0.3 V

MIN TYP MAX UNIT

9.10 Output Frequency – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Px.y

Port_CLK

PARAMETER TEST CONDITIONS V

Port output frequency (with load)

Px.y, CL= 20 pF, RL= 1 kΩ

Clock output frequency Px.y, CL= 20 pF

(2)

(1) (2)

3 V 12 MHz 3 V 16 MHz

(1) A resistive divider with 2 × 0.5 kΩ between VCCand VSSis used as load. The output is connected to the center tap of the divider. (2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

MIN TYP MAX UNIT

Product Folder Links: MSP430G2231-Q1

VOH− High-Level Output Voltage − V

−25

−20

−15

−10

−5

0 0.5 1 1.5 2 2.5

VCC= 2.2 V P1.7

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOH− High-Level Output Voltage − V

−50

−40

−30

−20

−10

0 0.5 1 1.5 2 2.5 3 3.5

VCC= 3 V P1.7

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOL− Low-Level Output Voltage − V

0 0.5 1 1.5 2 2.5

VCC= 2.2 V P1.7

TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

VOL− Low-Level Output Voltage − V

0 0.5 1 1.5 2 2.5 3 3.5

VCC= 3 V P1.7

TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.11 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

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Figure 7. Typical Low-Level Output Current vs Low-Level Figure 8. Typical Low-Level Output Current vs Low-Level

Output Voltage Output Voltage

Figure 9. Typical High-Level Output Current vs High-Level Figure 10. Typical High-Level Output Current vs High-Level

Output Voltage Output Voltage

Product Folder Links: MSP430G2231-Q1

CC(drop)

3 V

0.5

1.5

0.001 1 1000

Typical Conditions

1 ns 1 ns

tpw− Pulse Width − µs

CC(drop)

− V

tpw− Pulse Width − µs

VCC= 3 V

d(BOR)

(B_IT−)

hys(B_IT−)

CC(star t)

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MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.12 POR, BOR

(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC(start)

(B_IT–)

hys(B_IT–)

d(BOR)

(reset)

PARAMETER TEST CONDITIONS V

See Figure 11 dVCC/dt ≤ 3 V/s 0.7 × V See Figure 11 through Figure 13 dVCC/dt ≤ 3 V/s 1.35 V See Figure 11 dVCC/dt ≤ 3 V/s 130 mV See Figure 11 2000 µs Pulse duration needed at RST/NMI pin to

accepted reset internally

2.2 V, 3 V 2 µs

(1) The current consumption of the brownout module is already included in the ICCcurrent consumption data. The voltage level V

(2) During power up, the CPU begins code execution following a period of t

must not be changed until VCC≥ V

hys(B_IT–)

is ≤ 1.8 V.

CC(min)

, where V

after VCC= V

is the minimum supply voltage for the desired operating frequency.

CC(min)

d(BOR)

(B_IT–)

MIN TYP MAX UNIT

(B_IT–)

+ V

. The default DCO settings

hys(B_IT–)

(B_IT–)

Figure 12. V

CC(drop)

Level With a Square Voltage Drop to Generate a POR or BOR Signal

Figure 11. POR and BOR vs Supply Voltage

Product Folder Links: MSP430G2231-Q1

0.5

1.5

CC(drop)

tpw− Pulse Width − µs

CC(drop)

− V

3 V

0.001 1 1000

tpw− Pulse Width − µs

tf= t

Typical Conditions

VCC= 3 V

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

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Figure 13. V

CC(drop)

Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

Product Folder Links: MSP430G2231-Q1

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

average

DCO(RSEL,DCO) DCO(RSEL,DCO+1)

32 × f × f

f =

MOD × f + (32 – MOD) × f

MSP430G2231-Q1

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SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.13 Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.

• DCO control bits DCOx have a step size as defined by parameter S

• Modulation control bits MODx select how often f f

DCO(RSEL,DCO)

is used for the remaining cycles. The frequency is an average equal to:

DCO(RSEL,DCO+1)

DCO

is used within the period of 32 DCOCLK cycles. The frequency

9.14 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

DCO(0,0)

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

RSEL

DCO

PARAMETER TEST CONDITIONS V

RSELx < 14 1.8 3.6 V

Supply voltage RSELx = 14 2.2 3.6 V

RSELx = 15 3 3.6 V DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3 V 0.06 0.14 MHz DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3 V 0.12 MHz DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3 V 0.15 MHz DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3 V 0.21 MHz DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3 V 0.30 MHz DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3 V 0.41 MHz DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3 V 0.58 MHz DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3 V 0.80 MHz DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3 V 0.8 1.5 MHz DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3 V 1.6 MHz DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3 V 2.3 MHz DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3 V 3.4 MHz DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3 V 4.25 MHz DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3 V 4.3 7.3 MHz DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3 V 7.8 MHz DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3 V 8.6 13.9 MHz DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 15.25 MHz DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 21 MHz Frequency step between

range RSEL and RSEL+1 Frequency step between

tap DCO and DCO+1

= f

RSEL

DCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

= f

DCO

DCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

3 V 1.35 ratio

3 V 1.08 ratio

Duty cycle Measured at SMCLK output 3 V 50 %

MIN TYP MAX UNIT

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DCO Frequency − MHz

0.10

1.00

10.00

0.10 1.00 10.00

DCO Wake Time − µs

RSELx = 0...11

RSELx = 12...15

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

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9.15 Calibrated DCO Frequencies – Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS T

1-MHz tolerance over 0°C to 85°C temperature

(1)

BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, 3 V -3 ±0.5 +3 % calibrated at 30°C and 3 V

-40°C to 105°C

BCSCTL1= CALBC1_1MHz,

1-MHz tolerance over V

1-MHz tolerance overall DCOCTL = CALDCO_1MHz, 1.8 V to 3.6 V -6 ±3 +6 %

DCOCTL = CALDCO_1MHz, 30°C 1.8 V to 3.6 V -3 ±2 +3 % calibrated at 30°C and 3 V

BCSCTL1= CALBC1_1MHz, calibrated at 30°C and 3 V

-40°C to 85°C

-40°C to 105°C

(1) This is the frequency change from the measured frequency at 30°C over temperature.

MIN TYP MAX UNIT

9.16 Wakeup From Lower-Power Modes (LPM3, LPM4) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

DCO,LPM3/4

CPU,LPM3/4

PARAMETER TEST CONDITIONS V

DCO clock wakeup time from LPM3 BCSCTL1= CALBC1_1MHz, or LPM4

CPU wakeup time from LPM3 or 1/f LPM4

(1)

(2)

DCOCTL = CALDCO_1MHz

3 V 1.5 µs

(1) The DCO clock wakeup time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock

edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

MIN TYP MAX UNIT

MCLK

Clock,LPM3/4

9.17 Typical Characteristics – DCO Clock Wakeup Time From LPM3, LPM4

Figure 14. DCO Wakeup Time From LPM3 vs DCO Frequency

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MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.18 Crystal Oscillator, Xt1, Low-Frequency Mode

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LFXT1,LF

PARAMETER TEST CONDITIONS V

LFXT1 oscillator crystal frequency, LF mode 0, 1

XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz

LFXT1 oscillator logic level

LFXT1,LF,logic

square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz LF mode

XTS = 0, LFXT1Sx = 0,

Oscillation allowance for LF crystals

f XTS = 0, LFXT1Sx = 0,

LFXT1,LF

= 32768 Hz, C

L,eff

= 6 pF

= 12 pF

XTS = 0, XCAPx = 0 1

L,eff

Integrated effective load capacitance, LF mode

(2)

XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 XTS = 0, Measured at P2.0/ACLK,

LFXT1,LF

= 32768 Hz

XTS = 0, XCAPx = 0, LFXT1Sx = 3

(4)

2.2 V 10 10000 Hz

Fault,LF

Duty cycle, LF mode 2.2 V 30 50 70 % Oscillator fault frequency,

LF mode

(3)

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

MIN TYP MAX UNIT

500

200

kΩ

9.19 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER T

VLO

VLO/dT

VLO

VLO frequency -40°C to 85°C 3 V 4 12 20 kHz VLO frequency temperature drift -40°C to 85°C 3 V 0.5 %/°C

/dVCCVLO frequency supply voltage drift 25°C 1.8 V to 3.6 V 4 %/V

MIN TYP MAX UNIT

9.20 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

TA,cap

Timer_A input clock frequency External: TACLK, INCLK f

Duty cycle = 50% ± 10%

Timer_A capture timing TA0, TA1 3 V 20 ns

Product Folder Links: MSP430G2231-Q1

MIN TYP MAX UNIT

SYSTEM

MHz

VOL− Low-Level Output Voltage − V

0.0

1.0

2.0

3.0

4.0

5.0

0.0 0.2 0.4 0.6 0.8 1.0

VCC= 2.2 V

TA= 25°C

I − Low-Level Output Current − mA

TA= 85°C

VOL− Low-Level Output Voltage − V

0.0

1.0

2.0

3.0

4.0

5.0

0.0 0.2 0.4 0.6 0.8 1.0

VCC= 3 V

TA= 25°C

I − Low-Level Output Current − mA

TA= 85°C

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.21 USI, Universal Serial Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

USI

OL,I2C

PARAMETER TEST CONDITIONS V

External: SCLK,

USI clock frequency Duty cycle = 50% ±10%, f

SPI slave mode

Low-level output voltage on SDA and SCL 3 V V

USI module in I2C mode, V I

= 1.5 mA + 0.4

(OLmax)

MIN TYP MAX UNIT

9.22 Typical Characteristics – USI Low-Level Output Voltage On SDA and SCL

SYSTEM

www.ti.com

MHz

Figure 15. USI Low-Level Output Voltage vs Output Current Figure 16. USI Low-Level Output Voltage vs Output Current

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

www.ti.com

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.23 10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

ADC10

PARAMETER TEST CONDITIONS T

Analog supply voltage VSS= 0 V 2.2 3.6 V Analog input voltage

ADC10 supply current

(2)

(3)

All Ax terminals, Analog inputs selected in ADC10AE register

ADC10CLK

ADC10ON = 1, REFON = 0,

= 5.0 MHz,

ADC10SHT0 = 1, ADC10SHT1 = 0,

ADC10DIV = 0

REF+

Reference supply current, reference buffer disabled

ADC10CLK

ADC10ON = 0, REF2_5V = 0, 0.25 0.4 REFON = 1, REFOUT = 0

(4)

ADC10CLK

ADC10ON = 0, REF2_5V = 1, 0.25 0.4

= 5.0 MHz,

REFON = 1, REFOUT = 0

REFB,0

f Reference buffer supply ADC10ON = 0, REFON = 1, current with ADC10SR = 0

ADC10CLK

(4)

REF2_5V = 0, REFOUT = 1,

= 5.0 MHz,

ADC10SR = 0

REFB,1

f Reference buffer supply ADC10ON = 0, REFON = 1, current with ADC10SR = 1

ADC10CLK

(4)

REF2_5V = 0, REFOUT = 1,

= 5.0 MHz,

ADC10SR = 1

Input capacitance 3 V 27 pF Input MUX ON resistance 0 V ≤ VAx≤ V

Only one terminal Ax can be selected

at one time

(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter. (2) The analog input voltage range must be within the selected reference voltage range VR+to VR–for valid conversion results. (3) The internal reference supply current is not included in current consumption parameter I (4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

3 V 0 V

3 V 0.6 1.2 mA

3 V mA

3 V 1.1 1.4 mA

3 V 0.5 0.7 mA

3 V 1000 2000 Ω

ADC10

(1)

MIN TYP MAX UNIT

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.24 10-Bit ADC, Built-In Voltage Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC,REF+

REF+

LD,VREF+

VREF+

REF+

REFON

REFBURST

PARAMETER TEST CONDITIONS V

≤ 1 mA, REF2_5V = 0 2.2

Positive built-in reference analog supply voltage range

Positive built-in reference voltage

VREF+

≤ 1 mA, REF2_5V = 1 2.9

VREF+

≤ I

VREF+

max, REF2_5V = 0 1.41 1.5 1.59

VREF+

≤ I

max, REF2_5V = 1 2.35 2.5 2.65

VREF+

Maximum VREF+ load current

= 500 µA ± 100 µA,

VREF+

Analog input voltage VAx≈ 0.75 V, ±2

VREF+ load regulation 3 V LSB

REF2_5V = 0 I

= 500 µA ± 100 µA,

VREF+

Analog input voltage VAx≈ 1.25 V, ±2

3 V V

3 V ±1 mA

REF2_5V = 1 I

= 100 µA → 900 µA,

load regulation VAx≈ 0.5 × VREF+,

REF+

response time Error of conversion result ≤ 1 LSB,

VREF+

3 V 400 ns

ADC10SR = 0

Maximum capacitance at pin VREF+

Temperature coefficient I Settling time of internal

reference voltage to 99.9% 3.6 V 30 µs VREF

Settling time of reference buffer to 99.9% VREF

≤ ±1 mA, REFON = 1, REFOUT = 1 3 V 100 pF

VREF+

= const with 0 mA ≤ I

VREF+

= 0.5 mA, REF2_5V = 0,

VREF+

REFON = 0 → 1 I

= 0.5 mA,

VREF+

REF2_5V = 1, REFON = 1, 3 V 2 µs

≤ 1 mA 3 V ±100

VREF+

REFBURST = 1, ADC10SR = 0

MIN TYP MAX UNIT

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ppm/

°C

Product Folder Links: MSP430G2231-Q1

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MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.25 10-Bit ADC, External Reference

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

VEREF+ > VEREF–,

VEREF+ V

VEREF– VEREF+ > VEREF– 0 1.2 V

Positive external reference input voltage range

Negative external reference input voltage range

(2)

(4)

Differential external reference

ΔVEREF input voltage range, VEREF+ > VEREF–

SREF1 = 1, SREF0 = 0 VEREF– ≤ VEREF+ ≤ VCC– 0.15 V,

SREF1 = 1, SREF0 = 1

(3)

(5)

ΔVEREF = VEREF+ – VEREF–

VEREF+

VEREF–

0 V ≤ VEREF+ ≤ VCC,

Static input current into VEREF+ µA

Static input current into VEREF– 0 V ≤ VEREF– ≤ V

SREF1 = 1, SREF0 = 0 0 V ≤ VEREF+ ≤ VCC– 0.15 V ≤ 3 V,

SREF1 = 1, SREF0 = 1

(3)

3 V ±1

3 V 0 3 V ±1 µA

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current I

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

REFB

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

MIN TYP MAX UNIT

1.4 V

1.4 3

1.4 V

9.26 10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

ADC10CLK

ADC10OSC

ADC10 input clock For specified performance of frequency ADC10 linearity parameters

ADC10 built-in ADC10DIVx = 0, ADC10SSELx = 0, oscillator frequency f

ADC10CLK

= f

ADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0,

CONVERT

ADC10ON

Conversion time µs

Turn-on settling time of the ADC

ADC10CLK

ADC10SSELx ≠ 0

(1)

= f

ADC10OSC

from ACLK, MCLK, or SMCLK,

(1) The condition is that the error in a conversion started after t

settled.

ADC10SR = 0 0.45 6.3 ADC10SR = 1 0.45 1.5

3 V MHz

3 V 3.7 6.3 MHz

3 V 2.06 3.51

is less than ±0.5 LSB. The reference and input signal are already

ADC10ON

MIN TYP MAX UNIT

ADC10DIV ×

1/f

9.27 10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

E E E E E

Integral linearity error 3 V ±1 LSB

Differential linearity error 3 V ±1 LSB

Offset error Source impedance RS< 100 Ω 3 V ±1 LSB

Gain error 3 V ±1.1 ±2 LSB

Total unadjusted error 3 V ±2 ±5 LSB

MIN TYP MAX UNIT

13 ×

ADC10CLK

100 ns

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

www.ti.com

9.28 10-Bit ADC, Temperature Sensor and Built-In V

MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

SENSOR

Sensor(sample)

VMID

MID

VMID(sample)

Temperature sensor supply REFON = 0, INCHx = 0Ah, current

Sample time required if channel ADC10ON = 1, INCHx = 0Ah, 10 is selected

Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh 3 V VCCdivider at channel 11 3 V 1.5 V Sample time required if channel ADC10ON = 1, INCHx = 0Bh,

11 is selected

(1) The sensor current I

high). When REFON = 1, I input (INCH = 0Ah).

(1)

(3)

TA= 25°C ADC10ON = 1, INCHx = 0Ah

(2)

Error of conversion result ≤ 1 LSB

ADC10ON = 1, INCHx = 0Bh, V

≉ 0.5 × V

MID

(5)

is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

SENSOR

is included in I

Error of conversion result ≤ 1 LSB

. When REFON = 0, I

REF+

applies during conversion of the temperature sensor

SENSOR

3 V 60 µA 3 V 3.55 mV/°C 3 V 30 µs

3 V 1220 ns

(2) The following formula can be used to calculate the temperature sensor output voltage:

Sensor,typ

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t (4) No additional current is needed. The V (5) The on-time t

= TC = TC

(273 + T [°C] ) + V

Sensor

T [°C] + V

Sensor

is included in the sampling time t

VMID(on)

Sensor(TA

Offset,sensor

[mV] or

= 0°C) [mV]

is used during sampling.

MID

VMID(sample)

; no additional on time is needed.

MIN TYP MAX UNIT

9.29 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC(PGM/ERASE)

FTG

PGM

ERASE

CPT

CMErase

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Seg Erase

PARAMETER TEST

CONDITIONS

Program and erase supply voltage 2.2 3.6 V Flash timing generator frequency 257 476 kHz Supply current from VCCduring program 2.2 V, 3.6 V 1 5 mA Supply current from VCCduring erase 2.2 V, 3.6 V 1 7 mA Cumulative program time

(1)

Cumulative mass erase time 2.2 V, 3.6 V 20 ms Program/erase endurance 10 Data retention duration TJ= 25°C 15 years Word or byte program time Block program time for first byte or word Block program time for each additional byte or

word Block program end-sequence wait time Mass erase time Segment erase time

(2) (2)

(2)

(2) (2) (2)

MIN TYP MAX UNIT

2.2 V, 3.6 V 10 ms

10593 t

(4)

SENSOR(on)

30 t 25 t

18 t

6 t

4819 t

µA

cycles

FTG FTG

FTG

FTG FTG FTG

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the Flash Controller's state machine (t

= 1/f

FTG

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

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SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

9.30 RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(RAMh)

RAM retention supply voltage

(1) This parameter defines the minimum supply voltage VCCwhen the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

(1)

CPU halted 1.6 V

9.31 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

SBW

SBW,Low

SBW,En

SBW,Ret

TCK

Internal

Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs Spy-Bi-Wire enable time

(TEST high to acceptance of first clock edge

(1)

)

Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 15 100 µs

TCK input frequency

(2)

Internal pulldown resistance on TEST 2.2 V, 3 V 25 60 90 kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the maximum t

applying the first SBWTCK clock edge.

(2) f

9.32 JTAG Fuse

may be restricted to meet the timing requirements of the module selected.

TCK

(1)

time after pulling the TEST/SBWTCK pin high before

SBW,En

2.2 V, 3 V 1 µs

2.2 V 0 5 MHz 3 V 0 10 MHz

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

CC(FB)

Supply voltage during fuse-blow condition TA= 25°C 2.5 V Voltage level on TEST for fuse blow 6 7 V Supply current into TEST during fuse blow 100 mA Time to blow fuse 1 ms

MIN TYP MAX UNIT

(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

Product Folder Links: MSP430G2231-Q1

P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/A1 P1.2/TA0.1/A2

To Module

ACLK

PxOUT.y

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

INCHx

To ADC10

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Directio n 0: Input 1: Output

PxDIR.y

PxSEL.y

ADC10AE0.y

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10 I/O Port Schematics

10.1 Port P1 Pin Schematic: P1.0 To P1.2, Input/Output With Schmitt Trigger

www.ti.com

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

www.ti.com

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

Port P1 Pin Schematic: P1.0 To P1.2, Input/Output With Schmitt Trigger (continued)

Table 13. Port P1 (P1.0 To P1.2) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P1.x) x FUNCTION

P1.0/ P1.x (I/O) I: 0; O: 1 0 0 TA0CLK/ TA0.TACLK 0 1 0 ACLK/ ACLK 1 1 0 A0 A0 X X 1 (y = 0) P1.1/ P1.x (I/O) I: 0; O: 1 0 0 TA0.0/ TA0.0 1 1 0

A1 A1 X X 1 (y = 1) P1.2/ P1.x (I/O) I: 0; O: 1 0 0 TA0.1/ TA0.1 1 1 0

A2/ A2 X X 1 (y = 2)

TA0.CCI0A 0 1 0

TA0.CCI1A 0 1 0

P1DIR.x P1SEL.x

ADC10AE.x (INCH.y = 1)

Product Folder Links: MSP430G2231-Q1

To Module

ADC10CLK

PxOUT.y

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction 0: Input 1: Output

PxDIR.y

PxSEL.y

P1.3/ADC10CLK/A3/VREF-/VEREF-

INCHx = y

To ADC10

VSS

SREF2

ADC10AE0.y

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.2 Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger

www.ti.com

PIN NAME (P1.x) x FUNCTION

P1.3/ P1.x (I/O) I: 0; O: 1 0 0 ADC10CLK/ ADC10CLK 1 1 0 A3/ 3 A3 X X 1 (y = 3) VREF-/ VREF- X X 1 VEREF- VEREF- X X 1

Table 14. Port P1 (P1.3) Pin Functions

Product Folder Links: MSP430G2231-Q1

CONTROL BITS OR SIGNALS

P1DIR.x P1SEL.x

ADC10AE.x

(INCH.x = 1)

To Module

SMCLK

PxOUT.y

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Directio n 0: Input 1: Output

PxDIR.y

PxSEL.y

P1.4/SMCLK/A4/VREF+/VEREF+/TCK

INCHx = y

To ADC10

ADC10AE0.y

From JTAG

To JTAG

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SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.3 Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger

MSP430G2231-Q1

Table 15. Port P1 (P1.4) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P1.x) x FUNCTION

P1DIR.x P1SEL.x

P1.4/ P1.x (I/O) I: 0; O: 1 0 0 0 SMCLK/ SMCLK 1 1 0 0 A4/ A4 X X 1 (y = 4) 0 VREF+/ VREF+ X X 1 0 VEREF+/ VEREF+ X X 1 0 TCK TCK X X 0 1

Product Folder Links: MSP430G2231-Q1

ADC10AE.x JTAG

(INCH.x = 1) Mode

Bus

Keeper

P1.5/TA0.0/A5/TMS

To Module

From Module

PxOUT.y

PxIN.y

PxSEL.y

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction 0: Input 1: Output

PxDIR.y

PxSEL.y

From JTAG

To JTAG

INCHx

To ADC10

ADC10AE0.y

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.4 Port P1 Pin Schematic: P1.5, Input/Output With Schmitt Trigger

www.ti.com

Table 16. Port P1 (P1.5) Pin Functions

PIN NAME (P1.x) x FUNCTION

CONTROL BITS OR SIGNALS

P1DIR.x P1SEL.x USIP.x

ADC10AE.x JTAG

(INCH.x = 1) Mode

P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0 0 TA0.0/ TA0.0 1 1 0 0 0 A5/ 5 A5 X X X 1 (y = 5) 0 SCLK/ SCLK X X 1 0 0 TMS TMS X X 0 0 1

Product Folder Links: MSP430G2231-Q1

Bus

Keeper

P1.6/TA0.1/SDO/SCL/A6/TDI

To Module

From USI

PxOUT.y

PxIN.y

PxSEL.y or

USIPE6

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction 0: Input 1: Output

PxDIR.y

USIPE6

From JTAG

To JTAG

INCHx

To ADC10

ADC10AE0.y

from USI

PxSEL.y

USI in I2C mode: Out put driver drives low level onl y. Driver is disabled in JTAG mode.

www.ti.com

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.5 Port P1 Pin Schematic: P1.6, Input/Output With Schmitt Trigger

MSP430G2231-Q1

Table 17. Port P1 (P1.6) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P1.x) x FUNCTION

P1DIR.x P1SEL.x USIP.x

P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0 0 TA0.1/ TA0.1 1 1 0 0 0

A6/ A6 X X 0 1 (y = 6) 0 SDO/ SDO X X 1 0 0 TDI/TCLK TDI/TCLK X X 0 0 1

TA0.CCR1B 0 1 0 0 0

ADC10AE.x JTAG

(INCH.x = 1) Mode

Product Folder Links: MSP430G2231-Q1

Bus

Keeper

P1.7/SDI/SDA/A7/TDO/TDI

To Module

From US I

PxOUT.y

PxIN.y

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction 0: Input 1: Output

PxDIR.y

USIPE7

From JTAG

To JTAG

INCHx

To ADC10

ADC10AE0.y

from USI

PxSEL.y

PxSEL.y or

USIPE7

PxSEL.y

From JTAG

To JTAG

USI in I2C mode: Outp ut driver d rives lo w level only. Driver is disabled in JTAG mode.

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.6 Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger

www.ti.com

PIN NAME (P1.x) x FUNCTION

P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0 0 A7/ A7 X X 0 1 (y = 7) 0 SDI/SDO SDI/SDO X X 1 0 0

Table 18. Port P1 (P1.7) Pin Functions

CONTROL BITS OR SIGNALS

P1DIR.x P1SEL.x USIP.x

ADC10AE.x JTAG

(INCH.x = 1) Mode

TDO/TDI TDO/TDI X X 0 0 1

Product Folder Links: MSP430G2231-Q1

XIN/P2.6/TA0.1

XOUT/P2.7

LF off

LFXT1CLK

PxSEL.6 PxSEL.7

To Module

from Module

PxOUT.y

Bus

Keeper

PxIN.y

PxSEL.6

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Directio n 0: Input 1: Output

PxDIR.y

PxSEL.6

www.ti.com

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.7 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger

MSP430G2231-Q1

PIN NAME (P2.x) x FUNCTION

XIN XIN 0 1 1 P2.6 6 P2.x (I/O) I: 0; O: 1 0 X TA0.1 TA0.1

(1) BCSCTL3.LFXT1Sx = 11 is required.

Table 19. Port P2 (P2.6) Pin Functions

CONTROL BITS OR SIGNALS

P2DIR.x P2SEL.6 P2SEL.7

(1)

1 1 X

Product Folder Links: MSP430G2231-Q1

XIN/P2.6/TA0.1

XOUT/P2.7

LF off

LFXT1CLK

PxSEL.6 PxSEL.7

To Module

from Module

PxOUT.y

Bus

Keeper

PxIN.y

PxSEL.7

PxREN.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction 0: Input 1: Output

PxDIR.y

PxSEL.7

from P2.6/XIN

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

10.8 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger

www.ti.com

PIN NAME (P2.x) x FUNCTION

XOUT XOUT 1 1 1 P2.7 P2.x (I/O) I: 0; O: 1 X 0

Table 20. Port P2 (P2.7) Pin Functions

CONTROL BITS OR SIGNALS

P2DIR.x P2SEL.6 P2SEL.7

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

www.ti.com

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Tools Support

All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.

11.1.1.1 Hardware Features

See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.

MSP430 4-Wire 2-Wire Clock State Trace

Architecture JTAG JTAG Control Sequencer Buffer

MSP430 Yes Yes 2 No Yes No No No

Break- Range LPMx.5

points Break- Debugging

(N) points Support

11.1.1.2 Recommended Hardware Options

11.1.1.2.1 Target Socket Boards

The target socket boards allow easy programming and debugging of the device using JTAG. They also feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included. The following table shows the compatible target boards and the supported packages.

Package Target Board and Programmer Bundle Target Board Only

14-pin TSSOP (PW)

11.1.1.2.2 Experimenter Boards

MSP-FET430U14 MSP-TS430PW14

MSP-FET430U28A MSP-TS430PW28A

Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools for details.

11.1.1.2.3 Debugging and Programming Tools

Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full list of available tools at www.ti.com/msp430tools.

11.1.1.2.4 Production Programmers

The production programmers expedite loading firmware to devices by programming several devices simultaneously.

Part Number PC Port Features Provider

MSP-GANG Serial and USB Program up to eight devices at a time. Works with PC or standalone. Texas Instruments

11.1.1.3 Recommended Software Options

11.1.1.3.1 Integrated Development Environments

Software development tools are available from TI or from third parties. Open source solutions are also available. This device is supported by Code Composer Studio™ IDE (CCS).

11.1.1.3.2 MSP430Ware

MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices

delivered in a convenient package. MSP430Ware is available as a component of CCS or as a standalone package.

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

11.1.1.3.3 Command-Line Programmer

www.ti.com

MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a

FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.

11.1.1.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use. TI E2E Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

11.1.2 Device and Development Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of three prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).

Device development evolutionary flow:

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality and

reliability verification MSP – Fully qualified production device Support tool development evolutionary flow: MSPX – Development-support product that has not yet completed Texas Instruments internal qualification

testing. MSP – Fully-qualified development-support product XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of

the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZP) and temperature range (for example, T). Figure 17 provides a legend for reading the complete device name for any family member.

Product Folder Links: MSP430G2231-Q1

Processor Family

CC = Embedded RF Radio MSP = Mixed Signal Processor XMS = Experimental Silicon PMS = Prototype Device

430 MCU Platform TI’s Low Power Microcontroller Platform

Device Type Memory Type

C = ROM F = Flash FR = FRAM G = Flash or FRAM (Value Line) L = No Nonvolatile Memory

Specialized Application

AFE = Analog Front End BT = Preprogrammed with Bluetooth BQ = Contactless Power CG = ROM Medical FE = Flash Energy Meter FG = Flash Medical FW = Flash Electronic Flow Meter

Series 1 Series = Up to 8 MHz

2 Series = Up to 16 MHz 3 Series = Legacy 4 Series = Up to 16 MHz w/ LCD

5 Series = Up to 25 MHz 6 Series = Up to 25 MHz w/ LCD 0 = Low Voltage Series

Feature Set Various Levels of Integration Within a Series

Optional: A = Revision N/A

Optional: Temperature Range S = 0°C to 50 C

C to 70 C I = -40 C to 85 C T = -40 C to 105 C

C = 0° °

° °

Packaging

www.ti.com/packaging

Optional: Tape and Reel T = Small Reel (7 inch)

R = Large Reel (11 inch) No Markings = Tube or Tray

Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)

-HT = Extreme Temperature Parts (-55°C to 150°C)

-Q1 = Automotive Q100 Qualified

MSP 430 F 5 438 A I ZQW T XX

Processor Family

Series

Optional: Temperature Range

430 MCU Platform

PackagingDevice Type

Optional: A = Revision

Optional: Tape and Reel

Feature Set

Optional: Additional Features

www.ti.com

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

Figure 17. Device Nomenclature

11.2 Documentation Support

11.2.1 Related Documents

The following documents describe the MSP430G2231 device. Copies of these documents are available on the Internet at www.ti.com.

SLAU144 MSP430x2xx Family User's Guide. Detailed information on the modules and peripherals available in

SLAZ417 MSP430G2231 Device Erratasheet. Describes the known exceptions to the functional specifications

11.3 Community Resources

Use. TI E2E Community

this device family.

for the MSP430G2231 device.

Product Folder Links: MSP430G2231-Q1

MSP430G2231-Q1

SLAS787B –NOVEMBER 2011–REVISED MARCH 2014

www.ti.com

Community Resources (continued)

TI Embedded Processors Wiki

11.4 Trademarks

MSP430, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: MSP430G2231-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Nov-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430G2231IPW4RQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 G2231Q1

MSP430G2231IRSARQ1 ACTIVE QFN RSA 16 3000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G

2231Q1

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com

26-Nov-2014

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF MSP430G2231-Q1 :

•

Catalog: MSP430G2231

•

Enhanced Product: MSP430G2231-EP

NOTE: Qualified Version Definitions:

•

Catalog - TI's standard catalog product

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Mar-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

MSP430G2231IPW4RQ1 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

MSP430G2231IRSARQ1 QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Quadrant

Pin1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Mar-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430G2231IPW4RQ1 TSSOP PW 14 2000 367.0 367.0 35.0

MSP430G2231IRSARQ1 QFN RSA 16 3000 367.0 367.0 35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.

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Texas Instruments MSP430G2231 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual