Texas Instruments MSP430FG4270IDL, MSP430FG4270 Datasheet

MSP430FG42x0

40 C to 85 C

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption:

Active Mode: 250 μA at 1 MHz, 2.2 V Standby Mode: 1.1 μA Off Mode (RAM Retention): 0.1 μA

D Five Power Saving Modes D Wake-Up From Standby Mode in Less

Than 6 μs

D 16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D 16-Bit Sigma-Delta A/D Converter With

Internal Reference and Five Differential Analog Inputs

D 12-Bit D/A Converter D Two Configurable Operational Amplifiers D 16-Bit Timer_A With Three

Capture/Compare Registers

D Brownout Detector

D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Integrated LCD Driver With Contrast

Control for up to 56 Segments

D MSP430FG42x0 Family Members Include:

MSP430FG4250: 16KB+256B Flash Memory

256B RAM

MSP430FG4260: 24KB+256B Flash Memory

256B RAM

MSP430FG4270: 32KB+256B Flash Memory

256B RAM

D For Complete Module Descriptions, See

MSP430x4xx Family User’s Guide, Literature Number SLAU056

D For Additional Device Information, See

MSP430FG42x0 Device Erratasheet,

Literature Number SLAZ038

D Bootstrap Loader

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs.

The MSP430FG42x0 is a microcontroller configuration with a 16-bit timer, a high-performance 16-bit sigma-delta A/D converter, 12-bit D/A converter, two configurable operational amplifiers, 32 I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc.

AVAILABLE OPTIONS

PACKAGED DEVICES

−40°C to 85°C

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

PLASTIC 48-PIN SSOP

(DL)

MSP430FG4250IDL MSP430FG4250IRGZ MSP430FG4260IDL MSP430FG4260IRGZ MSP430FG4270IDL MSP430FG4270IRGZ

PLASTIC 48-PIN QFN

(RGZ)

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MSP430FG42x0 MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

pin designation, DL package

DL PACKAGE

(TOP VIEW)

TDO/TDI

TDI/TCLK

TMS

TCK

/NMI

RST

XIN

XOUT

REF

P6.0/A0+/OA0O

P6.1/A0−/OA0FB

P6.2/A1+/OA1O

P6.3/A1−/OA1FB

P6.4/OA0I1 P6.5/OA0I2 P6.6/OA1I1 P6.7/OA1I2

P1.7/A2+

P1.6/A2−/OA0I0

P1.5/TACLK/ACLK/A3+

P1.4/A3−/OA1I0/DAC0

1 2 3 4 5 6 7 8

MSP430FG42x0IDL

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

P5.4/COM3 P5.3/COM2 P5.2/COM1 COM0 P2.0/S13/SW0C P2.1/S12/SW1C P2.2/S11 P2.3/S10 P2.4/S9 P2.5/S8 P2.6/S7 P2.7/S6 S5 P5.7/S4 P5.6/S3 P5.5/S2 P5.0/S1 P5.1/S0 LCDCAP/R23 LCDREF/R13 P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1/A4− P1.3/TA2/A4+

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pin designation, RGZ package

XIN

XOUT

REF

P6.0/A0+/OA0O

P6.1/A0−/OA0FB

P6.2/A1+/OA1O

P6.3/A1−/OA1FB

P6.4/OA0I1 P6.5/OA0I2

1 2 3 4 5 6 7 8 9 10 11 12

RGZ PACKAGE

(TOP VIEW)

TCK

TMS

TDI/TCLK

TDO/TDI

RST/NMI

46 45 44 43 42 41 40 39 38

MSP430FG42x0IRGZ

15 16 17 18 19 20 21 22 23

P5.4/COM3

MSP430FG42x0

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

P5.3/COM2

P5.2/COM1

COM0

P2.0/S13/SW0C

P2.1/S12/SW1C

P2.2/S11

P2.3/S10

P2.4/S9

P2.5/S8

P2.6/S7

P2.7/S6

P5.7/S4

P5.6/S3

P5.5/S2

P5.0/S1

P5.1/S0

P6.6/OA1I1

P1.7/A2+

P6.7/OA1I2

P1.6/A2−/OA0I0

P1.3/TA2/A4+

P1.4/A3−/OA1I0/DAC0

P1.5/TACLK/ACLK/A3+

P1.2/TA1/A4−

P1.1/TA0/MCLK

P1.0/TA0

LCDREF/R13

LCDCAP/R23

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MSP430FG42x0 MIXED SIGNAL MICROCONTROLLER

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functional block diagram

XIN

Oscillator

FLL+

8 MHz

CPU

incl. 16

Registers

Emulation

Module

JTAG

Interface

XOUT

MCLK

DVCCDVSSAVCCAV

ACLK

MAB

MDB

Flash

32KB 24KB 16KB

POR/

Brownout

RST/NMI

SMCLK

RAM

256B

Watchdog

Timer+

WDT+

15/16-Bit

Port 1

8 I/O

Interrupt

Capability

Timer_A3

3 CC Reg

Port 2

8 I/O

Interrupt

Capability

Basic

Timer 1

1 Interrupt

Vector

LCD_A

Segments

1,2,3,4 MUX

SD16_A

16 Bit

Port 5

8 I/O

OA0, OA1

2 Op

Amps

GND

Switches

Port 6

8 I/O

DAC12

12 Bit

1 Channel

Voltage Out

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Terminal Functions

TERMINAL

NAME DL

TDO/TDI 1 43 I/O Test data output. TDO/TDI data output or programming data input terminal TDI/TCLK 2 44 I Test data input / test clock input. The device protection fuse is connected to TDI/TCLK. TMS 3 45 I Test mode select. TMS is used as an input port for device programming and test. TCK 4 46 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 5 47 I General-purpose digital I/O / reset input / nonmaskable interrupt input DV

XIN 8 2 I Input terminal of crystal oscillator XT1 XOUT 9 3 O Output terminal of crystal oscillator XT1 AV

REF

P6.0/A0+/OA0O 13 7 I/O General-purpose digital I/O / analog input A0+ / OA0 output P6.1/A0−/OA0FB 14 8 I/O General-purpose digital I/O / analog input A0− / OA0 feedback input P6.2/A1+/OA1O 15 9 I/O General-purpose digital I/O / analog input A1+ / OA1 output P6.3/A1−/OA1FB 16 10 I/O General-purpose digital I/O / analog input A1− / OA1 feedback input P6.4/OA0I1 17 11 I/O General-purpose digital I/O / OA0 input multiplexer on −terminal P6.5/OA0I2 18 12 I/O General-purpose digital I/O / OA0 input multiplexer on −terminal P6.6/OA1I1 19 13 I/O General-purpose digital I/O / OA1 input multiplexer on −terminal P6.7/OA1I2 20 14 I/O General-purpose digital I/O / OA1 input multiplexer on −terminal P1.7/A2+ 21 15 I/O General-purpose digital I/O / analog input A2+ P1.6/A2−/OA0I0 22 16 I/O General-purpose digital I/O / analog input A2− / OA0 input multiplexer on +terminal

P1.5/TACLK/ACLK/A3+ 23 17 I/O

P1.4/A3−/OA1I0/DAC0 24 18 I/O

P1.3/TA2/A4+ 25 19 I/O

P1.2/TA1/A4− 26 20 I/O

P1.1/TA0/MCLK 27 21 I/O

P1.0/TA0 28 22 I/O

LCDREF/R13 29 23 External LCD reference voltage input / input port of third most positive analog LCD level (V4

LCDCAP/R23 30 24 Capacitor connection for LCD charge pump /

P5.1/S0 31 25 I/O General-purpose digital I/O / LCD segment output 0 P5.0/S1 32 26 I/O General-purpose digital I/O / LCD segment output 1 P5.5/S2 33 27 I/O General-purpose digital I/O / LCD segment output 2 P5.6/S3 34 28 I/O General-purpose digital I/O / LCD segment output 3 P5.7/S4 35 29 I/O General-purpose digital I/O / LCD segment output 4 S5 36 30 O LCD segment output 5 P2.7/S6 37 31 I/O General-purpose digital I/O / LCD segment output 6 P2.6/S7 38 32 I/O General-purpose digital I/O / LCD segment output 7

RGZ

NO.

I/O

General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) / analog input A3+

General-purpose digital I/O / analog input A3− / OA1 input multiplexer on +terminal / DAC12 output

General-purpose digital I/O / Timer_A, Capture: CCI2A, compare: Out2 output / analog input A4+

General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output / analog input A4−

General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this pin / BSL Receive

General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit

or V3)

input port of second most positive analog LCD level (V2)

NO.

6 48 Digital supply voltage, positive terminal 7 1 Digital supply voltage, negative terminal

10 4 Analog supply voltage, negative terminal 11 5 Analog supply voltage, positive terminal 12 6 I/O Analog reference voltage

DESCRIPTION

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Terminal Functions (Continued)

TERMINAL

NAME DL

P2.5/S8 39 33 I/O General-purpose digital I/O / LCD segment output 8 P2.4/S9 40 34 I/O General-purpose digital I/O / LCD segment output 9 P2.3/S10 41 35 I/O General-purpose digital I/O / LCD segment output 10 P2.2/S11 42 36 I/O General-purpose digital I/O / LCD segment output 11 P2.1/S12/SW1C 43 37 I/O General-purpose digital I/O / LCD segment output 12 / Low resistance switch to V P2.0/S13/SW0C 44 38 I/O General-purpose digital I/O / LCD segment output 13 / Low resistance switch to V COM0 45 39 O Common output. COM0−COM3 are used for LCD backplanes. P5.2/COM1 46 40 I/O General-purpose digital I/O / common output. COM0−COM3 are used for LCD backplanes. P5.3/COM2 47 41 I/O General-purpose digital I/O / common output. COM0−COM3 are used for LCD backplanes. P5.4/COM3 48 42 I/O General-purpose digital I/O / common output. COM0−COM3 are used for LCD backplanes. QFN Pad NA None NA QFN package pad connection to DVSS is recommended.

NO.

RGZ

NO.

I/O

DESCRIPTION

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short-form description

CPU

MSP430FG42x0

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats. Table 2 lists the address modes.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV & MEM, & TCDAT M(MEM) —> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6) Indirect

autoincrement

Immediate F MOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source D = destination

F MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 —> R11

M(R10) —> R11 R10 + 2—> R10

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operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

− All clocks are active

D Low-power mode 0 (LPM0)

− CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control remains active

D Low-power mode 1 (LPM1)

− CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

− CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator remains enabled ACLK remains active

D Low-power mode 3 (LPM3)

− CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled ACLK remains active

D Low-power mode 4 (LPM4)

− CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

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interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 3. Interrupt Sources, Flags, and Vectors of MSP430FG42x0 Configuration

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

Power-Up

External Reset

Watchdog

Flash Memory

PC Out-of-Range (see Note 4)

NMI

Oscillator Fault

Flash Memory Access Violation

SD16_A

Watchdog Timer WDTIFG Maskable 0FFF4h 10

Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 6

Timer_A3

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4

DAC12 DAC12_0IFG

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1

Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from within unused address ranges (MSP430FG4270, MSP430FG4260: from 0300h to 0BFFh and from 01100h to 07FFFh, MSP430FG4250: from 0300h to 0BFFh and from 01100h to 0BFFFh).

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1 and 3)

SD16CCTLx SD16OVIFG,

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

WDTIFG

KEYV

(see Note 1)

SD16CCTLx SD16IFG

(see Notes 1 and 2)

(see Note 2)

Reset 0FFFEh 15, highest

(Non)maskable (Non)maskable (Non)maskable

Maskable 0FFF8h 12

Maskable 0FFEAh 5

Maskable 0FFE6h 3

WORD

ADDRESS

0FFFCh 14

0FFFAh 13

0FFF6h 11

0FFF2h 9 0FFF0h 8 0FFEEh 7

0FFE4h 2

PRIORITY

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special function registers (SFRs)

The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers. SFRs should be accessed with byte instructions.

interrupt enable registers 1 and 2

Address 0h ACCVIE NMIIE

7654 0

rw–0

rw–0 rw–0 rw–0

321

WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.

Active if watchdog timer is configured as a general-purpose timer. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable

Address 01h

7654 0321

BTIE

rw–0

BTIE: Basic timer interrupt enable

interrupt flag registers 1 and 2

Address 02h NMIIFG

7654 0

rw–0 rw–1 rw–(0)

WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation

Reset on V

power-on or a reset condition at the RST/NMI pin in reset mode

OFIFG: Flag set on oscillator fault NMIIFG: Set via RST

/NMI pin

321

OFIE WDTIE

OFIFG WDTIFG

Address 03h

7654 0321

BTIFG

rw–0

BTIFG: Basic timer flag

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module enable registers 1 and 2

MSP430FG42x0

MIXED SIGNAL MICROCONTROLLER

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Address 04h

Address 05h

Legend: rw:

rw–0,1: rw–(0,1):

7654 0321

Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device

memory organization

MSP430FG4250 MSP430FG4260 MSP430FG4270

Memory Main: interrupt vector Main: code memory

Information memory Size

Boot memory Size

RAM Size 256 Byte

Peripherals 16-bit

Size Flash Flash

Flash

ROM

8-bit

8-bit SFR

16KB 0FFFFh − 0FFE0h 0FFFFh − 0C000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

02FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

24KB 0FFFFh − 0FFE0h 0FFFFh − 0A000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

256 Byte

02FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

32KB 0FFFFh − 0FFE0h 0FFFFh − 08000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

256 Byte

02FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089.

BSL Function DL Package Pins RGZ Package Pins

Data Transmit 28 - P1.0 22 - P1.0 Data Receive 27 - P1.1 21 - P1.1

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flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B) of

128 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0 to n.

Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

16KB

24KB

32KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

0C400h

0C3FFh

0C200h

0C1FFh

0C000h 010FFh

01080h 0107Fh

01000h

0FFFFh

0FE00h 0FDFFh

0FC00h 0FBFFh

0FA00h 0F9FFh

0A400h 0A3FFh

0A200h 0A1FFh

0A000h 010FFh

01080h

0107Fh

01000h

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

08400h 083FFh

08200h 081FFh

08000h 010FFh

01080h 0107Fh

01000h

Segment 0

w/ Interrupt Vectors

Segment 1

Segment 2

Main Memory

Segment n-1

Segment n

Segment A

Information Memory

Segment B

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peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430FG42x0 family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal D Main clock (MCLK), the system clock used by the CPU D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The CPU begins code execution after the brownout circuit releases the device reset. However, V

may not have ramped to V

changed until V

reaches V

CC(min)

at that time. The user must ensure the default FLL+ settings are not

CC(min)

digital I/O

There are four 8-bit I/O ports implemented—ports P1, P2, P5, and P6:

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions.

Basic Timer1

Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 can be used to generate periodic interrupts.

LCD driver with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2−MUX, 3−MUX, and 4−MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore, it is possible to control the level of the LCD voltage and thus contrast in software.

watchdog timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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MSP430FG42x0

Device Input

Module

Module Output

Block

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer_A3 Signal Connections

Input Pin Number

DL RGZ

23 - P1.5 17 - P1.5 TACLK TACLK

23 - P1.5 17 - P1.5 TACLK INCLK 28 - P1.0 22 - P1.0 TA0 CCI0A 27 - P1.1 21 - P1.1 TA0 CCI0B

26 - P1.2 20 - P1.2 TA1 CCI1A 26 - P1.2 20 - P1.2 TA1 CCI1B

25 - P1.3 19 - P1.3 TA2 CCI2A

Device Input Module Module Module Output

gna

ACLK ACLK

SMCLK SMCLK

ACLK (internal) CCI2B

nput Name

GND

gna

Timer NA

CCR0 TA0

CCR1 TA1

CCR2 TA2

Output Pin Number

DL RGZ

28 - P1.0 22 - P1.0

26 - P1.2 20 - P1.2

25 - P1.3 19 - P1.3

SD16_A

The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta core and reference generator. In addition to external analog inputs, an internal V

temperature sensor are also available.

DAC12

The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode.

sense and

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MSP430FG42x0

Device Input

Module

Module Output

Block

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

operational amplifier (OA)

The MSP430FG42x0 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offers a flexible choice of connections for various applications. The OAs primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

OA Signal Connections

Input Pin Number

DL RGZ

22 - P1.6 16 - P1.6 OA0I0 OA0I0 17 - P6.4 11 - P6.4 OA0I1 OA0I1 18 - P6.5 12 - P6.5 OA0I2 OA0I2 14 - P6.1 8 - P6.1 OA0FB OA0FB 24 - P1.4 18 - P1.4 OA1I0 OA1I0 19 - P6.6 13 - P6.6 OA1I1 OA1I1 20 - P6.7 14 - P6.7 OA1I2 OA1I2 16 - P6.1 10 - P6.1 OA1FB OA1FB

Device Input Module Module Module Output

gna

nput Name

gna

OA0 OA0O

OA1 OA1O

Output Pin Number

DL RGZ

13 - P6.0 7 - P6.0

15 - P6.0 9 - P6.0

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MSP430FG42x0 MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

peripheral file map

PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Timer_A3

Flash

DAC12

SD16_A (see also Peripherals With Byte Access)

OA/GND Switches Switch control register SWCTL 0CFh OA1 Operational amplifier 1 control register 1

OA0 Operational amplifier 0 control register 1

SD16_A (see also: Peripherals with Word Access)

LCD_A LCD voltage control 1

Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h DAC12_0 data DAC12_0DAT 01C8h DAC12_0 control DAC12_0CTL 01C0h General control

Channel 0 control Interrupt vector word register Channel 0 conversion memory

PERIPHERALS WITH BYTE ACCESS

Operational amplifier 1 control register 0

Operational amplifier 0 control register 0 Channel 0 input control

Analog enable

LCD voltage control 0 LCD voltage port control 1 LCD voltage port control 0 LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode

SD16CTL SD16CCTL0 SD16IV SD16MEM0

OA1CTL1 OA1CTL0

OA0CTL1 OA0CTL0

SD16INCTL0 SD16AE

LCDAVCTL1 LCDAVCTL0 LCDAPCTL1 LCDAPCTL0 LCDM20 : LCDM16 LCDM15 : LCDM1 LCDACTL

0100h 0102h 0110h 0112h

0C3h 0C2h

0C1h 0C0h

0B0h 0B7h

0AFh 0AEh 0ADh 0ACh 0A4h : 0A0h 09Fh : 091h 090h

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peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

FLL+ Clock

Basic Timer1 BT counter 2

Port P6

Port P5

Port P2

Port P1

Special functions

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

FLL+ Control 1 FLL_CTL1 054h FLL+ Control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h

BTCNT2 BT counter 1 BT control

Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

BTCNT1

BTCTL

047h 046h 040h

MSP430FG42x0

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MSP430FG42x0

(see Note 2)

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (see Note 1) −0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T

: Unprogrammed device −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Programmed device −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages referenced to V

applied to the TDI/TCLK pin when blowing the JTAG fuse.

The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

SS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage during program execution (see Note 1), V

(AVCC = DVCC = VCC)

Supply voltage during flash memory programming (see Note 1), V

(AVCC = DVCC = VCC)

Supply voltage, V Operating free-air temperature, T

LFXT1 crystal frequency, f (see Note 2)

Processor frequency (signal MCLK), f

NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can

2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(AVSS = DVSS = VSS) 0 0 V

LF selected, XTS_FLL=0

(LFXT1)

(System)

be tolerated during power up and operation.

XT1 selected, XTS_FLL=1

Watch crystal 32.768

Ceramic resonator 450 8000

Crystal 1000 8000

VCC = 1.8 V DC 4.15 VCC = 3.6 V DC 8

1.8 3.6 V

2.5 3.6 V

−40 85 °C

kHz

MHz

(MHz)

System

8 MHz

4.15 MHz

Supply voltage range, MSP430FG42x0, during program execution

1.8 3.63

2.5

Supply Voltage − V

Supply voltage range, MSP430FG42x0, during flash memory programming

Figure 1. Frequency vs Supply Voltage, Typical Characteristic

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MSP430FG42x0

(MCLK)

(SMCLK)

MHz

Low power mode (LPM0)

(MCLK)

(SMCLK)

MHz

Low-power mode (LPM3)

(MCLK)

(SMCLK)

MHz,

LCD_A enabled, LCDCPEN = 0

LCD (ACLK)

Low-power mode (LPM3)

(MCLK)

(SMCLK)

MHz,

2.2 V

LCD_A enabled, LCDCPEN = 0

LCD (ACLK)

(LPM4)

(MCLK)

MHz, f

(SMCLK)

MHz

(ACLK)

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

supply current into AVCC + DVCC excluding external current

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Active mode (see Note 1),

(AM)

(ACLK)

= f

= 32,768 Hz

= 1 MHz,

= 1

XTS=0, SELM=(0,1)

(LPM0)

Low-power mode (LPM0) (see Note 1 and Note 4)

Low-power mode (LPM2),

(LPM2)

= f

= 32,768 Hz, SCG0 = 0

(ACLK)

= 0 MHz,

= 0

(see Note 2 and Note 4)

(LPM3)

= f

(MCLK)

= 32,768 Hz, SCG0 = 1

(ACLK)

Basic Timer1 enabled, ACLK selected LCD A enabled (static mode, f

(SMCLK)

LCDCPEN = 0

LCD

= 0 MHz,

= f

(ACLK)

(see Note 2, Note 3, and Note 4)

(LPM3)

= f

(MCLK)

= 32,768 Hz, SCG0 = 1

(ACLK)

Basic Timer1 enabled, ACLK selected LCD A enabled (4-mux mode, f

(SMCLK)

LCDCPEN = 0

LCD

= 0 MHz,

= f

(ACLK)

(see Note 2, Note 3, and Note 4)

ow-power mode

= 0 MHz, f

(LPM4)

= 0

= 0 Hz, SCG0 = 1

(ACLK)

(see Note 2 and Note 4)

NOTES: 1. Timer_A is clocked by f

2. All inputs are tied to 0 V or to V

3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 01h.

4. Current for brownout included.

/32),

= 0 MHz,

= 0

(DCOCLK)

= −40°C to 85°C

TA = −40°C 1.0 2.0 TA = 25°C T

= 60°C

TA = 85°C 3.5 6.0

= −40°C 1.8 2.8

= 25°C

= 60°C

TA = 85°C 4.2 7.5 TA = −40°C 2.5 3.5 T

= 25°C

TA = 85°C

= −40°C 2.9 4.0

= 25°C

= 85°C

TA = −40°C 0.1 0.5 TA = 25°C TA = 60°C T

= 85°C 1.7 3.0

TA = −40°C 0.1 0.8 T

= 25°C

TA = 60°C TA = 85°C 1.9 3.5

= f

= 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(DCO)

. Outputs do not source or sink any current.

VCC = 2.2 V 250 370

VCC = 3 V 400 520

VCC = 2.2 V 55 70 VCC = 3 V 95 110

VCC = 2.2 V 11 14

VCC = 3 V 17 22

VCC = 2.2 V

VCC = 3 V

VCC = 2.2 V

1.1 2.0

2.0 3.0

1.6 2.7

2.5 3.5

3.8 6.0

VCC = 3 V

2.9 4.0

4.4 7.5

VCC = 2.2 V

VCC = 3 V

0.1 0.5

0.7 1.1

0.1 0.8

0.8 1.2

μA

current consumption of active mode versus system frequency

current consumption of active mode versus supply voltage

(AM)

= I

(AM)

= I

(AM) [3 V]

[1 MHz] × f

(System)

+ 175 μA/V × (VCC – 3 V)

[MHz]

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MSP430FG42x0

Port P1, P2: P1.x to P2.x, external trigger signal

Timer_A clock frequency

MIXED SIGNAL MICROCONTROLLER

SLAS556A − JULY 2007 − REVISED AUGUST 2007

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IT+

IT−

hys

Positive-going input threshold voltage

Negative-going input threshold voltage

Input voltage hysteresis (V

IT+

− V

IT−

)

inputs Px.x, TAx

PARAMETER TEST CONDITIONS V

(int)

(cap)

(TAext)

(TAint)

External interrupt timing

Timer_A capture timing TA0, TA1, TA2

Timer_A clock frequenc externally applied to pin

Timer_A clock frequency SMCLK or ACLK signal selected

Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag, (see Note 1)

TACLK, INCLK:

= t

(H)

(L)

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

shorter than t

(int)

leakage current − ports P1, P2, P5, and P6 (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

lkg(Px.y)

NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

Leakage current

Port Px V

(see Note 2) VCC = 2.2 V/3 V ±50 nA

(Px.y)

2. The port pin must be selected as input.

VCC = 2.2 V 1.1 1.55

= 3 V 1.5 1.98

VCC = 2.2 V 0.4 0.9

= 3 V 0.9 1.3

VCC = 2.2 V 0.3 1.1 VCC = 3 V 0.5 1

MIN TYP MAX UNIT

2.2 V 62 3 V 50

2.2 V 8 3 V 10

parameters are met. It may be set even with trigger signals

(int)

MHz

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