Texas Instruments MSP430F5632, MSP430F5635, MSP430F5638, MSP430F5631, MSP430F5630 User Manual

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Mixed Signal Microcontroller

Check for

Samples: MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635, MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631,

1

FEATURES

23

• Low Supply Voltage Range: 1.8 V to 3.6 V

• Ultralow-Power Consumption
– Active Mode (AM):

All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support:
Execution (Typical)

– Standby Mode (LPM3): Baudrate Detection

Watchdog With Crystal and Supply
Supervisor Operational, Full RAM
Retention, Fast Wake-Up:

1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)

– Shutdown RTC Mode (LPM3.5):

Shutdown Mode, Active Real-Time Clock
With Crystal: • Full-Speed Universal Serial Bus (USB)

1.1 µA at 3.0 V (Typical)

– Shutdown Mode (LPM4.5):

0.3 µA at 3.0 V (Typical)

• Wake Up From Standby Mode in 3 µs (Typical)

• 16-Bit RISC Architecture, Extended Memory,
Up to 20-MHz System Clock

• Flexible Power Management System
– Fully Integrated LDO With Programmable and Autoscan Feature

Regulated Core Supply Voltage

– Supply Voltage Supervision, Monitoring, (DACs) With Synchronization

and Brownout

• Unified Clock System
– FLL Control Loop for Frequency Operations

Stabilization

– Low-Power Low-Frequency Internal Clock Programming Voltage Needed

Source (VLO)

– Low-Frequency Trimmed Internal Reference

Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals Up to 32 MHz

(XT2)

MSP430F5630

• Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers

• Two Universal Serial Communication
Interfaces

– Enhanced UART Supports Auto-

– IrDA Encoder and Decoder
– Synchronous SPI

– USCI_B0 and USCI_B1 Each Support:

– I2C
– Synchronous SPI

– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB Power

System
– Integrated USB-PLL
– Eight Input and Eight Output Endpoints

• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Shared Reference, Sample-and-Hold,

• Dual 12-Bit Digital-to-Analog Converters

• Voltage Comparator

• Hardware Multiplier Supporting 32-Bit

• Serial Onboard Programming, No External

• Six-Channel Internal DMA

• Real-Time Clock Module With Supply Voltage
Backup Switch

• Family Members are Summarized in Table 1

• For Complete Module Descriptions, See the

MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.
3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2010–2013, Texas Instruments Incorporated

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

APPLICATIONS

• Analog and Digital Sensor Systems

• Digital Motor Control

• Remote Controls

• Thermostats

• Digital Timers

• Hand-Held Meters

DESCRIPTION

The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in
3 µs (typical).

The MSP430F563x series are microcontroller configurations with a high-performance 12-bit analog-to-digital
converter (ADC), comparator, two universal serial communication interfaces (USCIs), USB 2.0, a hardware
multiplier, DMA, four 16-bit timers, a real-time clock module with alarm capabilities, and up to 74 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, and hand-held meters.

Table 1 summarizes the available family members.

www.ti.com

SPI, I2C

(1)(2)

(Ch) (Ch) (Ch) Type

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

12 ext, 100 PZ,

4 int 113 ZQW

I/O

100 PZ,

113 ZQW

100 PZ,

113 ZQW

100 PZ,

113 ZQW

Table 1. Family Members

USCI

Device Timer_A

MSP430F5638 256 16 + 2 5, 3, 3 7 2 2 2 12 74

MSP430F5637 192 16 + 2 5, 3, 3 7 2 2 2 12 74

MSP430F5636 128 16 + 2 5, 3, 3 7 2 2 2 12 74

MSP430F5635 256 16 + 2 5, 3, 3 7 2 2 - 12 74

MSP430F5634 192 16 + 2 5, 3, 3 7 2 2 - 12 74

MSP430F5633 128 16 + 2 5, 3, 3 7 2 2 - 12 74

MSP430F5632 256 16 + 2 5, 3, 3 7 2 2 - - 12 74

MSP430F5631 192 16 + 2 5, 3, 3 7 2 2 - - 12 74

MSP430F5630 128 16 + 2 5, 3, 3 7 2 2 - - 12 74

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at http://www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

http://www.ti.com/packaging.

(3) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

Flash SRAM ADC12_A DAC12_A Comp_B Package

(KB) (KB)

(3)

(4)

Timer_B

(5)

Channel A: Channel B:

UART,

IrDA, SPI

2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

Unified

Clock

System

256KB
192KB
128KB

Flash

16KB

RAM

+2KBRAM
USBBuffer

+8BBackup

RAM

MCLK

ACLK

SMCLK

I/OPorts

P1/P2

2×8I/Os

Interrupt

Capability

PA

1×16I/Os

CPUXV2

and

Working

Registers

EEM

(L:8+2)

XIN

XOUT

JTAG/

Interface/

PortPJ

SBW

PA PB PC PD

DMA

6Channel

XT2IN

XT OUT2

Power

Management

LDO
SVM/
Brownout

SVS

SYS

Watchdog

P2Port

Mapping

Controller

I/OPorts

P3/P4

2×8I/Os

Interrupt

Capability

PB

1×16I/Os

I/OPorts

P5/P6

2×8I/Os

PC

1×16I/Os

I/OPorts

P7/P8

1×6I/Os

PD

1×14I/Os

1×8I/Os

I/OPorts

P9

1×8I/Os

PE

1×8I/Os

MPY32

TA0

Timer_A

5CC

Registers

TA1and

TA2

2Timer_A

eachwith

3CC

Registers

TB0

Timer_B

7CC

Registers

CRC16

USCI0,1

Ax:UART,

IrDA,SPI

Bx:SPI,I2C

ADC12_A

200KSPS

16Channels
(12ext/4int)

Autoscan

12Bit

DVCCDVSSAVCCAV

SS

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V,2.0V,

2.5V

USB

Full-speed

Comp_B

PJ.x

RTC_B

Battery
Backup
System

Unified

Clock

System

256KB
192KB
128KB

Flash

MCLK

ACLK

SMCLK

I/OPorts

P1/P2

2×8I/Os

Interrupt

Capability

PA

1×16I/Os

CPUXV2

and

Working

Registers

EEM

(L:8+2)

XIN

XOUT

JTAG/

Interface/

PortPJ

SBW

PA PB PC PD

DMA

6Channel

XT2IN

XT OUT2

Power

Management

LDO
SVM/
Brownout

SVS

SYS

Watchdog

P2Port

Mapping

Controller

I/OPorts

P3/P4

2×8I/Os

Interrupt

Capability

PB

1×16I/Os

I/OPorts

P5/P6

2×8I/Os

PC

1×16I/Os

I/OPorts

P7/P8

1×6I/Os

PD

1×14I/Os

1×8I/Os

I/OPorts

P9

1×8I/Os

PE

1×8I/Os

MPY32

TA0

Timer_A

5CC

Registers

TA1and

TA2

2Timer_A

eachwith

3CC

Registers

TB0

Timer_B

7CC

Registers

RTC_B

Battery
Backup
System

CRC16

USCI0,1

Ax:UART,

IrDA,SPI

Bx:SPI,I2C

ADC12_A

200KSPS

16Channels
(12ext/4int)

Autoscan

12Bit

DVCCDVSSAVCCAV

SS

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V,2.0V,

2.5V

DAC12_A

12bit
2channels
voltageout

USB

Full-speed

Comp_B

PJ.x

16KB

RAM

+2KBRAM
USBBuffer

+8BBackup

RAM

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Functional Block Diagram, MSP430F5638, MSP430F5637, MSP430F5636

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Functional Block Diagram, MSP430F5635, MSP430F5634, MSP430F5633

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

Unified

Clock

System

256KB
192KB
128KB

Flash

MCLK

ACLK

SMCLK

I/OPorts

P1/P2

2×8I/Os

Interrupt

Capability

PA

1×16I/Os

CPUXV2

and

Working

Registers

EEM

(L:8+2)

XIN

XOUT

JTAG/

Interface/

PortPJ

SBW

PA PB PC PD

DMA

6Channel

XT2IN

XT OUT2

Power

Management

LDO
SVM/
Brownout

SVS

SYS

Watchdog

P2Port

Mapping

Controller

I/OPorts

P3/P4

2×8I/Os

Interrupt

Capability

PB

1×16I/Os

I/OPorts

P5/P6

2×8I/Os

PC

1×16I/Os

I/OPorts

P7/P8

1×6I/Os

PD

1×14I/Os

1×8I/Os

I/OPorts

P9

1×8I/Os

PE

1×8I/Os

MPY32

TA0

Timer_A

5CC

Registers

TA1and

TA2

2Timer_A

eachwith

3CC

Registers

TB0

Timer_B

7CC

Registers

CRC16

USCI0,1

Ax:UART,

IrDA,SPI

Bx:SPI,I2C

DVCCDVSSAVCCAV

SS

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V,2.0V,

2.5V

USB

Full-speed

Comp_B

PJ.x

RTC_B

Battery
Backup
System

16KB

RAM

+2KBRAM
USBBuffer

+8BBackup

RAM

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Functional Block Diagram, MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P6.4/CB4/A4

P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1

P7.4/CB8/A12
P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2

P2.0/P2MAP0

MSP430F5638
MSP430F5637
MSP430F5636

PZPACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2
P4.1/TB0.1

P4.4/TB0.4
P4.3/TB0.3

P4.6/TB0.6
P4.5/TB0.5

P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Pin Designation, MSP430F5638IPZ, MSP430F5637IPZ, MSP430F5636IPZ

SLAS650D –JUNE 2010–REVISED AUGUST 2013

NOTE: DNC = Do not connect

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12
P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2

P2.0/P2MAP0

MSP430F5635
MSP430F5634
MSP430F5633

PZPACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2
P4.1/TB0.1

P4.4/TB0.4
P4.3/TB0.3

P4.6/TB0.6
P4.5/TB0.5

P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Pin Designation, MSP430F5635IPZ, MSP430F5634IPZ, MSP430F5633IPZ

www.ti.com

NOTE: DNC = Do not connect

6 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P7.4/CB8
P7.5/CB9

P7.6/CB10

P7.7/CB11
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2

P2.0/P2MAP0

MSP430F5632
MSP430F5631
MSP430F5630

PZPACKAGE

(TOP VIEW)

P6.3/CB3

P6.2/CB2

P6.1/CB1

P6.0/CB0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2
P4.1/TB0.1

P4.4/TB0.4
P4.3/TB0.3

P4.6/TB0.6
P4.5/TB0.5

P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Pin Designation, MSP430F5632IPZ, MSP430F5631IPZ, MSP430F5630IPZ

SLAS650D –JUNE 2010–REVISED AUGUST 2013

NOTE: DNC = Do not connect

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

A1 A2

A3

A4

A5 A6

A7

A8 A9 A10

A11 A12

B1 B2

B3

B4

B5 B6

B7

B8 B9 B10

B11 B12

C1 C2 C3 C11 C12

D1 D2 D4

D5 D6

D7

D8 D9

D11 D12

E1 E2 E4

E5 E6

E7

E8 E9

E11 E12

F1 F2 F4

F5 F8 F9

F11 F12

G1 G2 G4

G5 G8 G9

G11 G12

J1 J2 J4

J5 J6

J7

J8 J9

J11 J12

H1 H2 H4

H5 H6

H7

H8 H9

H11 H12

K1 K2 K11 K12

L1 L2

L3

L4

L5 L6

L7

L8 L9 L10

L11 L12

M1 M2

M3 M5 M6

M7

M8 M9 M10

M11 M12

M4

ZQWPACKAGE

(TOP VIEW)

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Pin Designation, MSP430F5638IZQW, MSP430F5637IZQW, MSP430F5636IZQW,
MSP430F5635IZQW, MSP430F5634IZQW, MSP430F5633IZQW, MSP430F5632IZQW,
MSP430F5631IZQW, MSP430F5630IZQW

www.ti.com

NOTE: For terminal assignments, see Table 2

8 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Table 2. Terminal Functions

TERMINAL

NAME

P6.4/CB4/A4 1 A1 I/O

P6.5/CB5/A5 2 B2 I/O

P6.6/CB6/A6/DAC0 3 B1 I/O

P6.7/CB7/A7/DAC1 4 C2 I/O

P7.4/CB8/A12 5 C1 I/O

P7.5/CB9/A13 6 C3 I/O

P7.6/CB10/A14/DAC0 7 D2 I/O

P7.7/CB11/A15/DAC1 8 D1 I/O

P5.0/VREF+/VeREF+ 9 D4 I/O

P5.1/VREF-/VeREF- 10 E4 I/O

AVCC1 11 Analog power supply
AVSS1 12 F2 Analog ground supply

XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1
AVSS2 15 G2 Analog ground supply

NO. I/O

PZ ZQW

E1,

E2

(1)

General-purpose digital I/O
Comparator_B input CB4
Analog input A4 – ADC(not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB5
Analog input A5 – ADC(not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB6
Analog input A6 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)
General-purpose digital I/O

Comparator_B input CB7
Analog input A7 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)
General-purpose digital I/O

Comparator_B input CB8
Analog input A12 –ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB9
Analog input A13 – ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB10
Analog input A14 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)
General-purpose digital I/O

Comparator_B input CB11
Analog input A15 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)
General-purpose digital I/O

Output of reference voltage to the ADC
Input for an external reference voltage to the ADC

General-purpose digital I/O
Negative terminal for the ADC's reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

DESCRIPTION

SLAS650D –JUNE 2010–REVISED AUGUST 2013

(1) I = input, O = output, N/A = not available on this package offering

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 2. Terminal Functions (continued)

TERMINAL

NAME

P5.6/ADC12CLK/DMAE0 16 H1 I/O

P2.0/P2MAP0 17 G4 I/O

P2.1/P2MAP1 18 H2 I/O

P2.2/P2MAP2 19 J1 I/O

P2.3/P2MAP3 20 H4 I/O

P2.4/P2MAP4 21 J2 I/O

P2.5/P2MAP5 22 K1 I/O

P2.6/P2MAP6 23 K2 I/O

P2.7/P2MAP7 24 L2 I/O

DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply

(2)

VCORE
P5.2 28 L3 I/O
DVSS 29 M3 Digital ground supply

DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open.
P5.3 31 L4 I/O

P5.4 32 M4 I/O
P5.5 33 J5 I/O

P1.0/TA0CLK/ACLK 34 L5 I/O

P1.1/TA0.0 35 M5 I/O

P1.2/TA0.1 36 J6 I/O

P1.3/TA0.2 37 H6 I/O

P1.4/TA0.3 38 M6 I/O

NO. I/O

PZ ZQW

27 M2 Regulated core power supply (internal use only, no external current loading)

(1)

General-purpose digital I/O
Conversion clock output ADC (not available on F5632, F5631, F5630 devices)
DMA external trigger input

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function

General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function

General-purpose digital I/O

General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O with port interrupt

Timer TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output

General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input

General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

DESCRIPTION

www.ti.com

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

VCORE

.

MSP430F5632 MSP430F5631 MSP430F5630

www.ti.com

Table 2. Terminal Functions (continued)

TERMINAL

NAME

P1.5/TA0.4 39 L6 I/O

P1.6/TA0.1 40 J7 I/O

P1.7/TA0.2 41 M7 I/O

P3.0/TA1CLK/CBOUT 42 L7 I/O

P3.1/TA1.0 43 H7 I/O

P3.2/TA1.1 44 M8 I/O

P3.3/TA1.2 45 L8 I/O

P3.4/TA2CLK/SMCLK 46 J8 I/O

P3.5/TA2.0 47 M9 I/O

P3.6/TA2.1 48 L9 I/O

P3.7/TA2.2 49 M10 I/O

P4.0/TB0.0 50 J9 I/O

P4.1/TB0.1 51 M11 I/O

P4.2/TB0.2 52 L10 I/O

P4.3/TB0.3 53 M12 I/O

P4.4/TB0.4 54 L12 I/O

P4.5/TB0.5 55 L11 I/O

P4.6/TB0.6 56 K11 I/O

P4.7/TB0OUTH/SVMOUT 57 K12 I/O

P8.0/TB0CLK 58 J11 I/O

NO. I/O

PZ ZQW

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

(1)

General-purpose digital I/O with port interrupt
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt
Timer TA1 clock input
Comparator_B output

General-purpose digital I/O with port interrupt
Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

General-purpose digital I/O with port interrupt
Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt
Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt
Timer TA2 clock input
SMCLK output

General-purpose digital I/O with port interrupt
Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

General-purpose digital I/O with port interrupt
Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt
Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

General-purpose digital I/O with port interrupt
Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance
SVM output

General-purpose digital I/O
Timer TB0 clock input

DESCRIPTION

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 2. Terminal Functions (continued)

TERMINAL

NAME

P8.1/UCB1STE/UCA1CLK 59 J12 I/O

P8.2/UCA1TXD/UCA1SIMO 60 H11 I/O

P8.3/UCA1RXD/UCA1SOMI 61 H12 I/O

P8.4/UCB1CLK/UCA1STE 62 G11 I/O

DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply

P8.5/UCB1SIMO/UCB1SDA 65 F11 I/O

P8.6/UCB1SOMI/UCB1SCL 66 G9 I/O

P8.7 67 E12 I/O
P9.0 68 E11 I/O
P9.1 69 F9 I/O
P9.2 70 D12 I/O
P9.3 71 D11 I/O
P9.4 72 E9 I/O
P9.5 73 C12 I/O
P9.6 74 C11 I/O
P9.7 75 D9 I/O

VSSU 76 and USB PHY ground supply

PU.0/DP 77 A12 I/O

PUR 78 B10 I/O invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See USB

PU.1/DM 79 A11 I/O

VBUS 80 A10 USB LDO input (connect to USB power source)
VUSB 81 A9 USB LDO output
V18 82 B9 USB regulated power (internal use only, no external current loading)
AVSS3 83 A8 Analog ground supply

P7.2/XT2IN 84 B8 I/O

P7.3/XT2OUT 85 B7 I/O

VBAK 86 A7

NO. I/O

PZ ZQW

B11
B12

(1)

General-purpose digital I/O
USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output

General-purpose digital I/O
USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

General-purpose digital I/O
USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

General-purpose digital I/O
USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable

General-purpose digital I/O
USCI_B1 SPI slave in/master out; USCI_B1 I2C data

General-purpose digital I/O
USCI_B1 SPI slave out/master in; USCI_B1 I2C clock

General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O

General-purpose digital I/O - controlled by USB control register
USB data terminal DP

USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to

BSL for more information.

General-purpose digital I/O - controlled by USB control register
USB data terminal DM

General-purpose digital I/O
Input terminal for crystal oscillator XT2

General-purpose digital I/O
Output terminal of crystal oscillator XT2

Capacitor for backup subsystem. Do not load this pin externally. For capacitor
values, see C

in Recommended Operating Conditions.

BAK

DESCRIPTION

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Table 2. Terminal Functions (continued)

TERMINAL

NAME

VBAT 87 D8

P5.7/RTCCLK 88 D7 I/O

DVCC3 89 A6 Digital power supply
DVSS3 90 A5 Digital ground supply

TEST/SBWTCK 91 B6 I

PJ.0/TDO 92 B5 I/O

PJ.1/TDI/TCLK 93 A4 I/O

PJ.2/TMS 94 E7 I/O

PJ.3/TCK 95 D6 I/O

RST/NMI/SBWTDIO 96 A3 I/O

P6.0/CB0/A0 97 B4 I/O

P6.1/CB1/A1 98 B3 I/O

P6.2/CB2/A2 99 A2 I/O

P6.3/CB3/A3 100 D5 I/O

Reserved N/A F8, Reserved. It is recommended to connect to ground (DVSS, AVSS).

(3) When this pin is configured as reset, the intermal pullup resistor is enabled by default.

NO. I/O

PZ ZQW

E5,
E6,
E8,
F4,
F5,

G5,
G8,
H5,
H8,

H9

(1)

Backup or secondary supply voltage. If backup voltage is not supplied, connect to
DVCC externally.

General-purpose digital I/O
RTCCLK output

Test mode pin; selects digital I/O on JTAG pins
Spy-bi-wire input clock

General-purpose digital I/O
Test data output port

General-purpose digital I/O
Test data input or test clock input

General-purpose digital I/O
Test mode select

General-purpose digital I/O
Test clock

Reset input (active low)
Non-maskable interrupt input
Spy-bi-wire data input/output

General-purpose digital I/O
Comparator_B input CB0
Analog input A0 – ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB1
Analog input A1 – ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB2
Analog input A2 – ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O
Comparator_B input CB3
Analog input A3 – ADC (not available on F5632, F5631, F5630 devices)

(3)

SLAS650D –JUNE 2010–REVISED AUGUST 2013

DESCRIPTION

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Development Tools Support

All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.

Hardware Features

See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.

www.ti.com

MSP430 4-Wire 2-Wire Clock State Trace

Architecture JTAG JTAG Control Sequencer Buffer

MSP430Xv2 Yes Yes 8 Yes Yes Yes Yes No

Break- Range LPMx.5

points Break- Debugging

(N) points Support

Recommended Hardware Options

Target Socket Boards

The target socket boards allow easy programming and debugging of the device using JTAG. They also feature
header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG
programmer and debugger included. The following table shows the compatible target boards and the supported
packages.

Package Target Board and Programmer Bundle Target Board Only

100-pin LQFP (PZ) MSP-FET430U100USB MSP-TS430PZ100USB

Experimenter Boards

Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional
hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools
for details.

Debugging and Programming Tools

Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full
list of available tools at www.ti.com/msp430tools.

Production Programmers

The production programmers expedite loading firmware to devices by programming several devices
simultaneously.

Part Number PC Port Features Provider

MSP-GANG Serial and USB Program up to eight devices at a time. Works with PC or standalone. Texas Instruments

Recommended Software Options

Integrated Development Environments

Software development tools are available from TI or from third parties. Open source solutions are also available.
This device is supported by Code Composer Studio™ IDE (CCS).

MSP430Ware

MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices

delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design
resources, MSP430Ware also includes a high-level API called MSP430 Driver Library. This library makes it easy
to program MSP430 hardware. MSP430Ware is available as a component of CCS or as a standalone package.

14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

TI-RTOS

TI-RTOS is a complete real-time operating system for the MSP430 microcontrollers. It combines a real-time

multitasking kernel SYS/BIOS with additional middleware components. TI-RTOS is available free of charge and
provided with full source code.

MSP430 USB Developer's Package

MSP430 USB Developer's Package is an easy-to-use USB stack implementation for the MSP430

microcontrollers.

Command-Line Programmer

MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a

FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to
download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.
TI E2E Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Device and Development Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of two
prefixes: MSP or XMS (for example, MSP430F5259). Texas Instruments recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product
development from engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified
production devices and tools (with MSP for devices and MSP for tools).

Device development evolutionary flow:

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device

Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification

testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of

the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

Processor Family

CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon

430 MCU Platform TI’s Low Power Microcontroller Platform

Device Type Memory Type

C = ROM
F = Flash
FR = FRAM
G = Flash (Value Line)
L = No Nonvolatile Memory

Specialized Application

AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter

Series 1 Series = Up to 8 MHz

2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz w/ LCD

5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series

Feature Set Various Levels of Integration Within a Series

Optional: A = Revision N/A

Optional: Temperature Range S = 0°C to 50 C

C to 70 C
I = -40 C to 85 C
T = -40 C to 105 C

°

C = 0° °

° °

° °

Packaging

www.ti.com/packaging

Optional: Tape and Reel T = Small Reel (7 inch)

R = Large Reel (11 inch)
No Markings = Tube or Tray

Optional: Additional Features *-EP = Enhanced Product (-40°C to 105°C)

*-HT = Extreme Temperature Parts (-55°C to 150°C)

MSP 430 F 5 438 A I ZQW T XX

Processor Family

Series

Optional: Temperature Range

430 MCU Platform

PackagingDevice Type

Optional: A = Revision

Optional: Tape and Reel

Feature Set

Optional: Additional Features

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZP) and temperature range (for example, T). Figure 1 provides a legend for reading the complete
device name for any family member.

Part Number Decoder

www.ti.com

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Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

Figure 1. Device Nomenclature

MSP430F5632 MSP430F5631 MSP430F5630

Program Counter

PC/R0

Stack Pointer SP/R1

Status Register

SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register

R4

General-Purpose Register

R5

General-Purpose Register

R6

General-Purpose Register

R7

General-Purpose Register

R8

General-Purpose Register

R9

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R15

General-Purpose Register

R14

www.ti.com

Short-Form Description

CPU

The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.

The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to­register operation execution time is one cycle of the
CPU clock.

Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.

Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Instruction Set

The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 3 shows examples of the three
types of instruction formats; Table 4 shows the
address modes.

INSTRUCTION WORD FORMAT EXAMPLE OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC → (TOS), R8 → PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0

ADDRESS MODE S

Register + + MOV Rs,Rd MOV R10,R11 R10 → R11

Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)

Symbolic (PC relative) + + MOV EDE,TONI M(EDE) → M(TONI)

Absolute + + MOV &MEM, &TCDAT M(MEM) → M(TCDAT)

Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)

Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11

Immediate + MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) S = source, D = destination

Table 3. Instruction Word Formats

Table 4. Address Mode Descriptions

(1)

(1)

D

SYNTAX EXAMPLE OPERATION

M(R10) → R11

R10 + 2 → R10

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Operating Modes

The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.

The following seven operating modes can be configured by software:

• Active mode (AM)
– All clocks are active

• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active

• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled

• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active

• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active

• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention

• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4

• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4

www.ti.com

18 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 5. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

System Reset

Power-Up, External Reset

Watchdog Timeout, Key Violation

WDTIFG, KEYV (SYSRSTIV)

Flash Memory Key Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

JMBOUTIFG (SYSSNIV)

User NMI

NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG

Oscillator Fault (SYSUNIV)

(1)(2)

Flash Memory Access Violation

Comp_B Comparator B interrupt flags (CBIV)

Timer TB0 TB0CCR0 CCIFG0
Timer TB0 Maskable 0FFF4h 58

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)

ADC12_A

(4)

ADC12IFG0 to ADC12IFG15 (ADC12IV)

Timer TA0 TA0CCR0 CCIFG0
Timer TA0 Maskable 0FFE8h 52

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)

USB_UBM USB interrupts (USBIV)

DMA Maskable 0FFE4h 50

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,

DMA4IFG, DMA5IFG (DMAIV)

Timer TA1 TA1CCR0 CCIFG0
Timer TA1 Maskable 0FFE0h 48

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)

I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)

I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)

Reserved Reserved Maskable 0FFD6h 43

RTC_B Maskable 0FFD4h 42

DAC12_A

(5)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)

DAC12_0IFG, DAC12_1IFG

Timer TA2 TA2CCR0 CCIFG0
Timer TA2 Maskable 0FFCEh 39

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)

(1)(2)

(1)

(1)(3)

(3)

(1) (3)

(1)(3)
(1)(3)

(1)(3)

(3)

(1)(3)

(1)(3)

(1)(3)

(3)

(1)(3)

(1) (3)

(1)(3)
(1)(3)

(1) (3)

(1)(3)

(1)(3)

(3)

(1)(3)

(1)(3)
(1)(3)

SLAS650D –JUNE 2010–REVISED AUGUST 2013

SYSTEM WORD

INTERRUPT ADDRESS

Reset 0FFFEh 63, highest

(Non)maskable 0FFFAh 61

Maskable 0FFF8h 60
Maskable 0FFF6h 59

Maskable 0FFF0h 56
Maskable 0FFEEh 55
Maskable 0FFECh 54
Maskable 0FFEAh 53

Maskable 0FFE6h 51

Maskable 0FFE2h 49

Maskable 0FFDEh 47
Maskable 0FFDCh 46
Maskable 0FFDAh 45
Maskable 0FFD8h 44

Maskable 0FFD2h 41
Maskable 0FFD0h 40

Maskable 0FFCCh 38
Maskable 0FFCAh 37

(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with peripheral module ADC12_A, otherwise reserved.
(5) Only on devices with peripheral module DAC12_A, otherwise reserved.

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 5. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations (continued)

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

Reserved Reserved

(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatability with other devices, it is recommended to reserve these locations.

(6)

SYSTEM WORD

INTERRUPT ADDRESS

0FFC8h 36

⋮ ⋮

0FF80h 0, lowest

Memory Organization

www.ti.com

Table 6. Memory Organization

MSP430F5636 MSP430F5637 MSP430F5638
MSP430F5633 MSP430F5634 MSP430F5635
MSP430F5630 MSP430F5631 MSP430F5632

Memory (flash) Total Size 128KB 192KB 256KB
Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h

Bank 3 N/A N/A 64 KB

Bank 2 N/A 64 KB 64 KB

Main: code memory

RAM

USB RAM

Information memory
(flash)

Bootstrap loader (BSL)
memory (flash)

Peripherals

(1) N/A = Not available.
(2) Backup RAM is accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
(3) USB RAM can be used as general purpose RAM when not used for USB operation.

(3)

Bank 1 64 KB 64 KB 64 KB

027FFF-018000h 027FFF-018000h 027FFF-018000h

Bank 0 64 KB 64 KB 64 KB

017FFF-008000h 017FFF-008000h 017FFF-008000h

Sector 3 4 KB 4 KB 4 KB

0063FFh–005400h 0063FFh–005400h 0063FFh–005400h

Sector 2 4 KB 4 KB 4 KB

0053FFh–004400h 0053FFh–004400h 0053FFh–004400h

Sector 1 4 KB 4 KB 4 KB

0043FFh–003400h 0043FFh–003400h 0043FFh–003400h

Sector 0 4 KB 4 KB 4 KB

0033FFh–002400h 0033FFh–002400h 0033FFh–002400h

Size 2KB 2KB 2KB

RAM 0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h

Info A 128 B 128 B 128 B

0019FFh–001980h 0019FFh–001980h 0019FFh–001980h

Info B 128 B 128 B 128 B

00197Fh–001900h 00197Fh–001900h 00197Fh–001900h

Info C 128 B 128 B 128 B

0018FFh–001880h 0018FFh–001880h 0018FFh–001880h

Info D 128 B 128 B 128 B

00187Fh–001800h 00187Fh–001800h 00187Fh–001800h

BSL 3 512 B 512 B 512 B

0017FFh–001600h 0017FFh–001600h 0017FFh–001600h

BSL 2 512 B 512 B 512 B

0015FFh–001400h 0015FFh–001400h 0015FFh–001400h

BSL 1 512 B 512 B 512 B

0013FFh–001200h 0013FFh–001200h 0013FFh–001200h

BSL 0 512 B 512 B 512 B

0011FFh–001000h 0011FFh–001000h 0011FFh–001000h

Size 4KB 4KB 4KB

000FFFh–000000h 000FFFh–000000h 000FFFh–000000h

(1)(2)

047FFF-038000h

037FFF-028000h 037FFF-028000h

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MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. For complete description of the features of
the BSL and its implementation, see MSP430 Programming Via the Bootstrap Loader (BSL) (SLAU319).

USB BSL

All devices come pre-programmed with the USB BSL. Use of the USB BSL requires external access to the six
pins shown in Table 7. In addition to these pins, the application must support external components necessary for
normal USB operation; for example, the proper crystal on XT2IN and XT2OUT or proper decoupling.

Table 7. USB BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

PU.0/DP USB data terminal DP
PU.1/DM USB data terminal DM

PUR USB pullup resistor terminal
VBUS USB bus power supply
VSSU USB ground supply

SLAS650D –JUNE 2010–REVISED AUGUST 2013

NOTE

The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is
pulled high externally, then the BSL is invoked. Therefore, unless the application is
invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or
USB is never used. Applying a 1-MΩ resistor to ground is recommended.

UART BSL

A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the pre­programmed, factory supplied, USB BSL. Use of the UART BSL requires external access to the six pins shown
in Table 8.

Table 8. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

TEST/SBWTCK Entry sequence signal

P1.1 Data transmit

P1.2 Data receive

VCC Power supply

VSS Ground supply

JTAG Operation

JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 9. For further
details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools
User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 9. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control

PJ.1/TDI/TCLK IN JTAG data input, TCLK input

PJ.0/TDO OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

VCC Power supply
VSS Ground supply

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy­Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 10. For further details on interfacing to development tools and
device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description
of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).

www.ti.com

Table 10. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output

VCC Power supply
VSS Ground supply

Flash Memory (Link to User's Guide)

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.

• Segment A can be locked separately.

RAM Memory (Link to User's Guide)

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:

• RAM memory has n sectors. The size of a sector can be found in Memory Organization.

• Each sector 0 to n can be complete disabled, however data retention is lost.

• Each sector 0 to n automatically enters low power retention mode when possible.

• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

Backup RAM Memory

The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.

There are 8 bytes of Backup RAM available on MSP430F563x. It can be wordwise accessed via the control
registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

22 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated

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MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).

Digital I/O (Link to User's Guide)

There are up to nine 8-bit I/O ports implemented: P1 through P6, P8, and P9 are complete, P7 contains six
individual I/O ports, and PJ contains four individual I/O ports.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Programmable drive strength on all ports.

• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.

• Read/write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

Port Mapping Controller (Link to User's Guide)

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 11. Port Mapping, Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

0 PM_NONE None DV

1

2

3

4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0
5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1
6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2
7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3
8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4
9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5

10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6

11

12

13

14

15

16

17 PM_MCLK - MCLK
18 Reserved Reserved for test purposes. Do not use this setting.

PM_CBOUT - Comparator_B output

PM_TB0CLK Timer TB0 clock input -

PM_ADC12CLK - ADC12CLK

PM_DMAE0 DMAE0 Input -

PM_SVMOUT - SVM output

PM_TB0OUTH -

PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)

PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)

PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)

PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)

PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

Timer TB0 high impedance input

TB0OUTH

SS

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MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 11. Port Mapping, Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

19 Reserved Reserved for test purposes. Do not use this setting.

20-30 Reserved None DVSS

31 (0FFh)

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,

(1)

which results in a read out value of 31.

PM_ANALOG

Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents

when applying analog signals.

Table 12. Default Mapping

PIN INPUT PIN FUNCTION OUTPUT PIN FUNCTION

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5
P2.6/P2MAP6 PM_NONE - DVSS

P2.7/P2MAP7 PM_NONE - DVSS

PxMAPy

MNEMONIC

PM_UCB0STE, USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)

PM_UCB0SIMO, USCI_B0 SPI slave in master out (direction controlled by USCI),

PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0SOMI, USCI_B0 SPI slave out master in (direction controlled by USCI),

PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0CLK, USCI_B0 clock input/output (direction controlled by USCI),

PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

PM_UCA0TXD, USCI_A0 UART TXD (direction controlled by USCI - output),

PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0RXD, USCI_A0 UART RXD (direction controlled by USCI - input),

PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

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Oscillator and System Clock (Link to User's Guide)

The clock system in the MSP430F563x family of devices is supported by the Unified Clock System (UCS)
module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not
supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency
oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal
oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a
digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The
internal DCO provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the
following clock signals:

• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally­controlled oscillator DCO.

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources available to ACLK.

• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM) (Link to User's Guide)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

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MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

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Hardware Multiplier (MPY) (Link to User's Guide)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_B) (Link to User's Guide)

The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,
hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports
flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in
LPM3.5 mode and operation from a backup supply.

Watchdog Timer (WDT_A) (Link to User's Guide)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.

System Module (SYS) (Link to User's Guide)

The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap
loader entry mechanisms, and configuration management (device descriptors). SYS also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 13. System Module Interrupt Vector Registers

INTERRUPT VECTOR

REGISTER

SYSRSTIV, System Reset 019Eh

INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY

No interrupt pending 00h

Brownout (BOR) 02h Highest
RST/NMI (BOR) 04h

DoBOR (BOR) 06h

LPM3.5 or LPM4.5 wakeup (BOR) 08h

Security violation (BOR) 0Ah

SVSL (POR) 0Ch

SVSH (POR) 0Eh

SVML_OVP (POR) 10h

SVMH_OVP (POR) 12h

DoPOR (POR) 14h

WDT timeout (PUC) 16h

WDT key violation (PUC) 18h

KEYV flash key violation (PUC) 1Ah

Reserved 1Ch

Peripheral area fetch (PUC) 1Eh

PMM key violation (PUC) 20h

Reserved 22h to 3Eh Lowest

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MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 13. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

REGISTER

SYSSNIV, System NMI VMAIFG 019Ch 0Ah

SYSUNIV, User NMI 019Ah

SYSBERRIV, Bus Error USB wait state timeout 0198h 02h Highest

INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY

No interrupt pending 00h

SVMLIFG 02h Highest
SVMHIFG 04h

DLYLIFG 06h

DLYHIFG 08h

JMBINIFG 0Ch

JMBOUTIFG 0Eh

SVMLVLRIFG 10h

SVMHVLRIFG 12h

Reserved 14h to 1Eh Lowest

No interrupt pending 00h

NMIFG 02h Highest

OFIFG 04h

ACCVIFG 06h

BUSIFG 08h

Reserved 0Ah to 1Eh Lowest

No interrupt pending 00h

Reserved 04h to 1Eh Lowest

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MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

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DMA Controller (Link to User's Guide)

The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.

The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in

Table 14.

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 14. DMA Trigger Assignments

Trigger

0 DMAREQ
1 TA0CCR0 CCIFG
2 TA0CCR2 CCIFG
3 TA1CCR0 CCIFG
4 TA1CCR2 CCIFG
5 TA2CCR0 CCIFG
6 TA2CCR2 CCIFG
7 TBCCR0 CCIFG
8 TBCCR2 CCIFG

9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 UCA0RXIFG
17 UCA0TXIFG
18 UCB0RXIFG
19 UCB0TXIFG
20 UCA1RXIFG
21 UCA1TXIFG
22 UCB1RXIFG
23 UCB1TXIFG
24 ADC12IFGx
25 DAC12_0IFG
26 DAC12_1IFG
27 USB FNRXD
28 USB ready
29 MPY ready
30 DMA5IFG DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA4IFG
31 DMAE0

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not

cause any DMA trigger event when selected.
(2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC.
(3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

0 1 2 3 4 5

Channel

(2)

(3)
(3)

(1)

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MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode,

I2C Mode)

The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.

The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C.
The MSP430F563x series includes two complete USCI modules (n = 0 to 1).

Timer TA0 (Link to User's Guide)

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 15. Timer TA0 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

34-P1.0 L5-P1.0 TA0CLK TACLK

34-P1.0 L5-P1.0 TA0CLK TACLK
35-P1.1 M5-P1.1 TA0.0 CCI0A 35-P1.1 M5-P1.1

36-P1.2 J6-P1.2 TA0.1 CCI1A 36-P1.2 J6-P1.2
40-P1.6 J7-P1.6 TA0.1 CCI1B 40-P1.6 J7-P1.6

37-P1.3 H6-P1.3 TA0.2 CCI2A 37-P1.3 H6-P1.3
41-P1.7 M7-P1.7 TA0.2 CCI2B 41-P1.7 M7-P1.7

38-P1.4 M6-P1.4 TA0.3 CCI3A 38-P1.4 M6-P1.4

39-P1.5 L6-P1.5 TA0.4 CCI4A 39-P1.5 L6-P1.5

(1) Only on devices with peripheral module ADC12_A.

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

ACLK ACLK

SMCLK SMCLK

DV
DV
DV

DV
DV

DV
DV

DV
DV
DV

DV
DV
DV

SS
SS

CC

SS

CC

SS

CC

SS
SS

CC

SS
SS

CC

CCI0B

GND

V

CC

GND

V

CC

GND

V

CC

CCI3B

GND

V

CC

CCI4B

GND

V

CC

MODULE

BLOCK

Timer NA NA

CCR0 TA0 TA0.0

CCR1 TA1 TA0.1

CCR2 TA2 TA0.2

CCR3 TA3 TA0.3

CCR4 TA4 TA0.4

ADC12_A (internal)

ADC12SHSx = {1}

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(1)

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MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

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Timer TA1 (Link to User's Guide)

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 16. Timer TA1 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

42-P3.0 L7-P3.0 TA1CLK TACLK

42-P3.0 L7-P3.0 TA1CLK TACLK
43-P3.1 H7-P3.1 TA1.0 CCI0A 43-P3.1 H7-P3.1

44-P3.2 M8-P3.2 TA1.1 CCI1A 44-P3.2 M8-P3.2

45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3

(1) Only on devices with peripheral module DAC12_A.

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

ACLK ACLK

SMCLK SMCLK

DV

SS

DV

SS

DV

CC

CBOUT

(internal)

DV

SS

DV

CC

ACLK

(internal)

DV

SS

DV

CC

CCI0B

GND

V

CC

CCI1B DAC12_0, DAC12_1

GND

V

CC

CCI2B

GND

V

CC

MODULE

BLOCK

Timer NA NA

CCR0 TA0 TA1.0

CCR1 TA1 TA1.1

CCR2 TA2 TA1.2

SLAS650D –JUNE 2010–REVISED AUGUST 2013

DAC12_A

(internal)

(1)

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MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Timer TA2 (Link to User's Guide)

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 17. Timer TA2 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

46-P3.4 J8-P3.4 TA2CLK TACLK

46-P3.4 J8-P3.4 TA2CLK TACLK
47-P3.5 M9-P3.5 TA2.0 CCI0A 47-P3.5 M9-P3.5

48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6

49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

ACLK ACLK

SMCLK SMCLK

DV

SS

DV

SS

DV

CC

CBOUT

(internal)

DV

SS

DV

CC

ACLK

(internal)

DV

SS

DV

CC

CCI0B

GND

V

CC

CCI1B

GND

V

CC

CCI2B

GND

V

CC

MODULE

BLOCK

Timer NA NA

CCR0 TA0 TA2.0

CCR1 TA1 TA2.1

CCR2 TA2 TA2.2

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