Texas Instruments MSP430F2272TDA, MSP430F2252IYFF, MSP430F2232IDA, MSP430F2232IYFF, MSP430F2252IDA User Manual

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MSP430F22x2 MSP430F22x4

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MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range: 1.8 V to 3.6 V

• Ultra-Low Power Consumption – Active Mode: 270 µA at 1 MHz, 2.2 V – Standby Mode: 0.7 µA – Off Mode (RAM Retention): 0.1 µA

• Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs

• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time

• Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1% – 512B RAM

– Internal Very-Low-Power Low-Frequency – MSP430F2252

Oscillator – 32-kHz Crystal – High-Frequency (HF) Crystal up to 16 MHz – Resonator – External Digital Clock Source – External Resistor

• 16-Bit Timer_A With Three Capture/Compare Registers

• 16-Bit Timer_B With Three Capture/Compare Registers

• Universal Serial Communication Interface – Enhanced UART Supporting Auto-Baudrate

Detection (LIN) – IrDA Encoder and Decoder – Synchronous SPI – I2C™

• 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sampleand-Hold, Autoscan, and Data Transfer Controller

• Two Configurable Operational Amplifiers (MSP430F22x4 Only)

• Brownout Detector

• Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse

• Bootstrap Loader

• On-Chip Emulation Module

• Family Members Include: – MSP430F2232

– 8KB + 256B Flash Memory

– 16KB + 256B Flash Memory – 512B RAM

– MSP430F2272

– 32KB + 256B Flash Memory – 1KB RAM

– MSP430F2234

– 8KB + 256B Flash Memory – 512B RAM

– MSP430F2254

– 16KB + 256B Flash Memory – 512B RAM

– MSP430F2274

– 32KB + 256B Flash Memory – 1KB RAM

• Available in a 38-Pin Thin Shrink Small-Outline Package (TSSOP) (DA), 40-Pin QFN Package (RHA), and 49-Pin Ball Grid Array Package (YFF) (See Table 1)

• For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144)

SLAS504G –JULY 2006–REVISED AUGUST 2012

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430F22x4/MSP430F22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front ends are another area of application.

Table 1. Available Options

PACKAGED DEVICES

-40°C to 85°C

-40°C to 105°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PLASTIC 49-PIN BGA PLASTIC 38-PIN TSSOP PLASTIC 40-PIN QFN

(YFF) (DA) (RHA)

MSP430F2232IYFF MSP430F2232IDA MSP430F2232IRHA MSP430F2252IYFF MSP430F2252IDA MSP430F2252IRHA MSP430F2272IYFF MSP430F2272IDA MSP430F2272IRHA MSP430F2234IYFF MSP430F2234IDA MSP430F2234IRHA MSP430F2254IYFF MSP430F2254IDA MSP430F2254IRHA MSP430F2274IYFF MSP430F2274IDA MSP430F2274IRHA

MSP430F2232TDA MSP430F2232TRHA MSP430F2252TDA MSP430F2252TRHA MSP430F2272TDA MSP430F2272TRHA MSP430F2234TDA MSP430F2234TRHA MSP430F2254TDA MSP430F2254TRHA MSP430F2274TDA MSP430F2274TRHA

(1)(2)

Development Tool Support

All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging and programming through easy-to-use development tools. Recommended hardware options include:

• Debugging and Programming Interface – MSP-FET430UIF (USB) – MSP-FET430PIF (Parallel Port)

• Debugging and Programming Interface with Target Board – MSP-FET430U38 (DA package)

• Production Programmer – MSP-GANG430

1TEST/SBWTCK

2DVCC

3P2.5/R

OSC

XOUT/P2.7

XIN/P2.6 6

RST/NMI/SBWTDIO

P2.0/ACLK/A0/OA0I0

P2.1/TAINCLK/SMCLK/A1/OA0O 9

P2.2/TA0/A2/OA0I1

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

18 P4.4/TB1/A13/OA1O

38 P1.7/TA2/TDO/TDI

37 P1.6/TA1/TDI

P1.5/TA0/TMS

35 P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

32 P1.1/TA0

P1.0/TACLK/ADC10CLK

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

29 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O

28 P3.7/A7/OA1I2

27 P3.6/A6/OA0I2

26 P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TBCLK

P4.6/TBOUTH/A15/OA1I3

DVSS

P4.5/TB2/A14/OA0I3

1TEST/SBWTCK

2DVCC

3P2.5/R

OSC

XOUT/P2.7

XIN/P2.6 6

RST/NMI/SBWTDIO

P2.0/ACLK/A0

P2.1/TAINCLK/SMCLK/A1 9

P2.2/TA0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12

18 P4.4/TB1/A13

38 P1.7/TA2/TDO/TDI

37 P1.6/TA1/TDI

P1.5/TA0/TMS

35 P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

32 P1.1/TA0

P1.0/TACLK/ADC10CLK

P2.4/TA2/A4/VREF+/VeREF+

29 P2.3/TA1/A3/VREF−/VeREF−

28 P3.7/A7

27 P3.6/A6

26 P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TBCLK

P4.6/TBOUTH/A15

DVSS

P4.5/TB2/A14

MSP430F22x2 MSP430F22x4

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MSP430F22x2 Device Pinout, DA Package

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4 Device Pinout, DA Package

1DVSS

P1.5/TA0/TMS

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

P2.4/TA2/A4/VREF+/VeREF+

P2.5/R

OSC

DVCC

TEST/SBWTCK

P1.6/TA1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0

P2.1/TAINCLK/SMCLK/A1

P2.2/TA0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA2/TDO/TDI

P2.3/TA1/A3/VREF−/VeREF−

P3.7/A7

P3.6/A6

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12

P4.4/TB1/A13

P4.5/TB2/A14

P4.6/TBOUTH/A15

P4.7/TBCLK

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x2 Device Pinout, RHA Package

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1DVSS

P1.5/TA0/TMS

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

P2.5/R

OSC

DVCC

TEST/SBWTCK

P1.6/TA1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0/OA0I0

P2.1/TAINCLK/SMCLK/A1/OA0O

P2.2/TA0/A2/OA0I1

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA2/TDO/TDI

P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O

P3.7/A7/OA1I2

P3.6/A6/OA0I2

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

P4.4/TB1/A13/OA1O

P4.5/TB2/A14/OA0I3

P4.6/TBOUTH/A15/OA1I3

P4.7/TBCLK

MSP430F22x2 MSP430F22x4

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MSP430F22x4 Device Pinout, RHA Package

SLAS504G –JULY 2006–REVISED AUGUST 2012

A1 A2 A4A3 A5 A6 A7

TOP VIEW

B1 B2 B4B3 B5 B6 B7

C1 C2 C4C3 C5 C6 C7

D1 D2 D4D3 D5 D6 D7

E1 E2 E4E3 E5 E6 E7

F1 F2 F4F3 F5 F6 F7

G1 G2 G4G3 G5 G6 G7

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package

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Package Dimensions

The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this data sheet for more details.

Table 2. YFF Package Dimensions

PACKAGED DEVICES D E

MSP430F22x2 MSP430F22x4

3.33 ± 0.03 mm 3.49 ± 0.03 mm

Basic Clock

System+

RAM

1kB 512B 512B

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15/16−Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

32kB 16kB

8kB

ACLK

XIN

MDB

MAB

Spy−Bi Wire

Timer_B3

3 CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

OA0, OA1

2 Op Amps

ADC10

10−Bit

12 Channels, Autoscan,

DTC

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

Ports P3/P4

2x8 I/O

pull−up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

Basic Clock

System+

RAM

1kB 512B 512B

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15/16−Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

32kB 16kB

8kB

ACLK

XIN

MDB

MAB

Spy−Bi Wire

Timer_B3

3 CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

ADC10

10−Bit

12 Channels, Autoscan,

DTC

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

Ports P3/P4

2x8 I/O

pull−up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

MSP430F22x2 MSP430F22x4

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MSP430F22x2 Functional Block Diagram

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4 Functional Block Diagram

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2

TERMINAL

NAME

P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input

P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output

P1.2/TA1 E2 33 31 I/O

P1.3/TA2 G1 34 32 I/O

P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output

P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output

P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output

REF-

REF+

(1)

/ V

eREF-

eREF+

P1.7/TA2/TDO/TDI

P2.0/ACLK/A0 A4 8 6 I/O ACLK output

P2.1/TAINCLK/SMCLK/A1 B4 9 7 I/O

P2.2/TA0/A2 A5 10 8 I/O Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output

P2.3/TA1/A3/V

P2.4/TA2/A4/V

P2.5/R

OSC

XIN/P2.6 A2 6 3 I/O

YFF DA RHA

NO. I/O DESCRIPTION

General-purpose digital I/O pin

ADC10, conversion clock General-purpose digital I/O pin

BSL transmit General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin

Test Clock input for device programming and test General-purpose digital I/O pin

Test Mode Select input for device programming and test General-purpose digital I/O pin

Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin

D2 38 36 I/O Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin

ADC10, analog input A0 General-purpose digital I/O pin Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1 General-purpose digital I/O pin

ADC10, analog input A2 General-purpose digital I/O pin

F3 29 27 I/O

G3 30 28 I/O

C2 3 40 I/O

Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 Negative reference voltage input General-purpose digital I/O pin Timer_A, compare: OUT2 output ADC10, analog input A4 Positive reference voltage output or input General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator General-purpose digital I/O pin

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MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2 (continued)

TERMINAL

NAME

XOUT/P2.7 A1 5 2 I/O

P3.0/UCB0STE/UCA0CLK/ A5

P3.1/UCB0SIMO/ UCB0SDA

P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in

P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output

P3.4/UCA0TXD/ UCA0SIMO

P3.5/UCA0RXD/ UCA0SOMI

P3.6/A6 F4 27 25 I/O

P3.7/A7 G4 28 26 I/O

P4.0/TB0 D6 17 15 I/O

P4.1/TB1 D7 18 16 I/O

P4.2/TB2 E6 19 17 I/O

P4.3/TB0/A12 E7 20 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output

P4.4/TB1/A13 F7 21 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output

P4.5/TB2/A14 F6 22 20 I/O Timer_B, compare: OUT2 output

P4.6/TBOUTH/A15 G7 23 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance

YFF DA RHA

NO. I/O DESCRIPTION

Output terminal of crystal oscillator General-purpose digital I/O pin General-purpose digital I/O pin

B5 11 9 I/O

A6 12 10 I/O USCI_B0 SPI mode: slave in/master out

G6 25 23 I/O USCI_A0 UART mode: transmit data output

G5 26 24 I/O USCI_A0 UART mode: receive data input

USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin

USCI_B0 I2C mode: SDA I2C data General-purpose digital I/O pin

USCI_B0 I2C mode: SCL I2C clock General-purpose digital I/O pin

USCI_A0 slave transmit enable General-purpose digital I/O pin

USCI_A0 SPI mode: slave in/master out General-purpose digital I/O pin

USCI_A0 SPI mode: slave out/master in General-purpose digital I/O pin ADC10 analog input A6 General-purpose digital I/O pin ADC10 analog input A7 General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin

ADC10 analog input A12 General-purpose digital I/O pin

ADC10 analog input A13 General-purpose digital I/O pin

ADC10 analog input A14 General-purpose digital I/O pin

ADC10 analog input A15

(2)

(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2 (continued)

TERMINAL

NAME

P4.7/TBCLK F5 24 22 I/O

RST/NMI/SBWTDIO B3 7 5 I

TEST/SBWTCK D1 1 37 I

QFN Pad NA NA Pad NA QFN package pad; connection to DVSSrecommended.

YFF DA RHA

E4, E5

NO. I/O DESCRIPTION

General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST. Spy-Bi-Wire test clock input during programming and test

C1, D3, D4,

C6, C7, 16 14 Analog supply voltage

A3, B1, B2, 4 1, 4 Digital ground reference C3,

B7,

2 38, 39 Digital supply voltage

15 13 Analog ground reference

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MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 4. Terminal Functions, MSP430F22x4

TERMINAL

NAME

P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input

P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output

P1.2/TA1 E2 33 31 I/O

P1.3/TA2 G1 34 32 I/O

P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output

P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output

P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output

P1.7/TA2/TDO/TDI

P2.0/ACLK/A0/OA0I0 A4 8 6 I/O

P2.1/TAINCLK/SMCLK/ A1/OA0O

P2.2/TA0/A2/OA0I1 A5 10 8 I/O

P2.3/TA1/A3/ V OA1I1/OA1O

(1)

REF-/VeREF-

YFF DA RHA

NO. I/O DESCRIPTION

General-purpose digital I/O pin

ADC10, conversion clock General-purpose digital I/O pin

Test Clock input for device programming and test General-purpose digital I/O pin

Test Mode Select input for device programming and test General-purpose digital I/O pin

Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin

D2 38 36 I/O Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin ACLK output ADC10, analog input A0 OA0, analog input IO General-purpose digital I/O pin Timer_A, clock signal at INCLK

B4 9 7 I/O SMCLK signal output

ADC10, analog input A1 OA0, analog output General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 OA0, analog input I1 General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output

F3 29 27 I/O

ADC10, analog input A3 Negative reference voltage input OA1, analog input I1 OA1, analog output

(1) TDO or TDI is selected via JTAG instruction.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 4. Terminal Functions, MSP430F22x4 (continued)

TERMINAL

NAME

P2.4/TA2/A4/ V

REF+/VeREF+

P2.5/R

XIN/P2.6 A2 6 3 I/O

XOUT/P2.7 A1 5 2 I/O

P3.0/UCB0STE/UCA0CLK/ A5

P3.1/UCB0SIMO/ UCB0SDA

P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in

P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output

P3.4/UCA0TXD/ UCA0SIMO

P3.5/UCA0RXD/ UCA0SOMI

P3.6/A6/OA0I2 F4 27 25 I/O ADC10 analog input A6

P3.7/A7/OA1I2 G4 28 26 I/O ADC10 analog input A7

P4.0/TB0 D6 17 15 I/O

P4.1/TB1 D7 18 16 I/O

P4.2/TB2 E6 19 17 I/O

/OA1I0

OSC

YFF DA RHA

NO. I/O DESCRIPTION

General-purpose digital I/O pin Timer_A, compare: OUT2 output

G3 30 28 I/O ADC10, analog input A4

Positive reference voltage output or input OA1, analog input I/O

C2 3 40 I/O

B5 11 9 I/O

A6 12 10 I/O USCI_B0 SPI mode: slave in/master out

G6 25 23 I/O USCI_A0 UART mode: transmit data output

G5 26 24 I/O USCI_A0 UART mode: receive data input

General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator General-purpose digital I/O pin Output terminal of crystal oscillator General-purpose digital I/O pin General-purpose digital I/O pin USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin

USCI_B0 I2C mode: SDA I2C data General-purpose digital I/O pin

USCI_B0 I2C mode: SCL I2C clock General-purpose digital I/O pin

USCI_A0 slave transmit enable General-purpose digital I/O pin

USCI_A0 SPI mode: slave in/master out General-purpose digital I/O pin

USCI_A0 SPI mode: slave out/master in General-purpose digital I/O pin

OA0 analog input I2 General-purpose digital I/O pin

OA1 analog input I2 General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output

(2)

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(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Table 4. Terminal Functions, MSP430F22x4 (continued)

TERMINAL

NAME

P4.3/TB0/A12/OA0O E7 20 18 I/O

P4.4/TB1/A13/OA1O F7 21 19 I/O

P4.5/TB2/A14/OA0I3 F6 22 20 I/O

P4.6/TBOUTH/A15/OA1I3 G7 23 21 I/O

P4.7/TBCLK F5 24 22 I/O

RST/NMI/SBWTDIO B3 7 5 I

TEST/SBWTCK D1 1 37 I

QFN Pad NA NA Pad NA QFN package pad; connection to DVSSrecommended.

YFF DA RHA

E4, E5

NO. I/O DESCRIPTION

General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 OA0 analog output General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 OA1 analog output General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 OA0 analog input I3 General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 OA1 analog input I3 General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST. Spy-Bi-Wire test clock input during programming and test

C1, D3, D4,

C6, C7, 16 14 Analog supply voltage

A3, B1, B2, 4 1, 4 Digital ground reference C3,

B7,

2 38, 39 Digital supply voltage

15 13 Analog ground reference

General-PurposeRegister

ProgramCounter

StackPointer

StatusRegister

ConstantGenerator

General-PurposeRegister

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-PurposeRegister

R10

R11

General-PurposeRegister

R14

R15

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SHORT-FORM DESCRIPTION

CPU

The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.

Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.

Table 5 shows examples of the three types of

instruction formats; Table 6 shows the address modes.

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Dual operands, source-destination ADD R4,R5 R4 + R5 → R5 Single operands, destination only CALL R8 PC → (TOS), R8 → PC Relative jump, unconditional/conditional JNE Jump-on-equal bit = 0

Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6) Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI) Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) → M(TCDAT) Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)

Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) S = source (2) D = destination

INSTRUCTION FORMAT EXAMPLE OPERATION

ADDRESS MODE S

Table 5. Instruction Word Formats

Table 6. Address Mode Descriptions

(1)

(2)

SYNTAX EXAMPLE OPERATION

M(R10) → R11

R10 + 2 → R10

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Operating Modes

The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active.

• Low-power mode 0 (LPM0) – CPU is disabled. – ACLK and SMCLK remain active. MCLK is disabled.

• Low-power mode 1 (LPM1) – CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. – DCO dc-generator is disabled if DCO not used in active mode.

• Low-power mode 2 (LPM2) – CPU is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator remains enabled. – ACLK remains active.

• Low-power mode 3 (LPM3) – CPU is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – ACLK remains active.

• Low-power mode 4 (LPM4) – CPU is disabled. – ACLK is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – Crystal oscillator is stopped.

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up.

Table 7. Interrupt Vector Addresses

INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog Reset 0FFFEh 31, highest Flash key violation PC out-of-range

(1)

PORIFG

RSTIFG

WDTIFG

(2)

KEYV

NMI NMIIFG (non)-maskable,

Oscillator fault OFIFG (non)-maskable, 0FFFCh 30

Flash memory access violation ACCVIFG

Timer_B3 TBCCR0 CCIFG Timer_B3 maskable 0FFF8h 28

TBCCR1 and TBCCR2 CCIFGs,

TBIFG

(2)(3)

(4)

(2)(4)

Watchdog Timer WDTIFG maskable 0FFF4h 26

Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25

TACCR1 CCIFG

Timer_A3 TACCR2 CCIFG maskable 0FFF0h 24

USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG

ADC10 ADC10IFG

I/O Port P2

(eight flags)

I/O Port P1

(eight flags)

(5) (6)

P2IFG.0 to P2IFG.7

P1IFG.0 to P1IFG.7

TAIFG

(2)(4)

(2)

(4)

(2)(4)

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address range. (2) Multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (4) Interrupt flags are located in the module. (5) This location is used as bootstrap loader security key (BSLSKEY).

A 0AA55h at this location disables the BSL completely.

A zero (0h) disables the erasure of the flash if an invalid password is supplied. (6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

SYSTEM

INTERRUPT

(non)-maskable

maskable 0FFFAh 29

0FFF6h 27

maskable 0FFEEh 23 maskable 0FFECh 22 maskable 0FFEAh 21

0FFE8h 20

maskable 0FFE6h 19

maskable 0FFE4h 18

0FFE2h 17 0FFE0h 16

0FFDEh 15

0FFDCh to 0FFC0h 14 to 0, lowest

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Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend

rw Bit can be read and written. rw-0, 1 Bit can be read and written. It is Reset or Set by PUC. rw-(0), (1) Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

Table 8. Interrupt Enable 1

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval

OFIE Oscillator fault interrupt enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable

Address 7 6 5 4 3 2 1 0

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

timer mode.

Table 9. Interrupt Enable 2

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable

Table 10. Interrupt Flag Register 1

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCCpower-up or a reset condition at RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCCpower up. PORIFG Power-on reset interrupt flag. Set on VCCpower up. NMIIFG Set via RST/NMI pin

Table 11. Interrupt Flag Register 2

Address 7 6 5 4 3 2 1 0

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag

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Memory Organization

Table 12. Memory Organization

MSP430F223x MSP430F225x MSP430F227x

Memory Size 8KB Flash 16KB Flash 32KB Flash Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main: code memory Flash 0FFFFh-0E000h 0FFFFh-0C000h 0FFFFh-08000h

Information memory

Boot memory

RAM Size

Peripherals 8-bit 0FFh-010h 0FFh-010h 0FFh-010h

Size 256 Byte 256 Byte 256 Byte

Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h

Size 1KB 1KB 1KB

ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h

512 Byte 512 Byte 1KB

03FFh-0200h 03FFh-0200h 05FFh-0200h

16-bit 01FFh-0100h 01FFh-0100h 01FFh-0100h

8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h

Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User’s Guide (SLAU319).

Table 13. BSL Function Pins

BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS YFF PACKAGE PINS

Data transmit 32 - P1.1 30 - P1.1 G3 - P1.1

Data receive 10 - P2.2 8 - P2.2 A5 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory.

• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required.

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal verylow-power LF oscillator.

• Main clock (MCLK), the system clock used by the CPU.

• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

Table 14. DCO Calibration Data

(Provided From Factory in Flash Information Memory Segment A)

DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS

1 MHz

8 MHz

12 MHz

16 MHz

CALBC1_1MHZ byte 010FFh

CALDCO_1MHZ byte 010FEh

CALBC1_8MHZ byte 010FDh

CALDCO_8MHZ byte 010FCh

CALBC1_12MHZ byte 010FBh

CALDCO_12MHZ byte 010FAh

CALBC1_16MHZ byte 010F9h

CALDCO_16MHZ byte 010F8h

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

Digital I/O

There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt condition is possible.

• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.

• Read/write access to port-control registers is supported by all instructions.

• Each I/O has an individually programmable pullup/pulldown resistor.

Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and write data is ignored.

Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

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Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 15. Timer_A3 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER

DA RHA YFF DA RHA YFF

31 - P1.0 29 - P1.0 F2 - P1.0 TACLK TACLK Timer NA

9 - P2.1 7 - P2.1 B4 - P2.1 TAINCLK INCLK 32 - P1.1 30 - P1.1 G2 - P1.1 TA0 CCI0A CCR0 TA0 32 - P1.1 30 - P1.1 G2 - P1.1 10 - P2.2 8 - P2.2 A5 - P2.2 TA0 CCI0B 10 - P2.2 8 - P2.2 A5 - P2.2

33 - P1.2 31 - P1.2 E2 - P1.2 TA1 CCI1A CCR1 TA1 33 - P1.2 31 - P1.2 E2 - P1.2 29 - P2.3 27 - P2.3 F3 - P2.3 TA1 CCI1B 29 - P2.3 27 - P2.3 F3 - P2.3

34 - P1.3 32 - P1.3 G1 - P1.3 TA2 CCI2A CCR2 TA2 34 - P1.3 32 - P1.3 G1 - P1.3

INPUT INPUT OUTPUT

SIGNAL NAME SIGNAL

ACLK ACLK

SMCLK SMCLK

ACLK

(internal)

GND 36 - P1.5 34 - P1.5 E1 - P1.5

GND 37 - P1.6 35 - P1.6 E3 - P1.6

CCI2B 30 - P2.4 28 - P2.4 G3 - P2.4

GND 38 - P1.7 36 - P1.7 D2 - P1.7

MODULE

BLOCK

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Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 16. Timer_B3 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER

DA RHA YFF DA RHA YFF

24 - P4.7 22 - P4.7 F5 - P4.7 TBCLK TBCLK Timer NA

24 - P4.7 22 - P4.7 F5 - P4.7 TBCLK INCLK 17 - P4.0 15 - P4.0 D6 - P4.0 TB0 CCI0A CCR0 TB0 17 - P4.0 15 - P4.0 D6 - P4.0 20 - P4.3 18 - P4.3 E7 - P4.3 TB0 CCI0B 20 - P4.3 18 - P4.3 E7 - P4.3

18 - P4.1 16 - P4.1 D7 - P4.1 TB1 CCI1A CCR1 TB1 18 - P4.1 16 - P4.1 D7 - P4.1 21 - P4.4 19 - P4.4 F7 - P4.4 TB1 CCI1B 21 - P4.4 19 - P4.4 F7 - P4.4

19 - P4.2 17 - P4.2 E6 - P4.2 TB2 CCI2A CCR2 TB2 19 - P4.2 17 - P4.2 E6 - P4.2

INPUT INPUT OUTPUT

SIGNAL NAME SIGNAL

ACLK ACLK

SMCLK SMCLK

ACLK

(internal)

GND

CCI2B 22 - P4.5 20 - P4.5 F6 - P4.5

GND

MODULE

BLOCK

Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention.

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Operational Amplifier (OA) (MSP430F22x4 only)

The MSP430F22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

Table 17. OA0 Signal Connections

ANALOG INPUT PIN NUMBER

DA RHA YFF

8 - A0 6 - A0 B4 - A0 OA0I0 OAxI0 10 - A2 8 - A2 B5 - A2 OA0I1 OA0I1 10 - A2 8 - A2 B5 - A2 OA0I1 OAxI1 27 - A6 25 - A6 F4 - A6 OA0I2 OAxIA

22 - A14 20 - A14 F6 - A14 OA0I3 OAxIB

Table 18. OA1 Signal Connections

ANALOG INPUT PIN NUMBER

DA RHA YFF

30 - A4 28 - A4 G3 - A4 OA1I0 OAxI0 10 - A2 8 - A2 B5 - A2 OA0I1 OA0I1 29 - A3 27 - A3 F3 - A3 OA1I1 OAxI1 28 - A7 26 - A7 G4 - A7 OA1I2 OAxIA

23 - A15 21 - A15 G7 - A15 OA1I3 OAxIB

DEVICE INPUT SIGNAL MODULE INPUT NAME

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Peripheral File Map

Table 19. Peripherals With Word Access

MODULE REGISTER NAME SHORT NAME ADDRESS

ADC10 ADC data transfer start address ADC10SA 1BCh

ADC memory ADC10MEM 1B4h ADC control register 1 ADC10CTL1 1B2h ADC control register 0 ADC10CTL0 1B0h ADC analog enable 0 ADC10AE0 04Ah ADC analog enable 1 ADC10AE1 04Bh ADC data transfer control register 1 ADC10DTC1 049h ADC data transfer control register 0 ADC10DTC0 048h

Timer_B Capture/compare register TBCCR2 0196h

Capture/compare register TBCCR1 0194h Capture/compare register TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control TBCCTL2 0186h Capture/compare control TBCCTL1 0184h Capture/compare control TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh

Timer_A Capture/compare register TACCR2 0176h

Capture/compare register TACCR1 0174h Capture/compare register TACCR0 0172h Timer_A register TAR 0170h Capture/compare control TACCTL2 0166h Capture/compare control TACCTL1 0164h Capture/compare control TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh

Flash Memory Flash control 3 FCTL3 012Ch

Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h

Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

OFFSET

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Table 20. Peripherals With Byte Access

MODULE REGISTER NAME SHORT NAME ADDRESS

OA1 (MSP430F22x4 only) Operational Amplifier 1 control register 1 OA1CTL1 0C3h

Operational Amplifier 1 control register 1 OA1CTL0 0C2h

OA0 (MSP430F22x4 only) Operational Amplifier 0 control register 1 OA0CTL1 0C1h

Operational Amplifier 0 control register 1 OA0CTL0 0C0h

USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh

USCI_B0 receive buffer UCB0RXBUF 06Eh USCI_B0 status UCB0STAT 06Dh USCI_B0 bit rate control 1 UCB0BR1 06Bh USCI_B0 bit rate control 0 UCB0BR0 06Ah USCI_B0 control 1 UCB0CTL1 069h USCI_B0 control 0 UCB0CTL0 068h USCI_B0 I2C slave address UCB0SA 011Ah USCI_B0 I2C own address UCB0OA 0118h

USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h

USCI_A0 receive buffer UCA0RXBUF 066h USCI_A0 status UCA0STAT 065h USCI_A0 modulation control UCA0MCTL 064h USCI_A0 baud rate control 1 UCA0BR1 063h USCI_A0 baud rate control 0 UCA0BR0 062h USCI_A0 control 1 UCA0CTL1 061h USCI_A0 control 0 UCA0CTL0 060h USCI_A0 IrDA receive control UCA0IRRCTL 05Fh USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control UCA0ABCTL 05Dh

Basic Clock System+ Basic clock system control 3 BCSCTL3 053h

Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h

Port P4 Port P4 resistor enable P4REN 011h

Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch

Port P3 Port P3 resistor enable P3REN 010h

Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h

Port P2 Port P2 resistor enable P2REN 02Fh

Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h

OFFSET

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Table 20. Peripherals With Byte Access (continued)

MODULE REGISTER NAME SHORT NAME ADDRESS

Port P1 Port P1 resistor enable P1REN 027h

Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h

Special Function SFR interrupt flag 2 IFG2 003h

SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

OFFSET

4.15 MHz

12 MHz

16 MHz

1.8 V 2.2 V 2.7 V 3.3 V 3.6 V

Supply Voltage −V

System Frequency −MHz

Supply voltage range, during flash memory programming

Supply voltage range, during program execution

Legend:

7.5 MHz

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Absolute Maximum Ratings

Voltage applied at VCCto V Voltage applied to any pin

(2)

(1)

-0.3 V to 4.1 V

-0.3 V to VCC+ 0.3 V

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Diode current at any device terminal ±2 mA

Storage temperature, T

stg

(3)

Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak

reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

(1)(2)

MIN NOM MAX UNIT

SYSTEM

During program

Supply voltage AVCC= DVCC= V

execution During program/erase

flash memory

Supply voltage AVSS= DVSS= V

Operating free-air temperature °C

Processor frequency (maximum MCLK frequency) (see Figure 1)

VCC= 1.8 V, Duty cycle = 50% ±10% dc 4.15

(1)(2)

VCC= 2.7 V, Duty cycle = 50% ±10% dc 12 MHz VCC≥ 3.3 V, Duty cycle = 50% ±10% dc 16

I version -40 85 T version -40 105

1.8 3.6 V

2.2 3.6 V 0 V

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V

of 2.2 V.

Figure 1. Operating Area

MSP430F22x2 MSP430F22x4

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Active Mode Supply Current (into DVCC+ AVCC) Excluding External Current

SLAS504G –JULY 2006–REVISED AUGUST 2012

(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

AM,1MHz

AM,4kHz

AM,100kHz

PARAMETER TEST CONDITIONS T

= f

Active mode (AM) current (1 MHz)

DCO

ACLK

Program executes in flash,

= f

MCLK

= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

= 1 MHz, 2.2 V 270 390

SMCLK

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= f

Active mode (AM) current (1 MHz)

DCO

ACLK

Program executes in RAM,

= f

MCLK

= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

= 1 MHz, 2.2 V 240

SMCLK

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= f

MCLK

4096 Hz, 85°C f

= 0 Hz,

Active mode (AM) Program executes in flash,

DCO

current (4 kHz) SELMx = 11, SELS = 1,

DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0

SMCLK

= f

= 32768 Hz/8 = -40°C to

ACLK

105°C 18

-40°C to 85°C

105°C 20

-40°C to 85°C

105°C 95

-40°C to 85°C

Active mode (AM) current (100 kHz)

= f

MCLK

= 0 Hz,

ACLK

Program executes in flash, µA

SMCLK

= f

DCO(0, 0)

≈ 100 kHz,

RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1

105°C 105

MIN TYP MAX UNIT

3 V 390 550

3.3 V 340

2.2 V

3 V

2.2 V

3 V

5 9

µA

6 10

60 85

72 95

(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC− Supply Voltage − V

Active Mode Current − mA

DCO

= 1 MHz

DCO

= 8 MHz

DCO

= 12 MHz

DCO

= 16 MHz

0.0

1.0

2.0

3.0

4.0

5.0

0.0 4.0 8.0 12.0 16.0

DCO

− DCO Frequency − MHz

Active Mode Current − mA

TA= 25 °C

TA= 85 °C

VCC= 2.2 V

VCC= 3 V

TA= 25 °C

TA= 85 °C

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Typical Characteristics - Active-Mode Supply Current (Into DVCC+ AVCC)

ACTIVE-MODE CURRENT

vs ACTIVE-MODE CURRENT

SUPPLY VOLTAGE vs

TA= 25°C DCO FREQUENCY

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Figure 2. Figure 3.

MSP430F22x2 MSP430F22x4

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Low-Power-Mode Supply Currents (Into VCC) Excluding External Current

SLAS504G –JULY 2006–REVISED AUGUST 2012

(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LPM0,1MHz

PARAMETER TEST CONDITIONS T

= 0 MHz, 2.2 V 75 90

MCLK

= f

= 1 MHz,

DCO

= 32768 Hz,

Low-power mode 0 (LPM0) current

(3)

SMCLK

ACLK

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= 0 MHz, 2.2 V 37 48

MCLK

LPM0,100kHz

Low-power mode 0 f (LPM0) current

(3)

= f

SMCLK

= 0 Hz,

ACLK

RSELx = 0, DCOx = 0,

DCO(0, 0)

≈ 100 kHz,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1

-40°C to 85°C

105°C 31

-40°C to 85°C

105°C 34

LPM2

Low-power mode 2 (LPM2) current

(4)

= f

MCLK

= 1 MHz,

DCO

= 32768 Hz,

ACLK

BCSCTL1 = CALBC1_1MHZ, µA

SMCLK

= 0 MHz,

DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

-40°C 0.7 1.4 25°C 0.7 1.4 85°C 2.4 3.3

105°C 5 10

-40°C 0.9 1.5 25°C 0.9 1.5

LPM3,LFXT1

Low-power mode 3 f (LPM3) current

(4)

= f

DCO ACLK

CPUOFF = 1, SCG0 = 1,

= f

MCLK

= 32768 Hz,

SMCLK

= 0 MHz,

SCG1 = 1, OSCOFF = 0

85°C 2.6 3.8

105°C 6 12

-40°C 0.4 1 25°C 0.5 1 85°C 1.8 2.9

105°C 4.5 9

-40°C 0.5 1.2 25°C 0.6 1.2

LPM3,VLO

Low-power mode 3 current, (LPM3)

(4)

= f

DCO

ACLK

(VLO), µA

= f

MCLK

from internal LF oscillator

SMCLK

= 0 MHz,

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0

85°C 2.1 3.3

105°C 5.5 11

-40°C 0.1 0.5 25°C 0.1 0.5 85°C 1.5 3

105°C 4.5 9

LPM4

Low-power mode 4 f (LPM4) current

(5)

= f

DCO ACLK

CPUOFF = 1, SCG0 = 1, 3 V

= f

MCLK

= 0 Hz, 2.2 V/

SMCLK

= 0 MHz,

SCG1 = 1, OSCOFF = 1

load capacitance is chosen to closely match the required 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included.

MIN TYP MAX UNIT

3 V 90 120

3 V 41 65

2.2 V

3 V

22 29

25 32

2.2 V

3 V

2.2 V

3 V

µA

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Positive-going input threshold voltage 2.2 V 1 1.65 V

IT+

3 V 1.35 2.25

Negative-going input threshold voltage 2.2 V 0.55 1.20 V

IT-

3 V 0.75 1.65

Input voltage hysteresis (V

hys

Pullup/pulldown resistor 3 V 20 35 50 kΩ

Pull

Input capacitance VIN= VSSor V

IT+

- V

) V

IT-

For pullup: VIN= VSS, For pulldown: VIN= V

2.2 V 0.1 1 3 V 0.3 1

MIN TYP MAX UNIT

0.45 V

0.25 V

Inputs (Ports P1, P2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

External interrupt timing 2.2 V, 3 V 20 ns

(int)

Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag

(1)

(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t

shorter than t

(int)

is met. It may be set even with trigger signals

(int)

MIN TYP MAX UNIT

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0.75 V

0.55 V

5 pF

Leakage Current (Ports P1, P2, P3, and P4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

lkg(Px.y)

PARAMETER TEST CONDITIONS V

High-impedance leakage current

(1) (2)

2.2 V, 3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

MIN TYP MAX UNIT

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Outputs (Ports P1, P2, P3, and P4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

High-level output voltage V

Low-level output voltage V

(1) The maximum total current, I

specified.

(2) The maximum total current, I

specified.

OH(max)

OL(max)

and I and I

= -1.5 mA = -6 mA = -1.5 mA

= -6 mA = 1.5 mA = 6 mA = 1.5 mA = 6 mA

OL(max)

(1)

(2)

(1)

(2)

(1)

(2)

(1)

(2)

, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop , for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

2.2 V

3 V

2.2 V

3 V

MIN MAX UNIT

VCC- 0.25 V

VCC- 0.6 V

VCC- 0.25 V

VCC- 0.6 V

SSVSS

Output Frequency (Ports P1, P2, P3, and P4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Px.y

Port_CLK

PARAMETER TEST CONDITIONS V

Port output frequency (with load) MHz

Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL= 20 pF

P1.4/SMCLK, CL= 20 pF, RL= 1 kΩ against VCC/2

(1)(2)

(2)

2.2 V 10 3 V 12

2.2 V 12 3 V 16

MIN TYP MAX UNIT

CC CC CC CC

+ 0.25

VSS+ 0.6

+ 0.25

VSS+ 0.6

MHz

(1) Alternatively, a resistive divider with two 2-kΩ resistors between VCCand VSSis used as load. The output is connected to the center tap

of the divider.

(2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

VOH− High-Level Output V oltage − V

−25.0

−20.0

−15.0

−10.0

−5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5

VCC= 2.2 V P4.5

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOH− High-Level Output V oltage − V

−50.0

−40.0

−30.0

−20.0

−10.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VCC= 3 V P4.5

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOL− Low-Level Output V oltage − V

0.0

5.0

10.0

15.0

20.0

25.0

0.0 0.5 1.0 1.5 2.0 2.5

VCC= 2.2 V P4.5

TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

VOL− Low-Level Output V oltage − V

0.0

10.0

20.0

30.0

40.0

50.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VCC= 3 V P4.5

TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT

vs vs

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

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Typical Characteristics - Outputs

One output loaded at a time.

Figure 4. Figure 5.

TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

Figure 6. Figure 7.

d(BOR)

(B_IT−)

hys(B_IT−)

CC(star t)

MSP430F22x2 MSP430F22x4

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POR/Brownout Reset (BOR)

(1) (2)

SLAS504G –JULY 2006–REVISED AUGUST 2012

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC(start)

(B_IT-)

hys(B_IT-)

d(BOR)

(reset)

PARAMETER TEST CONDITIONS V

See Figure 8 dVCC/dt ≤ 3 V/s V See Figure 8 through Figure 10 dVCC/dt ≤ 3 V/s 1.71 V

See Figure 8 dVCC/dt ≤ 3 V/s 70 130 210 mV See Figure 8 2000 µs Pulse length needed at RST/NMI pin

to accepted reset internally

3 V 2 µs

(1) The current consumption of the brownout module is already included in the ICCcurrent consumption data. The voltage level V

(2) During power up, the CPU begins code execution following a period of t

must not be changed until VCC≥ V

hys(B_IT-)

is ≤ 1.8 V.

CC(min)

, where V

after VCC= V

is the minimum supply voltage for the desired operating frequency.

CC(min)

d(BOR)

(B_IT-)

MIN TYP MAX UNIT

0.7 ×

(B_IT-)

+ V

hys(B_IT-)

. The default DCO settings

(B_IT-)

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

0.5

1.5

CC(drop)

tpw− Pulse Width − µs

CC(drop)

− V

3 V

0.001 1 1000

tpw− Pulse Width − µs

tf= t

Typical Conditions

VCC= 3 V

CC(drop)

3 V

0.5

1.5

0.001 1 1000

Typical Conditions

1 ns 1 ns

tpw− Pulse Width − µs

CC(drop)

− V

tpw− Pulse Width − µs

VCC= 3 V

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Typical Characteristics - POR/Brownout Reset (BOR)

Figure 9. V

CC(drop)

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Level With a Square Voltage Drop to Generate a POR/Brownout Signal

Figure 10. V

CC(drop)

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

DCO(RSEL,DCO) DCO(RSEL,DCO+1)

average

DCO(RSEL,DCO) DCO(RSEL,DCO+1)

32 × f × f

f =

MOD × f + (32 – MOD) × f

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Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.

• DCO control bits DCOx have a step size as defined by parameter S

• Modulation control bits MODx select how often f cycles. The frequency f

DCO(RSEL,DCO)

is used for the remaining cycles. The frequency is an average equal to:

DCO(RSEL,DCO+1)

DCO

is used within the period of 32 DCOCLK

DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

DCO(0,0)

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

RSEL

DCO

PARAMETER TEST CONDITIONS V

RSELx < 14 1.8 3.6

Supply voltage range RSELx = 14 2.2 3.6 V

RSELx = 15 3.0 3.6 DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V, 3 V 0.06 0.14 MHz DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V, 3 V 0.07 0.17 MHz DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V, 3 V 0.10 0.20 MHz DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V, 3 V 0.14 0.28 MHz DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V, 3 V 0.20 0.40 MHz DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V, 3 V 0.28 0.54 MHz DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V, 3 V 0.39 0.77 MHz DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V, 3 V 0.54 1.06 MHz DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V, 3 V 0.80 1.50 MHz DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V, 3 V 1.10 2.10 MHz DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V, 3 V 1.60 3.00 MHz DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V, 3 V 2.50 4.30 MHz DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V, 3 V 3.00 5.50 MHz DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V, 3 V 4.30 7.30 MHz DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V, 3 V 6.00 9.60 MHz DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V, 3 V 8.60 13.9 MHz DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 12.0 18.5 MHz DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 16.0 26.0 MHz Frequency step between

range RSEL and RSEL+1 Frequency step between tap

DCO and DCO+1

= f

RSEL

DCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

= f

DCO

DCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

2.2 V, 3 V 1.55 ratio

2.2 V, 3 V 1.05 1.08 1.12 ratio

Duty cycle Measured at P1.4/SMCLK 2.2 V, 3 V 40 50 60 %

MIN TYP MAX UNIT

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Calibrated DCO Frequencies - Tolerance at Calibration

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CAL(1MHz)

CAL(8MHz)

CAL(12MHz)

CAL(16MHz)

PARAMETER TEST CONDITIONS T

Frequency tolerance at calibration 25°C 3 V -1 ±0.2 +1 %

BCSCTL1 = CALBC1_1MHZ,

1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 3 V 0.990 1 1.010 MHz

Gating time: 5 ms BCSCTL1 = CALBC1_8MHZ,

8-MHz calibration value DCOCTL = CALDCO_8MHZ, 25°C 3 V 7.920 8 8.080 MHz

Gating time: 5 ms BCSCTL1 = CALBC1_12MHZ,

12-MHz calibration value DCOCTL = CALDCO_12MHZ, 25°C 3 V 11.88 12 12.12 MHz

Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ,

16-MHz calibration value DCOCTL = CALDCO_16MHZ, 25°C 3 V 15.84 16 16.16 MHz

Gating time: 2 ms

MIN TYP MAX UNIT

Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CAL(1MHz)

CAL(8MHz)

CAL(12MHz)

CAL(16MHz)

PARAMETER TEST CONDITIONS T

1-MHz tolerance over temperature

8-MHz tolerance over temperature

12-MHz tolerance over temperature

16-MHz tolerance over temperature

0°C to 85°C 3 V -2.5 ±0.5 +2.5 %

0°C to 85°C 3 V -2.5 ±1.0 +2.5 %

0°C to 85°C 3 V -3 ±2.0 +3 %

BCSCTL1 = CALBC1_1MHZ,

1-MHz calibration value DCOCTL = CALDCO_1MHZ, 0°C to 85°C 3 V 0.975 1 1.025 MHz

Gating time: 5 ms

BCSCTL1 = CALBC1_8MHZ,

8-MHz calibration value DCOCTL = CALDCO_8MHZ, 0°C to 85°C 3 V 7.8 8 8.2 MHz

Gating time: 5 ms

BCSCTL1 = CALBC1_12MHZ,

12-MHz calibration value DCOCTL = CALDCO_12MHZ, 0°C to 85°C 3 V 11.7 12 12.3 MHz

Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ, 3 V 15.52 16 16.48

16-MHz calibration value DCOCTL = CALDCO_16MHZ, 0°C to 85°C MHz

Gating time: 2 ms

MIN TYP MAX UNIT

2.2 V 0.97 1 1.03

3.6 V 0.97 1 1.03

2.2 V 7.76 8 8.4

3.6 V 7.6 8 8.24

2.2 V 11.7 12 12.3

3.6 V 11.7 12 12.3

3.6 V 15 16 16.48

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Calibrated DCO Frequencies - Tolerance Over Supply Voltage V

SLAS504G –JULY 2006–REVISED AUGUST 2012

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CAL(1MHz)

CAL(8MHz)

CAL(12MHz)

CAL(16MHz)

PARAMETER TEST CONDITIONS T

1-MHz tolerance over V 8-MHz tolerance over V 12-MHz tolerance over V 16-MHz tolerance over V

CC CC

25°C 1.8 V to 3.6 V -3 ±2 +3 % 25°C 1.8 V to 3.6 V -3 ±2 +3 % 25°C 2.2 V to 3.6 V -3 ±2 +3 % 25°C 3 V to 3.6 V -6 ±2 +3 %

BCSCTL1 = CALBC1_1MHZ, 1-MHz calibration value DCOCTL = CALDCO_1MHZ, 25°C 1.8 V to 3.6 V 0.97 1 1.03 MHz

Gating time: 5 ms

BCSCTL1 = CALBC1_8MHZ, 8-MHz calibration value DCOCTL = CALDCO_8MHZ, 25°C 1.8 V to 3.6 V 7.76 8 8.24 MHz

Gating time: 5 ms

BCSCTL1 = CALBC1_12MHZ, 12-MHz calibration value DCOCTL = CALDCO_12MHZ, 25°C 2.2 V to 3.6 V 11.64 12 12.36 MHz

Gating time: 5 ms

BCSCTL1 = CALBC1_16MHZ, 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 25°C 3 V to 3.6 V 15 16 16.48 MHz

Gating time: 2 ms

MIN TYP MAX UNIT

Calibrated DCO Frequencies - Overall Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS T

1-MHz tolerance I: -40°C to 85°C overall T: -40°C to 105°C

8-MHz tolerance I: -40°C to 85°C overall T: -40°C to 105°C

12-MHz I: -40°C to 85°C tolerance overall T: -40°C to 105°C

16-MHz I: -40°C to 85°C tolerance overall T: -40°C to 105°C

CAL(1MHz)

CAL(8MHz)

CAL(12MHz)

CAL(16MHz)

1-MHz I: -40°C to 85°C calibration value T: -40°C to 105°C

8-MHz I: -40°C to 85°C calibration value T: -40°C to 105°C

12-MHz I: -40°C to 85°C calibration value T: -40°C to 105°C

16-MHz I: -40°C to 85°C calibration value T: -40°C to 105°C

BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, 1.8 V to 3.6 V 0.95 1 1.05 MHz Gating time: 5 ms

BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, 1.8 V to 3.6 V 7.6 8 8.4 MHz Gating time: 5 ms

BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, 2.2 V to 3.6 V 11.4 12 12.6 MHz Gating time: 5 ms

BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, 3 V to 3.6 V 15 16 17 MHz Gating time: 2 ms

MIN TYP MAX UNIT

1.8 V to 3.6 V -5 ±2 +5 %

2.2 V to 3.6 V -5 ±2 +5 %

3 V to 3.6 V -6 ±3 +6 %

TA− Temperature − °C

0.97

0.98

0.99

1.00

1.01

1.02

1.03

−50.0 −25.0 0.0 25.0 50.0 75.0 100.0

Frequency − MHz

VCC= 1.8 V

VCC= 2.2 V

VCC= 3.0 V

VCC= 3.6 V

VCC− Supply Voltage − V

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.5 2.0 2.5 3.0 3.5 4.0

Frequency − MHz

TA= −40 °C

TA= 25 °C

TA= 85 °C

TA= 105 °C

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Typical Characteristics - Calibrated 1-MHz DCO Frequency

CALIBRATED 1-MHz FREQUENCY CALIBRATED 1-MHz FREQUENCY

vs vs

TEMPERATURE SUPPLY VOLTAGE

Figure 11. Figure 12.

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DCO Frequency − MHz

0.10

1.00

10.00

0.10 1.00 10.00

RSELx = 0...11

RSELx = 12...15

DCO Wake-Up Time − µs

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Wake-Up From Lower-Power Modes (LPM3/4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ

BCSCTL1 = CALBC1_8MHZ,

DCO,LPM3/4

CPU,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock

edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

DCO clock wake-up time from LPM3/4

CPU wake-up time from 1 / f LPM3/4

(1)

(2)

DCOCTL = CALDCO_8MHZ BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ

2.2 V, 3 V 1.5

3 V 1

MIN TYP MAX UNIT

µs

MCLK

Clock,LPM3/4

Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4

CLOCK WAKE-UP TIME FROM LPM3

DCO FREQUENCY

Figure 13.

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

−50.0 −25.0 0.0 25.0 50.0 75.0 100.0

TA− Temperature − C

DCO Frequency − MHz

OSC

= 100k

OSC

= 270k

OSC

= 1M

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.0 2.5 3.0 3.5 4.0

VCC− Supply Voltage − V

DCO Frequency − MHz

OSC

= 100k

OSC

= 270k

OSC

= 1M

0.01

0.10

1.00

10.00

10.00 100.00 1000.00 10000.00

OSC

− External Resistor − kW

DCO Frequency − MHz

RSELx = 4

0.01

0.10

1.00

10.00

10.00 100.00 1000.00 10000.00

OSC

− External Resistor − kW

DCO Frequency − MHz

RSELx = 4

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

DCO With External Resistor R

OSC

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

DCO,ROSC

(1) R

PARAMETER TEST CONDITIONS V

DCOR = 1, 2.2 V 1.8

DCO output frequency with R

Temperature drift 2.2 V, 3 V ±0.1 %/°C

Drift with V

= 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK= ±50 ppm/°C.

OSC

RSELx = 4, DCOx = 3, MODx = 0, MHz

OSC

TA= 25°C

3 V 1.95

DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0

2.2 V, 3 V 10 %/V

Typical Characteristics - DCO With External Resistor R

DCO FREQUENCY DCO FREQUENCY

vs vs

VCC= 2.2 V, TA= 25°C VCC= 3 V, TA= 25°C

OSC

MIN TYP MAX UNIT

OSC

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Figure 14. Figure 15.

DCO FREQUENCY DCO FREQUENCY

vs vs

TEMPERATURE SUPPLY VOLTAGE

VCC= 3 V TA= 25°C

Figure 16. Figure 17.

MSP430F22x2 MSP430F22x4

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Crystal Oscillator LFXT1, Low-Frequency Mode

(1)

SLAS504G –JULY 2006–REVISED AUGUST 2012

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LFXT1,LF

PARAMETER TEST CONDITIONS V

LFXT1 oscillator crystal frequency, LF mode 0, 1

XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz

LFXT1 oscillator logic level

LFXT1,LF,logic

square wave input frequency, XTS = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz LF mode

XTS = 0, LFXT1Sx = 0,

Oscillation allowance for LF crystals

f XTS = 0, LFXT1Sx = 0,

LFXT1,LF

= 32768 Hz, C

L,eff

= 6 pF

= 12 pF

XTS = 0, XCAPx = 0 1

L,eff

Integrated effective load capacitance, LF mode

(2)

XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 XTS = 0, Measured at P2.0/ACLK,

f XTS = 0, LFXT1Sx = 3

LFXT1,LF

= 32768 Hz

(4)

2.2 V, 3 V 10 10000 Hz

Fault,LF

Duty cycle, LF mode 2.2 V, 3 V 30 50 70 % Oscillator fault frequency,

LF mode

(3)

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the crystal that is used.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

MIN TYP MAX UNIT

500

200

kΩ

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER T

VLO

/dT VLO frequency temperature drift

VLO

/dV

VLO

VLO frequency 2.2 V, 3 V kHz

VLO frequency supply voltage drift

(1)

(2)

T: -40°C to 105°C

-40°C to 85°C 4 12 20 105°C 22

I: -40°C to 85°C

25°C 1.8 V to 3.6 V 4 %/V

(1) Calculated using the box method:

I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)] T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]

(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)

MIN TYP MAX UNIT

2.2 V, 3 V 0.5 %/°C

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Crystal Oscillator LFXT1, High-Frequency Mode

PARAMETER TEST CONDITIONS V

LFXT1,HF0

LFXT1,HF1

LFXT1,HF2

LFXT1,HF,logic

L,eff

Fault,HF

LFXT1 oscillator crystal frequency, HF mode 0

LFXT1 oscillator crystal frequency, HF mode 1

LFXT1 oscillator crystal frequency, HF mode 2

XTS = 1, LFXT1Sx = 0 1.8 V to 3.6 V 0.4 1 MHz

XTS = 1, LFXT1Sx = 1 1.8 V to 3.6 V 1 4 MHz

XTS = 1, LFXT1Sx = 2 2.2 V to 3.6 V 2 12 MHz

LFXT1 oscillator logic-level square-wave input frequency, HF XTS = 1, LFXT1Sx = 3 2.2 V to 3.6 V 0.4 12 MHz mode

XTS = 1, LFXT1Sx = 0, f

LFXT1,HF

= 1 MHz, 2700

= 15 pF

L,eff

Oscillation allowance for HF XTS = 1, LFXT1Sx = 1, crystals (see Figure 18 and f

Figure 19) C

LFXT1,HF

= 4 MHz, 800 Ω

= 15 pF

L,eff

XTS = 1, LFXT1Sx = 2,

Integrated effective load capacitance, HF mode

LFXT1,HF

(2)

XTS = 1

= 16 MHz, 300

= 15 pF

L,eff

(3)

XTS = 1, Measured at P2.0/ACLK, 40 50 60 f

Duty cycle, HF mode 2.2 V, 3 V %

LFXT1,HF

XTS = 1,

= 10 MHz

Measured at P2.0/ACLK, 40 50 60

Oscillator fault frequency

(4)

LFXT1,HF

XTS = 1, LFXT1Sx = 3

= 16 MHz

(1)

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MIN TYP MAX UNIT

1.8 V to 3.6 V 2 10

3 V to 3.6 V 2 16

1.8 V to 3.6 V 0.4 10

3 V to 3.6 V 0.4 16

1 pF

(5)

2.2 V, 3 V 30 300 kHz

(1) To improve EMI on the XT1 oscillator the following guidelines should be observed:

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is

recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should

always match the specification of the used crystal. (3) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and

frequencies in between might set the flag. (5) Measured with logic-level input frequency, but also applies to operation with crystals.

0.0

100.0

200.0

300.0

400.0

500.0

600.0

700.0

800.0

0.0 4.0 8.0 12.0 16.0 20.0

Crystal Frequency − MHz

XT Oscillator Supply Current − uA

LFXT1Sx = 1

LFXT1Sx = 3

LFXT1Sx = 2

Crystal Frequency − MHz

10.00

100.00

1000.00

10000.00

100000.00

0.10 1.00 10.00 100.00

Oscillation Allowance − Ohms

LFXT1Sx = 1

LFXT1Sx = 3

LFXT1Sx = 2

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)

OSCILLATION ALLOWANCE OSCILLATOR SUPPLY CURRENT

vs vs CRYSTAL FREQUENCY CRYSTAL FREQUENCY C

= 15 pF, TA= 25°C C

L,eff

= 15 pF, TA= 25°C

L,eff

Figure 18. Figure 19.

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TA,cap

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK 2.2 V 10

Timer_A clock frequency External: TACLK, INCLK MHz

Duty cycle = 50% ± 10%

3 V 16

Timer_A capture timing TA0, TA1, TA2 2.2 V, 3 V 20 ns

MIN TYP MAX UNIT

Timer_B

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TB,cap

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK 2.2 V 10

Timer_B clock frequency External: TACLK, INCLK MHz

Duty cycle = 50% ± 10%

3 V 16

Timer_B capture timing TB0, TB1, TB2 2.2 V, 3 V 20 ns

MIN TYP MAX UNIT

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

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USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER CONDITIONS V

Internal: SMCLK, ACLK

USCI

BITCLK

USCI input clock frequency External: UCLK f

Duty cycle = 50% ± 10%

BITCLK clock frequency (equals baud rate in MBaud)

UART receive deglitch time

(1)

2.2 V, 3 V 1 MHz

2.2 V 50 150 600 3 V 50 100 600

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode)

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20 and Figure 21)

PARAMETER TEST CONDITIONS V

USCI

SU,MI

HD,MI

VALID,MO

(1) f

For the slave's parameters t

USCI input clock frequency f

SOMI input data setup time ns

SOMI input data hold time ns

SIMO output data valid time ns

UCxCLK

= 1/2t

LO/HI

with t

LO/HI

USCI (SPI Slave Mode)

≥ max(t

SU,SI(Slave)

(1)

VALID,MO(USCI)

and t

VALID,SO(Slave)

SMCLK, ACLK Duty cycle = 50% ± 10%

UCLK edge to SIMO valid, CL= 20 pF

+ t

SU,SI(Slave)

, t

SU,MI(USCI)

, see the SPI parameters of the attached slave.

+ t

VALID,SO(Slave)

2.2 V 110 3 V 75

2.2 V 0 3 V 0

2.2 V 30 3 V 20

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 22 and Figure 23)

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

SU,SI

HD,SI

VALID,SO

(1) f

For the master's parameters t

STE lead time, STE low to clock 2.2 V, 3 V 50 ns STE lag time, Last clock to STE high 2.2 V, 3 V 10 ns STE access time, STE low to SOMI data out 2.2 V, 3 V 50 ns STE disable time, STE high to SOMI high

impedance

SIMO input data setup time ns

SIMO input data hold time ns

SOMI output data valid time ns

= 1/2t

UCxCLK

LO/HI

PARAMETER TEST CONDITIONS V

UCLK edge to SOMI valid, CL= 20 pF

with t

LO/HI

≥ max(t

VALID,MO(Master)

SU,MI(Master)

and t

VALID,MO(Master)

+ t

SU,SI(USCI)

, t

SU,MI(Master)

refer to the SPI parameters of the attached slave.

+ t

VALID,SO(USCI)

2.2 V, 3 V 50 ns

2.2 V 20

3 V 15

2.2 V 10

3 V 10

2.2 V 75 110

3 V 50 75

MIN TYP MAX UNIT

SYSTEM

MIN TYP MAX UNIT

SYSTEM

MIN TYP MAX UNIT

MHz

UCLK

CKPL=0

CKPL=1

SIMO

1/f

UCxCLK

LO/HItLO/HI

SOMI

SU,MI

HD,MI

VALID,MO

UCLK

CKPL=0

CKPL=1

SIMO

1/f

UCxCLK

LO/HItLO/HI

SOMI

SU,MI

HD,MI

VALID,MO

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Figure 20. SPI Master Mode, CKPH = 0

Figure 21. SPI Master Mode, CKPH = 1

STE

UCLK

CKPL=0

CKPL=1

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

LO/HItLO/HI

SU,SI

HD,SI

VALID,SO

SOMI

SIMO

1/f

UCxCLK

STE

UCLK

CKPL=0

CKPL=1

SOMI

STE,ACC

STE,DIS

1/f

UCxCLK

LO/HItLO/HI

SIMO

SU,SI

HD,SI

VALID,SO

STE,LEAD

STE,LAG

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

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Figure 22. SPI Slave Mode, CKPH = 0

Figure 23. SPI Slave Mode, CKPH = 1

SDA

SCL

1/f

SCL

HD,DAT

SU,DAT

HD,STA

SU,STAtHD,STA

SU,STO

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)

USCI

SCL

HD,STA

SU,STA

HD,DAT

SU,DAT

SU,STO

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI input clock frequency External: UCLK f

Duty cycle = 50% ± 10%

SCL clock frequency 2.2 V, 3 V 0 400 kHz

≤ 100 kHz 4

Hold time (repeated) START 2.2 V, 3 V µs

Setup time for a repeated START 2.2 V, 3 V µs

SCL

> 100 kHz 0.6

SCL

≤ 100 kHz 4.7

SCL

> 100 kHz 0.6

SCL

Data hold time 2.2 V, 3 V 0 ns Data setup time 2.2 V, 3 V 250 ns Setup time for STOP 2.2 V, 3 V 4 µs

Pulse width of spikes suppressed by input filter ns

2.2 V 50 150 600 3 V 50 100 600

MIN TYP MAX UNIT

SYSTEM

MHz

Figure 24. I2C Mode Timing

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS T

Analog supply voltage

range Analog input voltage

range

ADC10 supply current

ADC10

VSS= 0 V 2.2 3.6 V All Ax terminals,

(2)

Analog inputs selected in 0 V ADC10AE register

ADC10CLK

ADC10ON = 1, REFON = 0,

(3)

ADC10SHT0 = 1, mA

= 5 MHz, 2.2 V 0.52 1.05

ADC10SHT1 = 0,

(1)

I: -40°C to 85°C

T: -40°C to 105°C

(1)

MIN TYP MAX UNIT

3 V 0.6 1.2

ADC10DIV = 0

REF+

ADC10CLK

Reference supply current, reference buffer mA disabled

(4)

ADC10ON = 0, REF2_5V = 0, 2.2 V, 3 V 0.25 0.4 REFON = 1, REFOUT = 0

ADC10CLK

ADC10ON = 0, REF2_5V = 1, 3 V 0.25 0.4

= 5 MHz,

I: -40°C to 85°C

T: -40°C to 105°C

REFON = 1, REFOUT = 0

REFB,0

REFB,1

Reference buffer supply current with mA ADC10SR = 0

(4)

Reference buffer supply current with mA ADC10SR = 1

(4)

Input capacitance 27 pF Input MUX ON I: -40°C to 85°C

resistance T: -40°C to 105°C

ADC10CLK

ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR = 0

ADC10CLK

ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR = 1

Only one terminal Ax selected at I: -40°C to 85°C a time T: -40°C to 105°C

0 V ≤ VAx≤ V

= 5 MHz -40°C to 85°C 2.2 V, 3 V 1.1 1.4

105°C 2.2 V, 3 V 1.8

= 5 MHz, -40°C to 85°C 2.2 V, 3 V 0.5 0.7

105°C 2.2 V, 3 V 0.8

2.2 V, 3 V 2000 Ω

(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter. (2) The analog input voltage range must be within the selected reference voltage range VR+to VR-for valid conversion results. (3) The internal reference supply current is not included in current consumption parameter I (4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a

ADC10

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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SLAS504G –JULY 2006–REVISED AUGUST 2012

10-Bit ADC, Built-In Voltage Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC,REF+

REF+

LD,VREF+

PARAMETER TEST CONDITIONS V

≤ 1 mA, REF2_5V = 0 2.2

Positive built-in reference analog I supply voltage range

Positive built-in reference voltage

Maximum V load current

REF+

regulation

REF+

load

VREF+

≤ 0.5 mA, REF2_5V = 1 2.8 V

VREF+

≤ 1 mA, REF2_5V = 1 2.9

VREF+

≤ I

VREF+

Analog input voltage VAx≈ 0.75 V, 2.2 V, 3 V ±2

max, REF2_5V = 0 2.2 V, 3 V 1.41 1.5 1.59

VREF+

≤ I

max, REF2_5V = 1 3 V 2.35 2.5 2.65

VREF+

= 500 µA ± 100 µA,

REF2_5V = 0 I

= 500 µA ± 100 µA,

VREF+

Analog input voltage VAx≈ 1.25 V, 3 V ±2

2.2 V ±0.5 3 V ±1

REF2_5V = 1 I

= 100 µA to 900 µA, ADC10SR = 0 400

VREF+

VAx≈ 0.5 x V Error of conversion result ≤1 LSB

≤ ±1 mA,

VREF+

REFON = 1, REFOUT = 1

= constant with

VREF+

0 mA ≤ I

VREF+

= 0.5 mA, REF2_5V = 0,

VREF+

REFON = 0 to 1 I

= 0.5 mA, ADC10SR = 0 1

VREF+

REF2_5V = 0, REFON = 1, REFBURST = 1

(3)

= 0.5 mA, ADC10SR = 0 2

VREF+

REF2_5V = 1, REFON = 1, REFBURST = 1

REF+

≤ 1 mA

ADC10SR = 1 2000

2.2 V, 3 V ±100 ppm/°C

ADC10SR = 1 2.5

ADC10SR = 1 4.5

2.2 V

3 V

VREF+

CREF+

REFON

REFBURST

load

REF+

regulation response 3 V ns time

Maximum capacitance at pin 2.2 V, 3 V 100 pF

(1)

REF+

Temperature I coefficient

(2)

Settling time of internal reference 3.6 V 30 µs

(3)

voltage

Settling time of reference buffer

(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA 2/A4/V

must be limited; the reference buffer may become unstable otherwise.

(2) Calculated using the box method:

I temperature: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) T temperature: (MAX(-40 to 105°C) – MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C – (–40°C))

(3) The condition is that the error in a conversion started after t

REFON

or t

is less than ±0.5 LSB.

RefBuf

MIN TYP MAX UNIT

/ V

REF+

(REFOUT = 1),

eREF+

LSB

µs

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

10-Bit ADC, External Reference

(1)

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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

eREF+

eREF-

ΔV

eREF

VeREF+

VeREF-

PARAMETER TEST CONDITIONS V

> V

eREF-

≤ VCC- 0.15 V,

eREF+

> V

eREF-

> V

eREF-

(5)

eREF-

≤ VCC,

eREF+

≤ VCC- 0.15 V ≤ 3 V,

eREF+

≤ V

(3)

Positive external reference input voltage range

Negative external reference input voltage range

(2)

(4)

Differential external reference input voltage range V ΔV

= V

eREF

Static input current into V

eREF+

- V

eREF-

eREF+

eREF-

eREF+

SREF1 = 1, SREF0 = 0 V

≤ V

eREF-

SREF1 = 1, SREF0 = 1 V

eREF+

0 V ≤ V SREF1 = 1, SREF0 = 0

0 V ≤ V SREF1 = 1, SREF0 = 1

0 V ≤ V

2.2 V, 3 V µA

2.2 V, 3 V ±1 µA

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current I

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

. The current consumption can be limited to the sample and conversion period with REBURST = 1.

REFB

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

MIN MAX UNIT

1.4 V

1.4 3

0 1.2 V

1.4 V

±1

10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

ADC10CLK

ADC10OSC

ADC10 input clock For specified performance of frequency ADC10 linearity parameters

ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0, frequency f

ADC10CLK

= f

ADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0,

CONVERT

ADC10ON

Conversion time µs

Turn on settling time of the ADC

(1)

ADC10CLK

ADC10SSELx ≠ 0 1 / f

= f

ADC10OSC

from ACLK, MCLK or SMCLK, 13 × ADC10DIVx ×

(1) The condition is that the error in a conversion started after t

settled.

ADC10ON

ADC10SR = 0 0.45 6.3 ADC10SR = 1 0.45 1.5

2.2 V, 3 V MHz

2.2 V, 3 V 3.7 6.3 MHz

2.2 V, 3 V 2.06 3.51

is less than ±0.5 LSB. The reference and input signal are already

MIN TYP MAX UNIT

ADC10CLK

100 ns

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

10-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

E E E

Integral linearity error 2.2 V, 3 V ±1 LSB

Differential linearity error 2.2 V, 3 V ±1 LSB

Offset error Source impedance RS< 100 Ω 2.2 V, 3 V ±1 LSB

SREFx = 010, unbuffered external reference, V

= 1.5 V

eREF+

SREFx = 010, unbuffered external reference, V

= 2.5 V

Gain error LSB

eREF+

SREFx = 011, buffered external reference V

= 1.5 V

eREF+

SREFx = 011, buffered external reference V

= 2.5 V

eREF+

SREFx = 010, unbuffered external reference, V

= 1.5 V

eREF+

SREFx = 010, unbuffered external reference, V

= 2.5 V

Total unadjusted error LSB

eREF+

SREFx = 011, buffered external reference V

= 1.5 V

eREF+

SREFx = 011, buffered external reference V

= 2.5 V

eREF+

(1) The reference buffer offset adds to the gain and total unadjusted error.

2.2 V ±1.1 ±2

3 V ±1.1 ±2

(1)

2.2 V ±1.1 ±4

3 V ±1.1 ±3

2.2 V ±2 ±5

3 V ±2 ±5

(1)

2.2 V ±2 ±7

3 V ±2 ±6

MIN TYP MAX UNIT

10-Bit ADC, Temperature Sensor and Built-In V

MID

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

SENSOR

Offset,Sensor

Temperature sensor supply REFON = 0, INCHx = 0Ah,

(1)

current

TA= 25°C ADC10ON = 1, INCHx = 0Ah

Sensor offset voltage ADC10ON = 1, INCHx = 0Ah

(2) (2)

Temperature sensor voltage at TA= 105°C (T version only)

SENSOR

Sensor output voltage

(3)

Temperature sensor voltage at TA= 85°C 1195 1295 1395 Temperature sensor voltage at TA= 25°C 985 1085 1185 Temperature sensor voltage at TA= 0°C 895 995 1095

SENSOR(sample)

VMID

MID

VMID(sample)

(1) The sensor current I

high).When REFON = 1, I input (INCH = 0Ah).

Sample time required if ADC10ON = 1, INCHx = 0Ah, channel 10 is selected

Current into divider at channel 11

(4)

VCCdivider at channel 11 V

Sample time required if ADC10ON = 1, INCHx = 0Bh, channel 11 is selected

is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is

SENSOR

(4)

(5)

is included in I

Error of conversion result ≤ 1 LSB

ADC10ON = 1, INCHx = 0Bh µA

ADC10ON = 1, INCHx = 0Bh, V

≈ 0.5 × V

MID

Error of conversion result ≤ 1 LSB

.When REFON = 0, I

REF+

applies during conversion of the temperature sensor

SENSOR

(2) The following formula can be used to calculate the temperature sensor output voltage:

Sensor,typ

(3) Results based on characterization and/or production test, not TC (4) No additional current is needed. The V (5) The on time, t

= TC = TC

( 273 + T [°C] ) + V

Sensor

T [°C] + V

Sensor

, is included in the sampling time, t

VMID(on)

Sensor(TA

MID

Offset,sensor

= 0°C) [mV]

[mV] or

is used during sampling.

VMID(sample)

or V

Sensor

Offset,sensor

; no additional on time is needed.

2.2 V 40 120 3 V 60 160

2.2 V, 3 V 3.44 3.55 3.66 mV/°C

2.2 V, 3 V mV

2.2 V, 3 V 30 µs

2.2 V N/A 3 V N/A

2.2 V 1.06 1.1 1.14 3 V 1.46 1.5 1.54

2.2 V 1400 3 V 1220

MIN TYP MAX UNIT

-100 100 mV

1265 1365 1465

µA

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

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Operational Amplifier (OA) Supply Specifications (MSP430F22x4 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Supply voltage range 2.2 3.6 V

Fast Mode 180 290

Supply current

(1)

Medium Mode 2.2 V, 3 V 110 190 µA Slow Mode 50 80

PSRR Power-supply rejection ratio Noninverting 2.2 V, 3 V 70 dB

(1) Corresponding pins configured as OA inputs and outputs, respectively.

MIN TYP MAX UNIT

Operational Amplifier (OA) Input/Output Specifications (MSP430F22x4 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

I/P

Input voltage range -0.1 VCC- 1.2 V

TA= -40 to +55°C -5 ±0.5 5

lkg

Input leakage

(1) (2)

current

TA= +55 to +85°C 2.2 V, 3 V -20 ±5 20 nA TA= +85 to +105°C -50 50 Fast Mode 50 Medium Mode f

Voltage noise density, I/P

Slow Mode 140 Fast Mode 30 Medium Mode f

= 1 kHz 80

V(I/P)

= 10 kHz 50

V(I/P)

Slow Mode 65

O/P(OAx)

CMRR Noninverting 2.2 V, 3 V 70 dB

Offset voltage, I/P 2.2 V, 3 V ±10 mV Offset temperature

(3)

drift, I/P Offset voltage drift 0.3 V ≤ VIN≤ VCC- 1.0 V

with supply, I/P ΔVCC≤ ±10%, TA= 25°C High-level output

voltage, O/P Low-level output

voltage, O/P

Output resistance

(4)

(see Figure 25) V

Fast Mode, I Slow Mode, I Fast Mode, I Slow Mode, I R

= 3 kΩ, C

Load

V R

0.2 V ≤ V

O/P(OAx)

= 3 kΩ, C

Load

O/P(OAx)

= 3 kΩ, C

Load

< 0.2 V

> VCC- 1.2 V

O/P(OAx)

≤ -500 µA VCC- 0.2 V

SOURCE

≤ -150 µA VCC- 0.1 V

SOURCE

≤ 500 µA V

SOURCE

≤ 150 µA V

SOURCE

= 50 pF,

Load

= 50 pF,

Load

= 50 pF,

Load

≤ VCC- 0.2 V

2.2 V, 3 V ±10 µV/°C

2.2 V, 3 V ±1.5 mV/V

2.2 V, 3 V V

2.2 V, 3 V 150 250 Ω

Common-mode rejection ratio

(1) ESD damage can degrade input current leakage. (2) The input bias current is overridden by the input leakage current. (3) Calculated using the box method (4) Specification valid for voltage-follower OAx configuration

MIN TYP MAX UNIT

nV/√Hz

CC SS SS

0.2

0.1

150 250

0.1 4

Input Frequency − kHz

−250

−200

−150

−100

−50

1 10 100 1000 10000 100000

Phase − degrees

Slow Mode

Fast Mode

Medium Mode

Input Frequency − kHz

−80

−60

−40

−20

100

120

140

1 10 100 1000 10000 100000

Slow Mode

Fast Mode

Gain − dB

Medium Mode

O/P(OAx)

Max

0.2V AV

AVCC−0.2V

OUT

Min

Load

OAx

O/P(OAx)

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Figure 25. OAx Output Resistance Tests

Operational Amplifier (OA) Dynamic Specifications (MSP430F22x4 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Fast Mode 1.2

SR Slew rate Medium Mode 0.8 V/µs

Slow Mode 0.3

Open-loop voltage gain 100 dB

φm Phase margin CL= 50 pF 60 deg

Gain margin CL= 50 pF 20 dB

Noninverting, Fast Mode, RL= 47 kΩ, CL= 50 pF

GBW 2.2 V, 3 V 1.4 MHz

t t

Gain-bandwidth product Noninverting, Medium Mode, (see Figure 26 and Figure 27) RL= 300 kΩ, CL= 50 pF

Noninverting, Slow Mode, RL= 300 kΩ, CL= 50 pF

Enable time on ton, noninverting, Gain = 1 2.2 V, 3 V 10 20 µs

en(on)

Enable time off 2.2 V, 3 V 1 µs

en(off)

MIN TYP MAX UNIT

2.2

0.5

TYPICAL OPEN-LOOP GAIN TYPICAL PHASE

vs vs

FREQUENCY FREQUENCY

Figure 26. Figure 27.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Operational Amplifier OA Feedback Network, Resistor Network (MSP430F22x4 Only)

www.ti.com

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

R R

(1) A single resistor string is composed of 4 R (2) For the matching (that is, the relative accuracy) of the unit resistors on a device, see the gain and level specifications of the respective

Total resistance of resistor string 76 96 128 kΩ

total

Unit resistor of resistor string

unit

(2)

unit

+ 4 R

unit

+ 2 R

unit

+ 2 R

unit

+ 1 R

unit

+ 1 R

unit

+ 1 R

unit

configurations.

MIN TYP MAX UNIT

4.8 6 8 kΩ

+ 1 R

unit

= 16 R

unit

= R

total

Operational Amplifier (OA) Feedback Network, Comparator Mode (OAFCx = 3) (MSP430F22x4 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

OAFBRx = 1, OARRIP = 0 0.245 0.25 0.255 OAFBRx = 2, OARRIP = 0 0.495 0.5 0.505 OAFBRx = 3, OARRIP = 0 0.619 0.625 0.631 OAFBRx = 4, OARRIP = 0 N/A OAFBRx = 5, OARRIP = 0 N/A OAFBRx = 6, OARRIP = 0 N/A

Comparator level 2.2 V, 3 V V

Level

OAFBRx = 7, OARRIP = 0 N/A OAFBRx = 1, OARRIP = 1 0.061 0.0625 0.065 OAFBRx = 2, OARRIP = 1 0.122 0.125 0.128 OAFBRx = 3, OARRIP = 1 0.184 0.1875 0.192 OAFBRx = 4, OARRIP = 1 0.245 0.25 0.255 OAFBRx = 5, OARRIP = 1 0.367 0.375 0.383 OAFBRx = 6, OARRIP = 1 0.495 0.5 0.505 OAFBRx = 7, OARRIP = 1 N/A Fast Mode, Overdrive 10 mV 40 Fast Mode, Overdrive 100 mV 4 Fast Mode, Overdrive 500 mV 3 Medium Mode, Overdrive 10 mV 60

, Propagation delay

PLH

(low-high and high-low)

PHL

Medium Mode, Overdrive 100 mV 2.2 V, 3 V 6 µs Medium Mode, Overdrive 500 mV 5 Slow Mode, Overdrive 10 mV 160 Slow Mode, Overdrive 100 mV 20 Slow Mode, Overdrive 500 mV 15

(1) The level is not available due to the analog input voltage range of the operational amplifier.

MIN TYP MAX UNIT

(1) (1) (1) (1)

(1)

MSP430F22x2 MSP430F22x4

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Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4) (MSP430F22x4 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

OAFBRx = 0 0.998 1 1.002 OAFBRx = 1 1.328 1.334 1.340 OAFBRx = 2 1.985 2.001 2.017

G Gain 2.2 V, 3 V

THD Total harmonic distortion/nonlinearity All gains dB

Settling time

Settle

(1) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

settling time of the amplifier itself might be faster.

Operational Amplifier (OA) Feedback Network, Inverting Amplifier Mode (OAFCx = 6) (MSP430F22x4 Only)

(1)

OAFBRx = 3 2.638 2.667 2.696 OAFBRx = 4 3.94 4 4.06 OAFBRx = 5 5.22 5.33 5.44 OAFBRx = 6 7.76 7.97 8.18 OAFBRx = 7 15 15.8 16.6

All power modes 2.2 V, 3 V 7 12 µs

2.2 V -60 3 V -70

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

OAFBRx = 1 -0.345 -0.335 -0.325 OAFBRx = 2 -1.023 -1.002 -0.979 OAFBRx = 3 -1.712 -1.668 -1.624

G Gain OAFBRx = 4 2.2 V, 3 V -3.1 -3 -2.9

OAFBRx = 5 -4.51 -4.33 -4.15 OAFBRx = 6 -7.37 -6.97 -6.57 OAFBRx = 7 -16.3 -14.8 -13.1

THD Total harmonic distortion/nonlinearity All gains dB

Settling time

Settle

(1) This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx. (2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

settling time of the amplifier itself might be faster.

(2)

All power modes 2.2 V, 3 V 7 12 µs

2.2 V -60 3 V -70

MIN TYP MAX UNIT

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

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Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC (PGM/ERASE)

FTG

PGM

ERASE

CPT

CMErase

PARAMETER TEST CONDITIONS V

Program and erase supply voltage 2.2 3.6 V Flash timing generator frequency 257 476 kHz Supply current from VCCduring program 2.2 V, 3.6 V 1 5 mA Supply current from VCCduring erase 2.2 V, 3.6 V 1 7 mA Cumulative program time

(1)

Cumulative mass erase time 2.2 V, 3.6 V 20 ms

2.2 V, 3.6 V 10 ms

Program/Erase endurance 10

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Seg Erase

Data retention duration TJ= 25°C 100 years Word or byte program time Block program time for first byte or word Block program time for each additional

byte or word Block program end-sequence wait time Mass erase time Segment erase time

(2) (2)

(2)

(2) (2) (2)

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the flash controller's state machine (t

FTG

= 1/f

FTG

MIN TYP MAX UNIT

30 t 25 t

18 t

6 t

10593 t

4819 t

cycles

FTG FTG

FTG

FTG FTG FTG

RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(RAMh)

RAM retention supply voltage

(1) This parameter defines the minimum supply voltage VCCwhen the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

(1)

CPU halted 1.6 V

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

SBW

SBW,Low

SBW,En

SBW,Ret

TCK

Internal

Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz Spy-Bi-Wire low clock pulse length 2.2 V, 3 V 0.025 15 µs Spy-Bi-Wire enable time

(TEST high to acceptance of first clock edge

(1)

)

Spy-Bi-Wire return to normal operation time 2.2 V, 3 V 15 100 µs

TCK input frequency

(2)

Internal pulldown resistance on TEST 2.2 V, 3 V 25 60 90 kΩ

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t

applying the first SBWCLK clock edge.

(2) f

JTAG Fuse

may be restricted to meet the timing requirements of the module selected.

TCK

(1)

time after pulling the TEST/SBWCLK pin high before

SBW,En

2.2 V, 3 V 1 µs

2.2 V 0 5 MHz 3 V 0 10 MHz

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

CC(FB)

Supply voltage during fuse-blow condition TA= 25°C 2.5 V Voltage level on TEST for fuse blow 6 7 V Supply current into TEST during fuse blow 100 mA Time to blow fuse 1 ms

MIN TYP MAX UNIT

(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

Direction 0: Input 1: Output

P1SEL.x

P1DIR.x

P1IN.x

P1IRQ.x

Module X IN

Module X OUT

P1OUT.x

Interrupt

Edge

Select

Set

P1SEL.x

P1IES.x

P1IFG.x

P1IE.x

P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2

DVSS

DVCC

P1REN.x

Pad Logic

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

APPLICATION INFORMATION

Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger

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Table 21. Port P1 (P1.0 to P1.3) Pin Functions

PIN NAME (P1.x) x FUNCTION

(1)

P1.0

P1.0/TACLK/ADC10CLK 0 Timer_A3.TACLK 0 1

ADC10CLK 1 1

(1)

P1.1

(I/O) I: 0; O: 1 0

P1.1/TA0 1 Timer_A3.CCI0A 0 1

P1.2/TA1 2 Timer_A3.CCI1A 0 1

P1.3/TA2 3 Timer_A3.CCI2A 0 1

(1) Default after reset (PUC/POR)

Timer_A3.TA0 1 1

(1)

P1.2

(I/O) I: 0; O: 1 0

Timer_A3.TA1 1 1

(1)

P1.3

(I/O) I: 0; O: 1 0

Timer_A3.TA2 1 1

CONTROL BITS/SIGNALS

P1DIR.x P1SEL.x

I: 0; O: 1 0

Bus

Keeper

Direction 0: Input 1: Output

P1SEL.x

P1DIR.x

P1IN.x

P1IRQ.x

Module X IN

Module X OUT

P1OUT.x

Interrupt

Edge

Select

Set

P1SEL.x

P1IES.x

P1IFG.x

P1IE.x

P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI

DVSS

DVCC

P1REN.x

To JTAG

From JTAG

Pad Logic

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Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access Features

PIN NAME (P1.x) x FUNCTION

P1.4/SMCLK/TCK 4 SMCLK 1 1 0

P1.5/TA0/TMS 5 Timer_A3.TA0 1 1 0

P1.6/TA1/TDI/TCLK 6 Timer_A3.TA1 1 1 0

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Function controlled by JTAG

P1.4

TCK X X 1 P1.5

TMS X X 1 P1.6

TDI/TCLK

Table 22. Port P1 (P1.4 to P1.6) Pin Functions

(2)

(I/O) I: 0; O: 1 0 0

(2)

(I/O) I: 0; O: 1 0 0

(2)

(I/O) I: 0; O: 1 0 0

(3)

CONTROL BITS/SIGNALS

P1DIR.x P1SEL.x 4-Wire JTAG

X X 1

(1)

From JTAG

From JTAG (TDO)

Bus

Keeper

Direction 0: Input 1: Output

P1SEL.7

P1DIR.7

P1IN.7

P1IRQ.7

Module X IN

Module X OUT

P1OUT.7

Interrupt

Edge

Select

Set

P1SEL.7

P1IES.7

P1IFG.7

P1IE.7

P1.7/TA2/TDO/TDI

DVSS

DVCC

P1REN.7

To JTAG

From JTAG

Pad Logic

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

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Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Function controlled by JTAG

PIN NAME (P1.x) x FUNCTION

P1.7/TA2/TDO/TDI 7 Timer_A3.TA2 1 1 0

Table 23. Port P1 (P1.7) Pin Functions

(2)

P1.7

(I/O) I: 0; O: 1 0 0

TDO/TDI

(3)

CONTROL BITS/SIGNALS

P1DIR.x P1SEL.x 4-Wire JTAG

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.x

P2DIR.x

P2IN.x

P2IRQ.x

Module X IN

Module X OUT

P2OUT.x

Interrupt

Edge

Select

Set

P2SEL.x

P2IES.x

P2IFG.x

P2IE.x

P2.0/ACLK/A0/OA0I0 P2.2/TA0/A2/OA0I1

DVSS

DVCC

P2REN.x

ADC10AE0.y

Pad Logic

INCHx = y

To ADC10

OA0

−

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger

Pin Name (P2.x) x y FUNCTION

P2.0/ACLK/A0/OA0I0 0 0 ACLK 1 1 0

P2.2/TA0/A2/OA0I1 2 2

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Table 24. Port P2 (P2.0, P2.2) Pin Functions

(2)

P2.0

(I/O) I: 0; O: 1 0 0

A0/OA0I0 P2.2 Timer_A3.CCI0B 0 1 0 Timer_A3.TA0 1 1 0 A2/OA0I1

(3)

(2)

(I/O) I: 0; O: 1 0 0

(3)

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

X X 1

(1)

OAFCx

OAPMx

OAADCx

To OA0 Feedback Network

(OAADCx = 10 or OAFCx = 000) and OAPMx> 00

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.1

P2DIR.1

P2IN.1

P2IRQ.1

Module X IN

Module X OUT

P2OUT.1

Interrupt

Edge

Select

Set

P2SEL.1

P2IES.1

P2IFG.1

P2IE.1

P2.1/TAINCLK/SMCLK/ A1/OA0O

DVSS

DVCC

P2REN.1

ADC10AE0.1

Pad Logic

INCHx = 1

To ADC10

OA0

−

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger

www.ti.com

PIN NAME (P2.x) x y FUNCTION

P2.1/TAINCLK/SMCLK/ A1/OA0O

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Table 25. Port P2 (P2.1) Pin Functions

(2)

P2.1

(I/O) I: 0; O: 1 0 0

Timer_A3.INCLK 0 1 0

1 1

SMCLK 1 1 0 A1/OA0O

(3)

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.3

P2DIR.3

P2IN.3

P2IRQ.3

Module X IN

Module X OUT

P2OUT.3

Interrupt

Edge

Select

Set

P2SEL.3

P2IES.3

P2IFG.3

P2IE.3

DVSS

DVCC

P2REN.3

ADC10AE0.3

Pad Logic

INCHx = 3

To ADC 10

OA1

−

OAFCx

OAPMx

OAADCx

To OA1 Feedback Network

To ADC10 V

R−

SREF2

VSS

P2.3/TA1/ A3/VREF−/VeREF−/ OA1I1/OA1O

(OAADCx = 10 or OAFCx = 000) and OAPMx > 00

MSP430F22x2 MSP430F22x4

www.ti.com

Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

Table 26. Port P2 (P2.3) Pin Functions

PIN NAME (P2.x) x y FUNCTION

(2)

P2.3

(I/O) I: 0; O: 1 0 0

P2.3/TA1/A3/V /V

eREF-

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

REF-

/ OA1I1/OA1O

Timer_A3.CCI1B 0 1 0

3 3

Timer_A3.TA1 1 1 0 A3/V

REF-/VeREF-

/OA1I1/OA1O

(3)

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.4

P2DIR.4

P2IN.4

P2IRQ.4

Module X IN

Module X OUT

P2OUT.4

Interrupt

Edge

Select

Set

P2SEL.4

P2IES.4

P2IFG.4

P2IE.4

P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0

DVSS

DVCC

P2REN.4

ADC10AE0.4

Pad Logic

INCHx = 4

To ADC10

To/from ADC10

positive reference

OA1

−

MSP430F22x2 MSP430F22x4

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Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger

SLAS504G –JULY 2006–REVISED AUGUST 2012

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

PIN NAME (P2.x) x y FUNCTION

P2.4/TA2/A4/V V

eREF+

applying analog signals.

/ OA1I0

REF+

Table 27. Port P2 (P2.4) Pin Functions

(2)

P2.4

(I/O) I: 0; O: 1 0 0

4 4 Timer_A3.TA2 1 1 0

A4/V

REF+/VeREF+

/OA1I0

(3)

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x ADC10AE0.y

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.x

P2DIR.x

P2IN.x

P2IRQ.x

Module X IN

Module X OUT

P2OUT.x

Interrupt

Edge

Select

Set

P2SEL.x

P2IES.x

P2IFG.x

P2IE.x

P2.5/ROSC

DVSS

DVCC

P2REN.x

DCOR

Pad Logic

To DCO

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External R

OSC

www.ti.com

for DCO

Table 28. Port P2 (P2.5) Pin Functions

PIN NAME (P2.x) x FUNCTION

(2)

P2.5

(I/O) I: 0; O: 1 0 0

(3)

N/A

OSC

P2.5/R

OSC

(1) X = Don't care (2) Default after reset (PUC/POR) (3) N/A = Not available or not applicable

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x DCOR

0 1 0 1 1 0 X X 1

(1)

LFXT1 off

P2SEL.7

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.6

P2DIR.6

P2IN.6

P2IRQ.6

Module X IN

Module X OUT

P2OUT.6

Interrupt

Edge

Select

Set

P2SEL.6

P2IES.6

P2IFG.6

P2IE.6

P2.6/XIN

DVSS

DVCC

P2REN.6

Pad Logic

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

P2.7/XOUT

LFXT1CLK

MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input

PIN NAME (P2.x) x FUNCTION

P2.6/XIN 6

(1) X = Don't care (2) Default after reset (PUC/POR)

P2.6 (I/O) I: 0; O: 1 0 XIN

(2)

Table 29. Port P2 (P2.6) Pin Functions

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x

X 1

(1)

LFXT1 off

P2SEL.6

Bus

Keeper

Direction 0: Input 1: Output

P2SEL.7

P2DIR.7

P2IN.7

P2IRQ.7

Module X IN

Module X OUT

P2OUT.7

Interrupt

Edge

Select

Set

P2SEL.7

P2IES.7

P2IFG.7

P2IE.7

P2.7/XOUT

DVSS

DVCC

P2REN.7

Pad Logic

LFXT1 Oscillator

BCSCTL3.LFXT1Sx = 11

LFXT1CLK

From P2.6/XIN

P2.6/XIN

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output

PIN NAME (P2.x) x FUNCTION

XOUT/P2.7 7

(1) X = Don't care (2) Default after reset (PUC/POR) (3) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this

pin after reset.

P2.7 (I/O) I: 0; O: 1 0 XOUT

Table 30. Port P2 (P2.7) Pin Functions

(2) (3)

CONTROL BITS/SIGNALS

P2DIR.x P2SEL.x

X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P3SEL.0

P3DIR.0

P3IN.0

Module X IN

Module X OUT

P3OUT.0

DVSS

DVCC

P3REN.0

ADC10AE0.5

Pad Logic

INCHx = 5

To ADC10

USCI Direction

Control

P3.0/UCB0STE/UCA0CLK/A5

MSP430F22x2 MSP430F22x4

www.ti.com

Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 31. Port P3 (P3.0) Pin Functions

PIN NAME (P1.x) x y FUNCTION

(2)

P3.0 P3.0/UCB0STE/ UCA0CLK/A5

(1) X = Don't care (2) Default after reset (PUC/POR) (3) The pin direction is controlled by the USCI module. (4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to

3-wire SPI mode if 4-wire SPI mode is selected.

(5) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

0 5 UCB0STE/UCA0CLK

(I/O) I: 0; O: 1 0 0

(3) (4)

(5)

CONTROL BITS/SIGNALS

P3DIR.x P3SEL.x ADC10AE0.y

X 1 0 X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P3SEL.x

P3DIR.x

P3IN.x

Module X IN

Module X OUT

P3OUT.x

DVSS

DVCC

P3REN.x

Pad Logic

USCI Direction

Control

DVSS

P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger

www.ti.com

Table 32. Port P3 (P3.1 to P3.5) Pin Functions

PIN NAME (P3.x) x FUNCTION

P3.1/UCB0SIMO/UCB0SDA 1

P3.2/UCB0SOMI/UCB0SCL 2

P3.3/UCB0CLK/UCA0STE 3

P3.4/UCA0TXD/UCA0SIMO 4

P3.5/UCA0RXD/UCA0SOMI 5

(2)

P3.1

(I/O) I: 0; O: 1 0

UCB0SIMO/UCB0SDA

(2)

P3.2

(I/O) I: 0; O: 1 0

UCB0SOMI/UCB0SCL

(2)

P3.3

(I/O) I: 0; O: 1 0

UCB0CLK/UCA0STE

(2)

P3.4

(I/O) I: 0; O: 1 0

UCA0TXD/UCA0SIMO

(2)

P3.5

(I/O) I: 0; O: 1 0

UCA0RXD/UCA0SOMI

(3)

(3) (4)

(3)

CONTROL BITS/SIGNALS

P3DIR.x P3SEL.x

X 1

(1) X = Don't care (2) Default after reset (PUC/POR) (3) The pin direction is controlled by the USCI module. (4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to

3-wire SPI mode even if 4-wire SPI mode is selected.

(1)

Bus

Keeper

Direction 0: Input 1: Output

P3SEL.x

P3DIR.x

P3IN.x

Module X IN

Module X OUT

P3OUT.x

P3.6/A6/OA0I2 P3.7/A7/OA1I2

DVSS

DVCC

P3REN.x

ADC10AE0.y

Pad Logic

INCHx = y

To ADC10

OA0/1

−

DVSS

MSP430F22x2 MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger

Table 33. Port P3 (P3.6, P3.7) Pin Functions

PIN NAME (P3.x) x y FUNCTION

P3.6/A6/OA0I2 6 6

P3.7/A7/OA1I2 7 7

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(2)

P3.6

(I/O) I: 0; O: 1 0 0

A6/OA0I2

(2)

P3.7

(I/O) I: 0; O: 1 0 0

A7/OA1I2

(3)

CONTROL BITS/SIGNALS

P3DIR.x P3SEL.x ADC10AE0.y

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P4SEL.x

P4DIR.x

P4IN.x

Module X IN

Module X OUT

P4OUT.x

P4.0/TB0 P4.1/TB1 P4.2/TB2

DVSS

DVCC

P4REN.x

Pad Logic

P4DIR.6

P4SEL.6

ADC10AE1.7

P4.6/TBOUTH/A15/OA1I3

Timer_B OutputTristate Logic

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger

www.ti.com

Table 34. Port P4 (P4.0 to P4.2) Pin Functions

PIN NAME (P4.x) x FUNCTION

(1)

P4.0

(I/O) I: 0; O: 1 0

P4.0/TB0 0 Timer_B3.CCI0A 0 1

Timer_B3.TB0 1 1

(1)

P4.1

P4.1/TB1 1 Timer_B3.CCI1A 0 1

P4.2/TB2 2 Timer_B3.CCI2A 0 1

(1) Default after reset (PUC/POR)

(I/O) I: 0; O: 1 0

Timer_B3.TB1 1 1

(1)

P4.2

(I/O) I: 0; O: 1 0

Timer_B3.TB2 1 1

CONTROL BITS/SIGNALS

P4DIR.x P4SEL.x

OAPMx

OAADCx

To OA0/1 Feedback Network

OAADCx = 01 and OAPMx > 00

Bus

Keeper

Direction 0: Input 1: Output

P4SEL.x

P4DIR.x

P4IN.x

Module X IN

Module X OUT

P4OUT.x

P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O

DVSS

DVCC

P4REN.x

ADC10AE1.y

Pad Logic

INCHx = 8+y

To ADC 10

OA0/1

−

P4DIR.6

P4SEL.6

ADC10AE1.7

P4.6/TBOUTH/A15/OA1I3

Timer_B OutputTristate Logic

†

MSP430F22x2 MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger

†

If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output,

respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

Table 35. Port P4 (P4.3 to P4.4) Pin Functions

PIN NAME (P4.x) x y FUNCTION

(2)

P4.3

(I/O) I: 0; O: 1 0 0

P4.3/TB0/A12/OA0O 3 4

P4.4/TB1/A13/OA1O 4 5

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Timer_B3.CCI0B 0 1 0

Timer_B3.TB0 1 1 0

A12/OA0O

P4.4

Timer_B3.CCI1B 0 1 0

Timer_B3.TB1 1 1 0

A13/OA1O

(3)

(2)

(I/O) I: 0; O: 1 0 0

(3)

CONTROL BITS/SIGNALS

P4DIR.x P4SEL.x ADC10AE1.y

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P4SEL.5

P4DIR.5

P4IN.5

Module X IN

Module X OUT

P4OUT.5

P4.5/TB3/A14/OA0I3

DVSS

DVCC

P4REN.5

ADC10AE1.6

Pad Logic

INCHx = 14

To ADC 10

P4DIR.6

P4SEL.6

ADC10AE1.7

P4.6/TBOUTH/A15/OA1I3

Timer_B OutputTristate Logic

OA0

−

MSP430F22x2 MSP430F22x4

www.ti.com

Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger

SLAS504G –JULY 2006–REVISED AUGUST 2012

PIN NAME (P4.x) x y FUNCTION

P4.5/TB3/A14/OA0I3 5 6 Timer_B3.TB2 1 1 0

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Table 36. Port P4 (P4.5) Pin Functions

(2)

P4.5

(I/O) I: 0; O: 1 0 0

A14/OA0I3

(3)

CONTROL BITS/SIGNALS

P4DIR.x P4SEL.x ADC10AE1.y

X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P4SEL.6

P4DIR.6

P4IN.6

Module X IN

Module X OUT

P4OUT.6

0DVSS

DVCC

P4REN.6

ADC10AE1.7

Pad Logic

INCHx = 15

To ADC 10

OA1

−

P4.6/TBOUTH/ A15/OA1I3

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger

www.ti.com

Table 37. Port P4 (P4.6) Pin Functions

PIN NAME (P4.x) x y FUNCTION

P4.6/TBOUTH/A15/OA1I3 6 7

(1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(2)

P4.6

(I/O) I: 0; O: 1 0 0 TBOUTH 0 1 0 DV

A15/OA1I3

(3)

CONTROL BITS/SIGNALS

P4DIR.x P4SEL.x ADC10AE1.y

1 1 0 X X 1

(1)

Bus

Keeper

Direction 0: Input 1: Output

P4SEL.x

P4DIR.x

P4IN.x

Module X IN

Module X OUT

P4OUT.x

P4.7/TBCLK

DVSS

DVCC

P4REN.x

Pad Logic

DVSS

MSP430F22x2 MSP430F22x4

www.ti.com

Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 38. Port P4 (Pr.7) Pin Functions

PIN NAME (P4.x) x FUNCTION

(1)

P4.7

(I/O) I: 0; O: 1 0

P4.7/TBCLK 7 Timer_B3.TBCLK 0 1

(1) Default after reset (PUC/POR)

CONTROL BITS/SIGNALS

P4DIR.x P4SEL.x

1 1

Time TMS Goes Low After POR

TMS

TEST

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see

Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Figure 28. Fuse Check Mode Current

NOTE

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the Bootstrap Loader section for more information.

MSP430F22x2 MSP430F22x4

www.ti.com

REVISION HISTORY

Literature Summary

Number

SLAS504 Preliminary data sheet release

SLAS504A

SLAS504B

SLAS504C

SLAS504D

SLAS504E Added information for YFF package SLAS504F

SLAS504G

Production data sheet release Updated specification and added characterization graphs Updated/corrected port pin schematics

Maximum low-power mode supply current limits decreased Added note concerning f

Added Development Tool Support section (page 2) Changed T

Corrected pin names in "Port P3 pin schematic: P3.0" and "Port P3 (P3.0) pin functions" (page 68) Corrected pin names in "Port P3 pin schematic: P3.1 to P3.5" and "Port P3 (P3.1 to P3.5) pin functions" (page 69) Corrected signal names in "Port P2 pin schematic: P2.5, input/output" (page 65) (D1) Corrected values in "x" column in "Port P3 (P3.1 to P3.5) pin functions" (page 69) (D2)

Correct signal names for P3.6 and P3.7 in MSP430F22x2 pinouts – DA package, RHA package Changed Storage temperature range limit in Absolute Maximum Ratings Corrected Test Conditions in Crystal Oscillator LFXT1, High-Frequency Mode Corrected signal names in Port P1 (P1.0 to P1.3) Pin Functions Corrected typo in note 1 on Crystal Oscillator LFXT1, High-Frequency Mode table

Terminal Functions tables, Corrected description of V Added note on TC

for programmed devices from "-40°C to 105°C" to "-55°C to 105°C" (page 23)

stg

REF+

to USCI SPI parameters

UCxCLK

REF-/VeREF-

in 10-Bit ADC, Built-In Voltage Reference.

SLAS504G –JULY 2006–REVISED AUGUST 2012

pins.

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430F2232IDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2232

MSP430F2232IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2232

MSP430F2232IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2232

MSP430F2232IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2232

MSP430F2232IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2232

MSP430F2232IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2232

MSP430F2232TDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2232T

MSP430F2232TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2232T

MSP430F2232TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2232T

MSP430F2232TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2232T

MSP430F2234IDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2234

MSP430F2234IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2234

MSP430F2234IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2234

MSP430F2234IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2234

MSP430F2234IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2234

MSP430F2234IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2234

MSP430F2234TDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2234T

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2014

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430F2234TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2234T

MSP430F2234TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2234T

MSP430F2234TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2234T

MSP430F2252IDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2252

MSP430F2252IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2252

MSP430F2252IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2252

MSP430F2252IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2252

MSP430F2252IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2252

MSP430F2252IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2252

MSP430F2252TDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2252T

MSP430F2252TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2252T

MSP430F2252TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2252T

MSP430F2252TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2252T

MSP430F2254IDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2254

MSP430F2254IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2254

MSP430F2254IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2254

MSP430F2254IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2254

MSP430F2254IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2254

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2014

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430F2254IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2254

MSP430F2254TDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2254T

MSP430F2254TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2254T

MSP430F2254TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2254T

MSP430F2254TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2254T

MSP430F2272IDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2272

MSP430F2272IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2272

MSP430F2272IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2272

MSP430F2272IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2272

MSP430F2272IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2272

MSP430F2272IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2272

MSP430F2272TDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2272T

MSP430F2272TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2272T

MSP430F2272TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2272T

MSP430F2272TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2272T

MSP430F2274IDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2274

MSP430F2274IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2274

MSP430F2274IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2274

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2014

Addendum-Page 4

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430F2274IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430

F2274

MSP430F2274IYFFR ACTIVE DSBGA YFF 49 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2274

MSP430F2274IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM M430F2274

MSP430F2274TDA ACTIVE TSSOP DA 38 40 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2274T

MSP430F2274TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2274T

MSP430F2274TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2274T

MSP430F2274TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 105 M430

F2274T

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com

9-Sep-2014

Addendum-Page 5

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF MSP430F2252, MSP430F2272, MSP430F2274 :

•

Automotive: MSP430F2252-Q1, MSP430F2272-Q1

•

Enhanced Product: MSP430F2274-EP

NOTE: Qualified Version Definitions:

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

MSP430F2232IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2232IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2232IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2232TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2232TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2234IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2234IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2234IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2234TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2252IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2252IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2252IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2252TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2252TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2254IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2254IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2254IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2254TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

Device Package

MSP430F2254TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2272IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2272IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2272IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2272TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2272TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2274IDAR TSSOP DA 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 MSP430F2274IRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2274IRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

MSP430F2274TRHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 MSP430F2274TRHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430F2232IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F2232IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2232IRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2232TRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2232TRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2234IDAR TSSOP DA 38 2000 367.0 367.0 45.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430F2234IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2234IRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2234TRHAR VQFN RHA 40 2500 367.0 367.0 38.0

MSP430F2252IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F2252IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2252IRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2252TRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2252TRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2254IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F2254IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2254IRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2254TRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2254TRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2272IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F2272IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2272IRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2272TRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2272TRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2274IDAR TSSOP DA 38 2000 367.0 367.0 45.0 MSP430F2274IRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2274IRHAT VQFN RHA 40 250 210.0 185.0 35.0

MSP430F2274TRHAR VQFN RHA 40 2500 367.0 367.0 38.0 MSP430F2274TRHAT VQFN RHA 40 250 210.0 185.0 35.0

Pack Materials-Page 3

D: Max =

3.518 mm, Min =

3.458 mm

E: Max =

3.36 mm, Min =

3.3 mm

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

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Texas Instruments MSP430F2272TDA, MSP430F2252IYFF, MSP430F2232IDA, MSP430F2232IYFF, MSP430F2252IDA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual