Texas Instruments LMS3655AQEVM, LMS3635MQEVM, LMS3655MQEVM, LMS3655NQEVM User Manual

User's Guide
SNVU542–July 2017
LMS36x5x-Q1 EVM User's Guide
Figure 1. LMS3635xQEVM and LMS3655xQEVM Evaluation Board – Top View
All aspects of the LMS3635xQEVM and LMS3655xQEVM are optimized for high-performance industrial and automotive markets. An input voltage range to 36 V eases the input surge protection design. Exceptional dropout performance allows for the elimination of a boost stage in many designs for start and stop applications. An open-drain RESET output, with filtering and Power Good delay, provides a true indication of system status. This feature negates the requirement for additional supervisory circuitry, saving cost, and board space. Seamless transition between PWM and PFM operation, along with a low quiescent current, ensures high efficiency at all loads. The Texas Instruments LMS3655xQEVM and LMS3635xQEVM help to evaluate the operation and performance of the LMS3655-Q1, LMS3655, and LMS3635-Q1. The LMS36x5xQEVM is available for order in four variants.
See Table 1 for orderable EVM variants and configurations.
Table 1. Orderable EVM Variants and Configuration for LM53625 and LM53635
EVM
VARIANT
001 LMS3655AQEVM LMS3655AQRNLRQ1 5.5 A 5 V Adjusted Yes 002 LMS3655MQEVM LMS3655MQRNLRQ1 5.5 A 5 V Adjusted Yes Yes 003 LMS3655NQEVM LMS3655NQRNLRQ1 5.5 A 3.3 V Fixed Yes Yes 004 LMS3635MQEVM LMS3635MQRNLRQ1 3.5 A 5 V Adjusted Yes Yes
EVM ORDERABLE
NAME
IC U1
CONTINUOUS
LOAD
OUTPUT
VOLTAGE
SPREAD
SPECTRUM
AVAILABLE
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Technical Specification EVM Board
1 Technical Specification EVM Board ....................................................................................... 2
2 Schematics ................................................................................................................... 3
3 Board Layout ................................................................................................................. 5
4 Operation and Test Setup .................................................................................................. 9
4.1 Efficiency Measurement ........................................................................................... 9
4.2 Measure Load Transient ......................................................................................... 10
4.3 Measure EMI....................................................................................................... 10
5 Posts, Probes, and Jumpers.............................................................................................. 11
5.1 VIN1 and GND1 Posts............................................................................................ 11
5.2 VOUT and GND Posts............................................................................................ 11
5.3 IN+ and IN– Posts................................................................................................. 11
5.4 EN and GND2 Probe ............................................................................................. 11
5.5 VINS, VOUTS, and GNDS Probe............................................................................... 11
5.6 BIAS and GNDS Probe........................................................................................... 11
5.7 RESET and GND3 Probe ........................................................................................ 11
5.8 SYNC and GND3 Probe.......................................................................................... 11
5.9 Jumper J1 .......................................................................................................... 12
5.10 Jumper J2 .......................................................................................................... 12
5.11 Jumper J3 .......................................................................................................... 12
6 Bill of Materials ............................................................................................................. 12
7 Efficiency and Line and Load Regulation ............................................................................... 14
7.1 Load Transients ................................................................................................... 15
7.2 Conducted EMI .................................................................................................... 15
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Contents
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1 Technical Specification EVM Board
Table 2 shows specifications for the LMS3635xQEVM and LMS3655xQEVM board.
Table 2. Technical Specification
BOARD SIZE
4000 × 3000 mil 101 mm × 76 mm
BOARD LAYER
4-Layer FR4 PCB Top Layer1 and Bottom Layer2
SOLUTION SIZE
700 mil × 1700 mil 17.78 mm × 43.18 mm
POWER INPUT
VIN1 and GND1
IN+ / IN–
POWER OUTPUT
VOUT and GND Power Output to Load typical 3.3 V or 5 V
JUMPERS
J1 FPWM pin
J2 ENABLE pin
J3 RESET pin
TEST POINTS
GNDS, GND2 and GND3
EN
VINS
VOUTS
BIAS
RESET
SYNC
Mid Layer2 and Mid Layer3
Power Supply Input
Power Input for EMI Test
Auto Mode or Forced PWM
Enable LMS3635x and LMS3655x
Open-drain output
Sense GND Points
Enable Pin Voltage
Input Voltage Sense
Output Voltage Sense
BIAS Voltage Sense
RESET output
Switch node SYNC input
76 cm
2.8-mil, 2-oz. Cu
1.4-mil, 1-oz. Cu
7.68 cm
typical 13.5 V (range 3.5 to 36 V) typical 13.5 V (range 3.5 to 36 V)
Set – Default [AUTO-MODE]
Set – Default [EN-VIN]
Optional - [RESET-VOUT]
Sense Ground
If J2[EN-VIN], then EN = VIN1 3.5 to 36 V
Sense VIN1 3.5 to 36 V
Sense VOUT typical 3.3 V or 5 V
Sense BIAS typical 3.3 V or 5 V
If J3 [RESET-VOUT], then RESET = VOUTS
External sync frequency source
2
2
2
LMS36x5x-Q1 EVM User's Guide
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All capacitors at input of LMS3655/35 should be rated to 50VDC.
V
OUT
: 3.3V/5V
I
OUT
: 5.5A/3.5A
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Schematics
3
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2 Schematics
Figure 2. Fixed - Output Voltage Option Schematic
The fixed voltage option has an internal resistor divider, and the FB pin connects directly to the output capacitance.
NOTE: Cvcc and Cbias must connect directly to AGND, pin 20.
All capacitors at input of LMS3655/35 should be rated to 50VDC.
V
OUT
: 3.3V/5V
I
OUT
: 5.5A/3.5A
Schematics
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Figure 3. Adjustable - Output Voltage Option Schematic
The adjustable output option uses an external resistor divider to define output voltage. The CFF capacitor can be adjusted to make the feedback loop response faster for load transients. By lowering the total resistance of the feedback divider, the noise immunity can be increased.
NOTE: To minimize noise coupling into the feedback pin, the maximum resistance recommended for the feedback resistor RFBT is 50 kΩ. The
feedback resistors RFBB and RFBT must be placed as close to the FB pin as possible, and RFBB must be grounded to the AGND pin.
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3 Board Layout
The LMS3655xQEVM uses a four-layer PCB stack-up design. Top Layer 1 and Bottom Layer 4 are implemented using 2-oz. copper for optimized heat transfer and dissipation. Mid Layer 2 and Mid Layer 3 use 1-oz. copper. Total PCB thickness is 61 mil (1.55 mm).
The overall EVM PCB board size dimension is 4000 mil × 3000 mil (101 mm × 76 mm) with a top surface area of 76 cm2. All vias on the PCB are constructed using 8-mil drill through-hole with 16-mil pad size.
Figure 5 to Figure 8 shows the PCB Layout for each Cu Layer. Top Layer 1 and Bottom Layer 4 are
constructed using large filled Cu areas connected to GND. This is done to improve thermal performance as well as improve overall EMI performance. Mid Layer 2 is constructed using a large GND plane. The purpose is to minimize loop inductance by placing metal directly under the Top Layer 1 traces, which minimizes the cross section of current loops. Mid Layer 3 is mainly used to route non-critical signal traces to the IC.
Board Layout
Figure 4. Four-Layer PCB Stack-Up
NOTE: The PCB layout is not fully optimized to use for final applications, but gives a good starting
point. The layout can be simplified and optimized by eliminating features included for evaluation purposes such as measurement sense lines, jumper connections, and features unused in a particular application such as the feedback resistor divider for fixed voltage options.
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Board Layout
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Figure 5. PCB Layout Top Layer 1 – Top View
Figure 6. PCB Layout Mid Layer 2 GND Plane – Top View
6
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Board Layout
Figure 7. PCB Layer Mid Layer 3 – Top View
Figure 8. PCB Layer Bottom Layer 4 – Flipped View (as Seen From Bottom of Board)
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