Texas Instruments LMK04906 Series, LMK04906B User Manual

LMK04906 Evaluation Board

User's Guide

January 2012

Literature Number SNAU126A

Revised – December 2013

LMK04906 Family

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

Evaluation Board Instructions

2 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

TABLE OF CONTENTS ..............................................................................................................................................................3

GENERAL DESCRIPTION ..........................................................................................................................................................5

Evaluation Board Kit Contents .................................................................................................................. 5

Available LMK04906 Evaluation Boards ................................................................................................. 5

Available LMK04906 Family Devices ...................................................................................................... 5

QUICK START ..........................................................................................................................................................................6

Default CodeLoader Modes for Evaluation Boards................................................................................... 7

EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04906B ............................................................................................8

1. Start CodeLoader 4 Application ............................................................................................................ 8

2. Select Device ......................................................................................................................................... 8

3. Program/Load Device ............................................................................................................................ 9

4. Restoring a Default Mode ...................................................................................................................... 9

5. Visual Confirmation of Frequency Lock ............................................................................................. 10

6. Enable Clock Outputs .......................................................................................................................... 10

PLL LOOP FILTERS AND LOOP PARAMETERS ......................................................................................................................... 12

PLL 1 Loop Filter .................................................................................................................................... 12

25 MHz VCXO PLL ............................................................................................................................ 12

PLL2 Loop Filter ..................................................................................................................................... 13

EVALUATION BOARD INPUTS AND OUTPUTS ........................................................................................................................ 14

RECOMMENDED TEST EQUIPMENT ...................................................................................................................................... 21

APPENDIX A: CODELOADER USAGE....................................................................................................................................... 22

Port Setup Tab.......................................................................................................................................... 22

Clock Outputs Tab ................................................................................................................................... 23

PLL1 Tab ................................................................................................................................................. 26

Setting the PLL1 VCO Frequency and PLL2 Reference Frequency ................................................... 27

PLL2 Tab ................................................................................................................................................. 28

Bits/Pins Tab ............................................................................................................................................ 29

Registers Tab ........................................................................................................................................... 34

APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS .................................................................................................. 35

PLL1 ........................................................................................................................................................ 35

25 MHz VCXO Phase Noise ............................................................................................................... 35

Clock Output Measurement Technique ............................................................................................... 36

Clock Outputs (CLKout).......................................................................................................................... 37

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 3

LMK04906B CLKout Phase Noise ..................................................................................................... 37

APPENDIX C: SCHEMATICS .................................................................................................................................................... 38

Power Supplies......................................................................................................................................... 38

LMK04906B Device with Loop Filter and Crystal Circuits ................................................................... 39

Reference Inputs (CLKin0, CLKin1 & CLKin2), External VCXO (OSCin) & VCO Circuits............... 40

Clock Outputs (OSCout0, CLKout0 to CLKout5) .................................................................................. 41

uWire Header, Logic I/O Ports and Status LEDs .................................................................................... 42

APPENDIX D: BILL OF MATERIALS ......................................................................................................................................... 43

APPENDIX E: PCB LAYERS STACKUP ..................................................................................................................................... 47

APPENDIX F: PCB LAYOUT ..................................................................................................................................................... 48

Layer #1 – Top ......................................................................................................................................... 48

Layer #2 – RF Ground Plane (Inverted) .................................................................................................. 49

Layer #3 – Vcc Planes ............................................................................................................................. 50

Layer #4 – Ground Plane (Inverted) ........................................................................................................ 51

Layer # 5 – Vcc Planes 2 ......................................................................................................................... 52

Layer #6 – Bottom ................................................................................................................................... 53

Layers #1 and 6 – Top and Bottom (Composite) ..................................................................................... 54

APPENDIX G: PROPERLY CONFIGURING LPT PORT ................................................................................................................ 55

LPT Driver Loading ................................................................................................................................. 55

Correct LPT Port/Address........................................................................................................................ 55

Correct LPT Mode ................................................................................................................................... 56

Legacy Board Port Setup ......................................................................................................................... 56

APPENDIX H: TROUBLESHOOTING INFORMATION ................................................................................................................ 57

1) Confirm Communications ................................................................................................................ 57

2) Confirm PLL1 operation/locking ..................................................................................................... 57

3) Confirm PLL2 operation/locking ..................................................................................................... 58

APPENDIX I: EVM SOFTWARE AND COMMUNICATION ......................................................................................................... 59

OPTION 1 ................................................................................................................................................ 59

OPTION 2 ................................................................................................................................................ 59

4 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

Evaluation Board ID

Device

PLL1 VCXO

25 MHz Epson VCXO

Model VG-4231CA 25.0000M-FGRC3

Buffered/

Outputs

Programmable

Outputs

LMK04906B

3 1 6

2370 to 2600 MHz

General Description

The LMK04906 Evaluation Board simplifies evaluation of the LMK04906B Low-Noise Clock Jitter Cleaner with Dual Loop PLLs. Texas Instrument’s CodeLoader software can be used to program the internal registers of the LMK04906B device through the USB2ANY-uWIRE interface. The CodeLoader software will run on a Windows 2000/XP or Windows 7 PC and can be downloaded from http://www.ti.com/tool/codeloader.

Evaluation Board Kit Contents

The evaluation board kit includes:

• (1) LMK04906 Evaluati on Boar d fr om Table 1

• (1) CodeLoader and USB2ANY-uWIRE Interface  uWire header on EVM

A vailable LMK04906 Ev aluation Bo ards

The LMK04906 Evaluation Board supports any of the four devices offered in the LMK04906 Family. All evaluation boards use the same PCB layout and bill-of-materials, except for the corresponding LMK04906B device affixed to the board. A commercial-quality VCXO is also mounted to the board to provide a known reference point for evaluating device performance and functionality.

Table 1: Available Evaluation Board Configurations

LMK04906BEVAL LMK04906B

A vailable LMK04906 F amily Devices

Table 2: LMK04906B Devices

Device

Reference

Inputs

Divided

OSCin

LVDS/LVPECL/

LVCMOS

VCO Frequency

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 5

125 MHz (Default)

Quick Start

Full evaluation board instructions are downloadable from the LMK04906B device product folder at www.ti.com/product/LMK04906.

1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard LP3878ADJ LDO regulator will output a low-noise 3.3 V supply to operate the device.

2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 125 MHz for default. The reference frequency depends on the device programming.

3. Connect the uWire header to a PC USB port using the USB2ANY-uWIRE interface.

4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at least once to load all registers. Alternatively click menu “Keyboard Controls”  “Load Device”. CodeLoader can be downloaded from www.ti.com/tool/codeloader.

5. Measurements may be made on an active output clock port via its SMA connector.

Figure 1: Quick Start Diagram

6 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

CLKin

Frequency

OSCin

Frequency

122.88 MHz CLKin1, 122.88 MHz VCXO

122.88 MHz

125 MHz CLKin1, 25 MHz VCXO

Dual PLL, Internal VCO

125 MHz

25 MHz

Default CodeLoader Modes for Evaluation Boards

CodeLoader saves the state of the selected LMK04906B device when exiting the software. To ensure a common starting point, the following modes listed in Table 3 may be restored by clicking “Mode” and selecting the appropriate device configuration, as shown in Figure 2 in the case of the LMK04906B device. Similar default modes are available for each LMK04906B device in CodeLoader. Choose a mode with CLKin0 or CLKin2 for differential clock signal or CLKin1 for a single ended signal.

Figure 2: Selecting a Default Mode for the LMK04906 Device

After restoring a default mode, press Ctrl+L to program the device. The default modes also disable certain outputs , so make sure t o enable the output under test to make measurements.

Table 3: Default CodeLoader Modes for LMK04906

Default CodeLoader Mode Device Mode

Dual PLL, Internal VCO

The next section outlines step-by-step procedures for using the evaluation board with the LMK04906B. For boards with another part number, make sure to select the corresponding part number under the “Device” menu.

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 7

Figure 3 – Selecting the LMK04906B device

Example: Using CodeLoader to Program the LMK04906B

The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements with the LMK04906B device as an example. For more information on CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader.

Before proceeding, be sur e to foll ow the Quick Start section above to ensure proper connections.

1. Start CodeLoader 4 A pplication

Click “Start”  “Programs”  “CodeLoader 4”  “CodeLoader 4” The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.

2. Select Device

Click “Select Device”  “Clock Conditioners”  “LMK04906B”

Once started CodeLoader 4 will load the last used device. To load a new device, click “Select Device” from the menu bar. Then, select the subgroup and finally device to load. In this example, the LMK04906B is chosen. Selecting the device does cause the device to be programmed.

8 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

Figure 4 – Loading the Device

3. Program/Load Device

Assuming the Port Setup settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls”  “Load Device” from the menu to program the device to the current state of the newly loaded LMK04906 file.

Once the device has been initially loaded, CodeLoader will automatically program changed registers so it is not necessary to re-load the device upon subsequent changes in the device configuration. It is possible to disable this functionality by ensuring there is no checkmark by the “Options”  “AutoR el oa d with Changes.”

Because a default mode will be restored in the next step, this step is not really needed but is included to emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting CodeLoader, restoring a mode, or restoring a saved setup using the File menu.

See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at

http://www.ti.com/tool/codeloader for more informati on on Por t Setu p. Appendix H:

Troubleshooting Information contains information on troubleshooting communi cat ions.

4. Restoring a Default Mode

Click “Mode”  “125 MHz CLKin1, 25 MHz VCXO”; then press Ctrl+L.

Figure 5: Setting the Default mode for L MK04906

For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point. This is important because when CodeLoader is closed, it remembers the last settings used for a particular device. Again, remember to press Ctrl+L as the first step after loading a default mode.

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 9

Figure 7: Setting LVCMOS modes

Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0

5. Visual Confirmation of Frequency Lock

After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2 are locked to the reference clock applied to CLKin1. This assumes LD_M U X = PLL1/2 DLD an d LD_TYPE = Active High, which are the default settings.

6. Enable Clock Outputs

While the LMK04906B offers programmable clock output buffer formats, the evaluation board is shipped with preconfigured output terminations to match the default buffer type for each output. Refer to the CLKout port description in the Evaluation Board Inputs and Outputs section.

To measure phase noise at one of the clock outputs, for example, CLKout0:

1. Click on the Clock Outputs tab,

2. Uncheck “Powerdown” in the Digital Delay box to enable the channel,

3. Set the following settings as needed: a. Digital Delay value b. Clock Divider value c. Analog Delay select and Analog Delay value (if not “Bypassed”) d. Clock Output type.

4. Depending on the configured output type, the clock output SMAs can be interfaced to a test

instrument with a single-ended 50-ohm input as follows.

a. For LVDS:

i. A balun (like ADT2-1T) is recommended for differential-to-single-ended

conversion.

b. For LVPECL:

i. A balun can be used, or

ii. One side of the LVPECL signal can be terminated with a 50-ohm load and the

other side can be run single-ended to the instrument.

c. For LVCMOS:

i. There are two single-ended outputs, CLKoutX

and CLKoutX*, and each output can be set to Normal, Inverted, or Off. There are nine (9) combinations of LVCMOS modes in the Clock Output list.

ii. One side of the LVCMOS signal can be

terminated with a 50-ohm load and the other side can be run single-ended to the instrument.

iii. A balun may also be used. Ensure CLKoutX

and CLKoutX* states are complementary to each other. That is, Norm/Inv or Inv/Norm.

10 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.

See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs.

National’s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.ti.com/tool/clockdesigntool.

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 11

25 MHz VCXO PLL

PLL Loop Filters and Loop Parameters

In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a “dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a frequency reference rather than a phase reference.

The loop filters on the LMK04906 ev al uati o n boar d ar e se tup using t he approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. The following tables co ntai n the par am eter s for PLL 1 and PL L2 f or eac h oscil l at or opt ion.

National’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See: http://www.ti.com/tool/clockdesigntool.

PLL 1 Loop Filter

Table 4: PLL1 Loop Filter Parameters for Epson 25 MHz VCXO

Phase Margin

49˚

Kφ (Charge Pump)

400 uA

Loop Bandwidth

Reference Clock

Frequency Loop Filter

Components

21 Hz

125 MHz

C1_VCXO = 3300

Phase Detector Freq

VCO Gain

Output Frequency

C2_VCXO = 10000 nF

C2A_VCXO = 10000 nF

2083.33 MHz

4.5 kHz/Volt

25 MHz (To PLL 2)

R2_VCXO = 1 kΩ

Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.

12 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

LMK04906B

C1_VCO

0.082

C2_VCO

5.6

C3 (internal)

0.01

C4 (internal)

0.01

R2_VCO

0.68

kΩ

R3 (internal)

0.2

kΩ

R4 (internal)

0.2

kΩ

Charge Pump

Current, Kφ

Phase

Frequency

2500

MHz

Kvco

18.5

MHz/V N 50

degree

Loop

Bandwidth

PLL2 Loop Filter

Table 5: PLL2 Loop Filter Parameters for LMK04906B

3.2 mA

Detector

50 MHz

Phase Margin 69

132 kHz

Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 13

Signal Type, Input/Output

Clock outputs with programmable output buffers.

Clock output pair

Default Board Termination

CLKout0

LVPECL*

CLKout1

LVPECL

CLKout2

LVDS* / LVCMOS

CLKout3

LVDS / LVCMOS

CLKout4

LVDS* / LVCMOS

CLKout5

LVPECL

state).

Evaluation Board Inputs and Outputs

The following table contains descriptions of the inputs and outputs for the evaluation board. Unless otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some applicable CodeLoader programming controls are noted for convenience. Refer to the LMK04906 Family Datasheet for complete register programming information.

Table 6: Evaluation Board Inputs and Outputs

Connector Name

Populated: CLKout0, CLKout0*, CLKout1, CLKout1*, CLKout2, CLKout2*, CLKout3, CLKout3*, CLKout4, CLKout4*,

CLKout5, CLKout5*

Analog, Output

Description

The output terminations by default on the evaluation board are shown below, and the output type selected by default in CodeLoader is indicated by an asterisk (*):

Each CLKout pair has a programmable LVDS, LVPECL, or LVCMOS buffer. The output buffer type can be selected in CodeLoader in the Clock Outputs tab via the CLKoutX_TYPE control.

All clock outputs are AC-coupled to allow safe testing with RF test equipment.

All LVPECL clock outputs are source-terminated using 240ohm resistors.

If an output pair is programmed to LVCMOS, each output can be independently configured (normal, inverted, or off/tri-

14 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

Signal Type, Input/Output

Buffered outputs of OSCin port.

OSC output pair

Default Board Termination

OSCout0

LVDS* / LVCMOS

off/tri-state).

Main power supply input for the evaluation board.

schematics for more details.

Alternative power supply input for the evaluation board using Apply power to either Vcc SMA or J1, but not both.

Optional Vcc input to power the VCO circuit if separated

power.

Connector Name

Populated:

OSCout0, OSCout0*,

Vcc

Analog,

Output

Power,

Input

Description

The output terminations on the evaluation board are shown below, the output type selected by default in CodeLoader is indicated by an asterisk (*):

OSCout0 has a programmable LVDS, LVPECL, or LVCMOS output buffer. The OSCout0 buffer type can be selected in CodeLoader on the Clock Outputs tab via the OSCout0_TYPE control.

OSCout0 is AC-coupled to allow safe testing with RF test equipment.

If OSCout0 is programmed as LVCMOS, each output can be independently configured (normal, inverted, inverted, and

A 3.9 V DC power source applied to this SMA will, by default, source the onboard LDO regulators that power the inner layer planes that supply the LMK04906B and its auxiliary circuits (e.g. VCXO).

The LMK04906B contains internal voltage regulators for the VCO, PLL and other internal blocks. The clock outputs do not have an internal regulator, so a clean power supply with sufficient output current capability is required for optimal performance.

On-board LDO regulators and 0  flexibility to supply and route power to various devices. See

Populated:

Unpopulated: VccVCO/Aux

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 15

Power,

Input

Power,

Input

two unshielded wires (Vcc and GND).

voltage rails are needed. The VccVCO/Aux input can power these circuits directly or supply the on-board LDO

regulators. 0 Ω resistor options provide flexibility to route

Signal Type, Input/Output

Reference Clock Inputs for PLL1 (CLKin0, 1, 2).

selected in CodeLoader. The clock input selection

Input

Mode

Min

Max

Units

Differential

Bipolar or

0.5

3.1

Vpp

Single Ended

0.25

2.4

Vpp

Ext VCO (Fin)

Connector Name

CLKin1 can alternatively be used as an External Feedback Clock Input (FBCLKin) in 0-delay mode or an RF Input (Fin) in External VCO mode.

Reference Clock Inputs for PLL1 (CLKin0, 1)

FBCLKin/CLKin1* is configured by default for a single-ended reference clock input from a 50-ohm source. The non-driven input pin (FBCLKin/CLKin1) is connected to GND with a 0.1 uF. CLKin0/CLKin0* is configured by default for a differential reference clock input from a 50-ohm source.

CLKin1* is the default reference clock input mode can be programmed on the Bits/Pins tab

via the CLKin_Select_MODE control . Re fer t o the

LMK04906 Family Datasheet secti on “I npu t C l ock

Populated:

CLKin0, CLKin0*,

FBCLKin*/CLKin1*

CLKin2, CLKin2*

Analog,

Input

Switching” for more information.

AC coupled Input Clock Swing Levels

Not Populated:

FBCLKin/CLKin1

External Feedback Input (FBCLKin) for 0-Delay

CLKin1 is shared for use with FBCLKin as an external feedback clock input to PLL1 for 0-delay mode. See section, Error! Reference source not found. Error! Reference source not found., for more details on using 0-delay mode with the evaluation board and the evaluation board software.

RF Input (Fin) for External VCO

CLKin1 is also shared for use with Fin as an RF input for external VCO mode usi ng the onboard VCO footprint (U3) or add-on VCO board. To enable Dual PLL mode with External VCO, the following registers must be properly configured in CodeLoader:

Description

CMOS

• MODE = (3) Dual PLL, Ext VCO (F i n), (5) Dual PLL, Ext VCO, 0-Delay, (11) PLL2,

16 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

Signal Type, Input/Output

Feedback VCXO clock input to PLL1 and

does not accommodate the desired VCXO device.

Input (OSCin) specifications.

Test point:

Tuning voltage output from the loop filter for PLL1.

Test point:

VTUNE2_TP

Analog,

Output

Tuning voltage output from the loop filter for PLL2.

10-pin header for uWire programming interface

dedicated SMAs and test poi nts .

Connector Name

Not populated:

OSCin, OSCin*

Analog,

Input

Description

Reference clock input to PLL2. By default, these SMAs are not connected to the

traces going to the OSCin/OSCin* pins of the LMK04906B. Instead, the single-ended output of the onboard VCXO (U2) drives the OSCin* input of the device and the OSCin input of the device is connected to GND with 0.1 uF.

A VCXO add-on board may be optionally attached via these SMA connectors with minor modification to the components going to the OSCin/OSCin* pins of device. This is useful if the VCXO footprint

A single-ended or differential signal may be used to drive the OSCin/OSCin* pins and must be AC coupled. If operated in single-ended mode, the unused input must be connected to GND with 0.1 uF.

Refer to the LMK04906 Family Datasheet section “Electrical Characteristics” for PLL2 Reference

VTUNE1_TP

Analog,

Output

and programmable logi c I/O pins for the

Populated:

uWire

Test points: DATAuWire_TP CLKuWIRE_TP

LEuWIRE_TP

CMOS,

Input/Output

LMK04906B. The uWire interface includes CLKuWire,

DATAuWire, and LEuWire signals. The programmable logic I/O signals accessible

through this header include: SYNC, Status_Holdover , Status _LD, Status_CLKin0, and Status_CLKin1. These logic I/O signals also have

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 17

Signal Type, Input/Output

Programmable status outp ut pi n. By defaul t, set

output.

Programmable status outp ut pi n. By defaul t, set

loading the output.

Connector Name

Test point:

LD_TP

Not populated:

Status_LD

Description

to output the digital lock detect status signal for PLL1 and PLL2 combined.

In the default CodeLoader modes, LED D5 will illuminate green when PLL lock is detected by the LMK04906B (output is high) and turn off when lock is lost (output is low).

The status output signal for the Status_LD pin can

CMOS,

Output

be selected on the Bits/Pins tab via the LD_MUX control.

Refer to the LMK04906 Family Datasheet section “Status Pins” and “Digital Lock Detect” for more information.

Note: Before a high-frequency inter nal sig nal ( e.g . PLL divider output signal) is selected by LD_MUX, it is suggested to first remove the 270 ohm resistor to prevent the LED from loading the

Test point:

Holdover_TP

CMOS,

Output

to the output holdover mode status signal. In the default CodeLoader mode, LED D8 will

illuminate red when holdover mode is active (output is high) and turn off when holdover mode is not active (output is low).

Refer to the LMK04906 Family Datasheet section “Status Pins” and “Holdover Mode” for more information.

Note: Before a high-frequency internal signal (e.g. PLL divider output signal) is selected by HOLDOVER_MUX, it is suggested to first remove the 270 ohm resistor to prevent the LED from

18 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013

Signal Type, Input/Output

Programmable status I/O pins. By default, set as input

Status_CLKin1

Status_CLKin0

Active Clock

CLKin0

CLKin1

CLKin2

Holdover

Active

Clock

CLKin0

CLKin1

Reserved

“Status Pins” for more information.

Connector Name

pins for controlling input clock switching of CLKin0 and CLKin1.

These inputs will not be functional because CLKin_Select_MODE is set to 0 (CLKin0 Manual) by default in the Bits/Pins tab in CodeLoader. To enable input clock switching, CLKin_Select_MODE must be 3 or 6 and Status_CLKinX_TYPE must be 0 to 3 (pin enabled as an input).

Input Clock Switching – Pin Select Mode

When CLKin_SELECT_MODE is 3, the Status_CLKinX pins select which clock input is active as follows:

Test point: CLKin0_SEL_TP CLKin1_SEL_TP

CMOS,

Input/Output

Input Clock Switching – Auto with Pin Select

When CLKin_SELECT_MODE is 6, the active clock is selected using the Status_CLKinX pins upon an input clock switch event as follows:

Description

Status_CLKin1 Status_CLKin0

Refer to the LMK04906 Family Datasheet

section

“Input Clock Switching” for more information.

Status Outputs

When Status_CLKinX_TYPE is 3 to 6 (pin enabled as an output), the status output signal for the corresponding Status_CLKinX pin can be programmed on the Bits/Pins tab via the Status_CLKinX_MUX control.

Refer to the LMK04906 Family Datasheet

section

Revised - December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A 19

+ 43 hidden pages

Texas Instruments LMK04906 Series, LMK04906B User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

General Description

Evaluation Board Kit Contents

A vailable LMK04906 Ev aluation Bo ards

A vailable LMK04906 F amily Devices

Quick Start

Default CodeLoader Modes for Evaluation Boards

Example: Using CodeLoader to Program the LMK04906B

1. Start CodeLoader 4 A pplication

2. Select Device

3. Program/Load Device

4. Restoring a Default Mode

5. Visual Confirmation of Frequency Lock

6. Enable Clock Outputs

25 MHz VCXO PLL

PLL Loop Filters and Loop Parameters

PLL 1 Loop Filter

PLL2 Loop Filter

Evaluation Board Inputs and Outputs