Texas Instruments LMK04906 Datasheet

LMK04906 LMK04906

10 GbE

PHY

10 GbE

PHY

FPGA NPU SONET SONET

622.08,

155.52, 77.76,

19.44 MHz

Hitless Switching, Jitter

Cleaning, Frequency

Multiplication, and

Programmable Clock

Distribution

Backplane

156.25 MHz LVPECL

100 MHz

LVDS

33.33 MHz LVCMOS

Recovered

³GLUW\´FORFNV

or clean clocks

0XOWLSOH³FOHDQ´

clocks at different frequencies

CLKout2

CLKout3

CLKout0

FPGA

CLKin0

Crystal or

VCXO

Backup Reference Clock

CLKin1

OSCout0

CLKout4

DAC

ADC

LMX2541

PLL+VCO

Serializer/

Deserializer

LMK04906

Precision Clock

Conditioner

CLKout1

CLKin2

CPLD

Product Folder

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Technical Documents

Tools & Software

Support & Community

SNAS589F –JUNE 2012–REVISED AUGUST 2017

LMK04906 Ultralow Noise Clock Jitter Cleaner and Multiplier With

6 Programmable Outputs

LMK04906

1 Features

• Ultralow RMS Jitter Performance – 100-fs RMS Jitter (12 kHz to 20 MHz) – 123-fs RMS Jitter (100 Hz to 20 MHz)

• Dual Loop PLLatinum™ PLL Architecture – PLL1

– Integrated Low-Noise Crystal Oscillator

Circuit

– Holdover Mode when Input Clocks are Lost

– Automatic or Manual

Triggering/Recovery

– PLL2

– Normalized [1 Hz] PLL Noise Floor of –227

dBc/Hz – Phase Detector Rate up to 155 MHz – OSCin Frequency-doubler – Integrated Low-Noise VCO

• 3 Redundant Input Clocks with LOS – Automatic and Manual Switch-Over Modes

• 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)

• LVPECL, LVDS, or LVCMOS Programmable Outputs

• Precision Digital Delay, Fixed or Dynamically Adjustable

• 25-ps Step Analog Delay Control.

• 6 Differential Outputs. Up to 12 Single Ended. – Up to 5 VCXO/Crystal Buffered Outputs

• Clock Rates of up to 2600 MHz

• 0-Delay Mode

• Three Default Clock Outputs at Power Up

• Multi-mode: Dual PLL, Single PLL, and Clock Distribution

• Industrial Temperature Range: –40 to 85 °C

• 3.15-V to 3.45-V Operation

• Package: 64-Pin WQFN (9 mm × 9 mm × 0.8 mm)

System Application Diagram

2 Applications

• 10G, 40G, and 100G OTN Line Cards

• SONET/SDH OC-48/STM-16 and OC-192/STM64 Line Cards

• GbE/10GbE, 1/2/4/8/10GFC Line Cards

• ITU G.709 and Custom FEC Line Cards

• Synchronous Ethernet

• Optical Modules

• DSLAM/MSANs

• Test and Measurement

• Broadcast Video

• Wireless Basestations

• Data Converter Clocking

• Microwave ODU and IDUs for Wireless Backhaul

3 Description

The LMK04906 is the industry's highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.

The LMK04906 accepts 3 clock inputs ranging from 1 kHz to 500 MHz and generates 6 unique clock output frequencies ranging from 284 kHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7thunique clock frequency.

The device provides virtually all frequency translation combinations required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.

The LMK04906 input clock frequency and clock multiplication ratio are programmable through a SPI interface.

Device Information

PART NUMBER VCO FREQUENCY

LMK04906 2370 to 2600 MHz 3 (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified LMK04906 Block Diagram

(1)

REFERENCE

INPUTS

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK04906

SNAS589F –JUNE 2012–REVISED AUGUST 2017

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1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions ...................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements.............................................. 12

6.7 Typical Characteristics............................................ 13

7 Parameter Measurement Information ................ 14

7.1 Charge Pump Current Specification Definitions...... 14

7.2 Differential Voltage Measurement Terminology...... 15

8 Detailed Description............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram....................................... 21

8.3 Feature Description................................................. 21

8.4 Device Functional Modes........................................ 42

8.5 Programming........................................................... 45

8.6 Register Maps......................................................... 48

9 Application and Implementation ........................ 85

9.1 Application Information............................................ 85

9.2 Typical Application ............................................... 101

9.3 System Examples ................................................. 108

9.4 Do's and Don'ts..................................................... 111

10 Power Supply Recommendations ................... 112

10.1 Pin Connection Recommendations..................... 112

10.2 Current Consumption and Power Dissipation

Calculations............................................................ 113

11 Layout................................................................. 115

11.1 Layout Guidelines ............................................... 115

11.2 Layout Example .................................................. 117

12 Device and Documentation Support............... 118

12.1 Device Support.................................................... 118

12.2 Receiving Notification of Documentation

Updates.................................................................. 118

12.3 Community Resource.......................................... 118

12.4 Trademarks......................................................... 118

12.5 Electrostatic Discharge Caution.......................... 118

12.6 Glossary.............................................................. 118

13 Mechanical, Packaging, and Orderable

Information......................................................... 118

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (August 2016) to Revision F Page

• Changed From: CLKout3_PD = 0 To: CLKout2_PD = 0 in Table 7..................................................................................... 37

• Changed From: CLKout3_PD = 0 To: CLKout2_PD = 0 in Table 9..................................................................................... 40

Changes from Revision D (May 2013) to Revision E Page

• Changed 750 to 500............................................................................................................................................................... 1

• Changed 2.26 MHz to 284 kHz .............................................................................................................................................. 1

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Changed Clock Switch Event With Holdover section........................................................................................................... 26

• Deleted Clock Switch Event without Holdover section......................................................................................................... 26

• Changed 5 cycles to 5.5 cycles............................................................................................................................................ 38

• Changed 5 cycles to 5.5 cycles............................................................................................................................................ 41

• Added (Auto modes only)..................................................................................................................................................... 70

• Changed equation ................................................................................................................................................................ 94

Changes from Revision C (May 2013) to Revision D Page

• Changed layout of National Semiconductor Data Sheet to TI format. ............................................................................... 115

Product Folder Links: LMK04906

6364 62 61 60 59 58 57 56 55 54 53

CLKout4

CLKout5*

Status_CLKin0

CLKout4*

Vcc12

CLKout5

Status_CLKin1

Vcc13

DAP

52 51 50 49

CLKout3

Vcc11

CLKout3*

CLKin2*

Vcc3

Vcc4

CLKout2*

CLKout2

GND

FBCLKin/Fin/CLKin1

Status_Holdover

CLKin0

CLKin0*

Vcc5

CLKin2

38 37

Vcc7

CPout2

Vcc9

CLKuWire

OSCin*

OSCout0

OSCout0*

Vcc8

LEuWire

DATAuWire

Vcc10 NC

34 33

CPout1 Status_LD

Vcc6

OSCin

Vcc2

11 12

CLKout0*

CLKout0

SYNC/

Status_CLKin2

Vcc1

LDObyp1

LDObyp2

15 16

13CLKout1

CLKout1*

1817 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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5 Pin Configuration and Functions

LMK04906

SNAS589F –JUNE 2012–REVISED AUGUST 2017

64-Pin WQFN With Exposed Pad

NKD Package

Top View

2, 5, 7, 8, 9, 15,

22, 47, 51, 55,

17, 19

56, 60,

61, 64

NAME NO.

Vcc13 1 — PWR Power Supply for CLKou0

CLKout0*, CLKout0 3, 4 O Programmable Clock output 0. SYNC /

Status_CLKin2 Vcc1 10 — PWR Power supply for VCO LDO. LDObyp1 11 — ANLG LDO Bypass, bypassed to ground with 10 µF capacitor.

(1) See Application and Implementation section for recommended connections.

6 I/O Programmable CLKout Synchronization input or CLKin2 Status output.

I/O TYPE DESCRIPTION

— No Connect These pins must be left floating.

Pin Functions

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(1)

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SNAS589F –JUNE 2012–REVISED AUGUST 2017

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Pin Functions (continued)

NAME NO.

LDObyp2 12 — ANLG LDO Bypass, bypassed to ground with a 0.1 µF capacitor. CLKout1, CLKout1* 13, 14 O Programmable Clock output 1. Vcc2 16 — PWR Power supply for CLKout1. Vcc3 18 — PWR Power supply for CLKout2 CLKout2*, CLKout2 20, 21 O Programmable Clock output 2 GND 23 — PWR Ground Vcc4 24 — PWR Power supply for digital. CLKin1, CLKin1*

FBCLKin, FBCLKin* Fin/Fin* External VCO input (External VCO mode). AC or DC Coupled.

Status_Holdover 27 I/O Programmable

CLKin0, CLKin0* 28, 29 I ANLG Vcc5 30 — PWR Power supply for clock inputs. CLKin2, CLKin2* 31, 32 I ANLG

Status_LD 33 I/O Programmable CPout1 34 O ANLG Charge pump 1 output.

Vcc6 35 — PWR Power supply for PLL1, charge pump 1. OSCin, OSCin* 36, 37 I ANLG Vcc7 38 — PWR Power supply for OSCin port.

OSCout0, OSCout0* 39, 40 O Programmable Buffered output 0 of OSCin port. Vcc8 41 — PWR Power supply for PLL2, charge pump 2. CPout2 42 O ANLG Charge pump 2 output. Vcc9 43 — PWR Power supply for PLL2. LEuWire 44 I CMOS MICROWIRE Latch Enable Input. CLKuWire 45 I CMOS MICROWIRE Clock Input. DATAuWire 46 I CMOS MICROWIRE Data Input. Vcc10 48 — PWR Power supply for CLKout3. CLKout3, CLKout3* 49, 50 O Programmable Clock output 3. Vcc11 52 — PWR Power supply for CLKout4. CLKout4, CLKout4* 53, 54 O Programmable Clock output 4. Vcc12 57 — PWR Power supply for CLKout5. CLKout5, CLKout5* 58, 59 O Programmable Clock output 5.

Status_CLKin0 62 I/O Programmable

Status_CLKin1 63 I/O Programmable

DAP DAP — GND DIE ATTACH PAD, connect to GND.

25, 26 I ANLG

I/O TYPE DESCRIPTION

Reference Clock Input Port 1 for PLL1. AC or DC Coupled. Feedback input for external clock feedback input (0-delay mode).

AC or DC Coupled.

Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming.

Reference Clock Input Port 0 for PLL1. AC or DC Coupled.

Reference Clock Input Port 2 for PLL1, AC or DC Coupled.

Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming.

Feedback to PLL1, Reference input to PLL2. AC Coupled.

Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming.

Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming.

(1)

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SNAS589F –JUNE 2012–REVISED AUGUST 2017

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage Input voltage –0.3 (VCC+ 0.3) V Differential input current (CLKinX/X*,

OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) MSL Moisture sensitivity level 3 T

stg

Junction temperature 150 °C

Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Never to exceed 3.6 V.

(3)

6.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101 Machine model (MM) ±150

(1)(2)

MIN MAX UNIT

–0.3 3.6 V

±5 mA

VALUE UNIT

(1)

±2000

±750

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT

Junction temperature 125 °C Ambient temperature VCC= 3.3 V –40 25 85 °C Supply voltage 3.15 3.3 3.45 V

6.4 Thermal Information

LMK04906

THERMAL METRIC

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 25.2 °C/W Junction-to-case (top) thermal resistance 6.9 °C/W Junction-to-board thermal resistance 4 °C/W Junction-to-top characterization parameter 0.1 °C/W Junction-to-board characterization parameter 4 °C/W Junction-to-case (bottom) thermal resistance 0.8 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITNKD (WQFN)

64 PINS

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6.5 Electrical Characteristics

(3.15 V ≤ VCC≤ 3.45 V, -40 °C ≤ TA≤ 85 °C. Typical values represent most likely parametric norms at VCC= 3.3 V, TA= 25 °C, at the Recommended Operating Conditions at the time of product characterization and are not ensured.)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT CONSUMPTION

CC_PD

CC_CLKS

CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS

CLKin

SLEW

CLKin

VIDCLKin VSSCLKin 0.5 3.1 Vpp VIDCLKin VSSCLKin 0.5 3.1 Vpp

CLKin

CLKin0-offset

CLKin1-offset

CLKin2-offset

CLKinX-offset

CLKin-VIH

CLKin-VIL

FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS

FBCLKin

Fin

FBCLKin/Fin

SLEW

FBCLKin/Fin

(1) Load conditions for output clocks: LVDS: 100 Ω differential. See Current Consumption and Power Dissipation Calculations for ICCfor

specific part configuration and how to calculate ICCfor a specific design. (2) CLKin0, CLKin1, and CLKin2 maximum is specified by characterization, production tested at 200 MHz. (3) Specified by characterization. (4) See Differential Voltage Measurement Terminology for definition of VIDand VODvoltages.

Power Down Supply Current 1 3 mA

All clock delays disabled,

Supply Current with all clocks enabled

(1)

CLKoutX_DIV = 1045, CLKoutX_TYPE = 1 (LVDS),

410 470 mA

PLL1 and PLL2 locked.

Clock Input Frequency

(2)

Clock Input Slew Rate

(3)

Clock Input Differential Input Voltage

(4)

Figure 4

20% to 80% 0.15 0.5 V/ns

AC coupled CLKinX_BUF_TYPE = 0 (Bipolar)

AC coupled CLKinX_BUF_TYPE = 1 (MOS)

0.001 500 MHz

0.25 1.55 |V|

AC coupled to CLKinX; CLKinX* AC

Clock Input Single-ended Input Voltage

(3)

coupled to Ground CLKinX_BUF_TYPE = 0 (Bipolar)

AC coupled to CLKinX; CLKinX* AC coupled to Ground

0.25 2.4 Vpp

CLKinX_BUF_TYPE = 1 (MOS)

DC offset voltage between CLKin0/CLKin0*

20 mV

CLKin0* - CLKin0 DC offset voltage between

CLKin1/CLKin1* CLKin1* - CLKin1

Each pin AC coupled CLKin0_BUF_TYPE = 0 (Bipolar)

0 mV

DC offset voltage between CLKin2/CLKin2*

20 mV

CLKin2* - CLKin2 DC offset voltage between

CLKinX/CLKinX* CLKinX* - CLKinX

High input voltage DC coupled to CLKinX; CLKinX* AC Low input voltage 0 0.4 V

Clock Input Frequency

(3)

Clock Input Frequency

(3)

Single Ended Clock Input Voltage

(3)

Slew Rate on CLKin

(3)

Each pin AC coupled CLKinX_BUF_TYPE = 1 (MOS)

coupled to Ground CLKinX_BUF_TYPE = 1 (MOS)

AC coupled (CLKinX_BUF_TYPE = 0) MODE = 2 or 8; FEEDBACK_MUX = 6

AC coupled (CLKinX_BUF_TYPE = 0) MODE = 3 or 11

AC coupled; (CLKinX_BUF_TYPE = 0)

AC coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0)

55 mV

2 V

0.001 1000 MHz

0.001 3100 MHz

0.25 2 Vpp

0.15 0.5 V/ns

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Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PLL1 SPECIFICATIONS

PD1

SOURCE

CPout1

SINK

CPout1

%MIS

CPout1

CPout1VTUNE

%TEMP

CPout1

TRI

CPout1

PN10kHz

PN1Hz Normalized Phase Noise Contribution

PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS

OSCin

SLEW

OSCin

VIDOSCin VSSOSCin 0.4 3.1 Vpp

OSCin-offset

doubler_max

CRYSTAL OSCILLATOR MODE SPECIFICATIONS

XTAL

(5) This parameter is programmable (6) F

OSCin

(7) See Optional Crystal Oscillator Implementation (OSCin/OSCin*)

PLL1 Phase Detector Frequency 40 MHz

= VCC/2, PLL1_CP_GAIN = 0 100

PLL1 Charge Pump Source Current

(5)

PLL1 Charge Pump Sink Current

(5)

Charge Pump Sink / Source Mismatch

Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage

Charge Pump Current vs. Temperature Variation

Charge Pump TRI-STATELeakage Current

PLL 1/f Noise at 10-kHz offset. Normalized to 1-GHz Output Frequency

CPout1

= VCC/2, PLL1_CP_GAIN = 1 200

CPout1

= VCC/2, PLL1_CP_GAIN = 2 400

CPout1

= VCC/2, PLL1_CP_GAIN = 3 1600

CPout1

CPout1=VCC

CPout1

0.5 V < V TA= 25 °C

/2, PLL1_CP_GAIN = 0 –100 /2, PLL1_CP_GAIN = 1 –200 /2, PLL1_CP_GAIN = 2 –400 /2, PLL1_CP_GAIN = 3 –1600

= VCC/2, T = 25 °C 3% 10

< VCC- 0.5 V

CPout1

0.5 V < V

< VCC- 0.5 V 5 nA

CPout

PLL1_CP_GAIN = 400 µA –117 PLL1_CP_GAIN = 1600 µA –118 PLL1_CP_GAIN = 400 µA –221.5

PLL1_CP_GAIN = 1600 µA –223

PLL2 Reference Input

(6)

PLL2 Reference Clock minimum slew rate on OSCin

Input Voltage for OSCin or OSCin*

(3)

Differential voltage swing

Figure 4

20% to 80% 0.15 0.5 V/ns AC coupled; Single-ended (Unused pin

AC coupled to GND)

AC coupled

0.2 2.4 Vpp

0.2 1.55 |V|

DC offset voltage between OSCin/OSCin*

Each pin AC coupled 20 mV

OSCinX* - OSCinX Doubler input frequency

Crystal frequency range

(3)

Crystal power dissipation

(3)

(7)

Input capacitance of LMK04906 OSCin port

EN_PLL2_REF_2X = 1; OSCin Duty Cycle 40% to 60%

< 40 Ω 6 20.5 MHz

ESR

Vectron VXB1 crystal, 20.48 MHz, R

< 40 Ω

ESR

XTAL_LVL = 0

100 µW

–40 to +85 °C 6 pF

maximum frequency specified by characterization. Production tested at 200 MHz.

µA

dBc/Hz

500 MHz

155 MHz

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Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PLL2 PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS

PD2

SOURCE PLL2 charge pump source current

CPout

SINK PLL2 charge pump sink current

CPout

%MIS Charge pump sink/source mismatch V

CPout2

CPout2VTUNE

%TEMP

CPout2

TRI Charge pump leakage 0.5 V < V

CPout2

PN10kHz

PN1Hz Normalized phase noise contribution

INTERNAL VCO SPECIFICATIONS

VCO

|ΔTCL|

(8) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L

noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L

kHz) - 20log(Fout / 1 GHz), where L

L(f). To measure L

crystal are important to isolating this noise source from the total phase noise, L(f). L

oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L

and L (9) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L

PLL_flat

PN1HZ=L

bandwidth and f (10) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was

at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register,

even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if

the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R30 register to

ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the

frequency range of -40 °C to 85 °C without violating specifications.

Phase detector frequency 155 MHz

(5)

Magnitude of charge pump current vs charge pump voltage variation

Charge pump current vs temperature variation

PLL 1/f noise at 10-kHz offset

(8)

. Normalized to

1-GHz output frequency

CPout2=VCC

CPout2=VCC CPout2=VCC

0.5 V < V TA= 25 °C

PLL2_CP_GAIN = 400 µA –118 PLL2_CP_GAIN = 3200 µA –121 PLL2_CP_GAIN = 400 µA –222.5

(9)

/2, PLL2_CP_GAIN = 0 100 /2, PLL2_CP_GAIN = 1 400 /2, PLL2_CP_GAIN = 2 1600 /2, PLL2_CP_GAIN = 3 3200 /2, PLL2_CP_GAIN = 0 –100 /2, PLL2_CP_GAIN = 1 –400 /2, PLL2_CP_GAIN = 2 –1600 /2, PLL2_CP_GAIN = 3 –3200 /2, TA= 25 °C 3% 10%

< VCC- 0.5 V

CPout2

< VCC– 0.5 V 10 nA

CPout2

PLL2_CP_GAIN = 3200 µA –227

VCO tuning range LMK04906 2370 2600 MHz Fine tuning sensitivity

(The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning

LMK04906 16 to 21 MHz/V range, and the higher tuning sensitivity is typical at the higher end of the tuning range).

Allowable temperature drift for continuous lock

(10) (3)

(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean

PLL_flicker

(f) is the single side band phase noise of only the flicker noise's contribution to total noise,

After programming R30 for lock, no

changes to output configuration are

permitted to guarantee continuous lock

(f), which is dominant close to the carrier. Flicker

PLL_flicker

(f) can be masked by the reference

PLL_flicker

125 °C

PLL_flicker

(f).

(f), is defined as:

(f) - 20log(N) - 10log(f

PLL_flat

is the phase detector frequency of the synthesizer. L

PDX

). L

(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz

PLL_flat

(f) contributes to the total noise, L(f).

PLL_flat

µA

dBc/Hz

(10

PLL_flicker

(f)

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Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CLKout CLOSED LOOP JITTER SPECIFICATIONS USING A COMMERCIAL QUALITY VCXO

Offset = 1 kHz –122.5

Offset = 10 kHz –132.9

Offset = 100 kHz –135.2

Offset = 800 kHz –143.9

Offset = 10 MHz; LVDS –156

Offset = 10 MHz; LVPECL 1600 mVpp –157.5

L(f)

CLKout

LMK04906 f

= 245.76 MHz

CLKout

SSB phase noise Measured at clock outputs Value is average for all output types

(12)

Offset = 10 MHz; LVCMOS –157.1

CLKout

LVDS/LVPECL/ LVCMOS

LMK04906 f

CLKout

Integrated RMS jitter

(12)

= 245.76 MHz

BW = 12 kHz to 20 MHz 115

BW = 100 Hz to 20 MHz 123

CLKout CLOSED LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW NOISE CRYSTAL OSCILLATOR CIRCUIT

LMK04906 f

= 245.76 MHz

CLKout

Integrated RMS jitter

BW = 12 kHz to 20 MHz

XTAL_LVL = 3

BW = 100 Hz to 20 MHz

XTAL_LVL = 3

DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY

Default output clock frequency at

CLKout-startup

device power on

(14)

CLKout4, LVDS, LMK04906 90 98 110 MHz

CLOCK SKEW AND DELAY

LVDS-to-LVDS, T = 25 °C,

= 800 MHz, RL= 100 Ω

CLK

AC coupled

LVPECL-to-LVPECL,

T = 25 °C,

= 800 MHz, RL= 100 Ω

CLK

emitter resistors =

SKEW

Maximum CLKoutX to CLKoutY

(15) (3)

240 Ω to GND

AC coupled

MixedT

SKEW

Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout

(15) (3)

LVDS or LVPECL to LVCMOS

RL= 50 Ω, CL= 5 pF,

T = 25 °C, F

(15)

= 100 MHz.

CLK

Same device, T = 25 °C,

250 MHz

MODE = 2

PLL1_R_DLY = 0; PLL1_N_DLY = 0

MODE = 2

PLL1_R_DLY = 0; PLL1_N_DLY = 0;

VCO Frequency = 2949.12 MHz

Analog delay select = 0;

0-DELAY

CLKin to CLKoutX delay

(15)

Feedback clock digital delay = 11;

Feedback clock half step = 1;

Output clock digital delay = 5;

Output clock half step = 0;

(11)

dBc/Hz

(13)

192

450

100

750 ps

1850

fs rms

(11) VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. (12) f

= 2457.6 MHz, PLL1 parameters: EN_PLL2_REF_2X = 1, PLL2_R = 2, F

VCO

A 122.88 MHz Crystek CVHD-950–122.880. PLL2 parameters: PLL2_R = 1, F nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_DIV = 10, and

= 1.024 MHz, I

PD1

= 122.88 MHz, I

PD2

= 100 μA, loop bandwidth = 10 Hz.

CP1

= 3200 μA, C1 = 47 pF, C2 = 3.9

CP2

CLKoutX_ADLY_SEL = 0. (13) Crystal used is a 20.48 MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF. (14) CLKout3 and OSCout0 also oscillate at start-up at the frequency of the VCXO attached to OSCin port. (15) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid

for delay mode.

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Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1

CLKout

ΔV

TR/ T

SAB

LVPECL CLOCK OUTPUTS (CLKoutX)

CLKout

TR/ T

700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2

1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3

1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4

(16) See Typical Characteristics for output operation performance at higher frequencies than the minimum maximum output frequency.

Maximum frequency

(3) (16)

Differential output voltage

Figure 5

Change in Magnitude of VODfor complementary output states

Output offset voltage 1.125 1.25 1.375 V Change in VOSfor complementary

output states Output rise time 20% to 80%, RL = 100 Ω Output fall time 80% to 20%, RL = 100 Ω Output short-circuit current: single

ended

RL= 100 Ω 1536 MHz

250 400 450 |mV| 500 800 900 mVpp

T = 25 °C, DC measurement AC coupled to receiver input

–50 50 mV

R = 100 Ω differential termination

35 |mV|

200 ps

Single-ended output shorted to GND, T = 25 °C

–24 24 mA

Output short-circuit current: differential Complimentary outputs tied together –12 12 mA

Maximum frequency

(3) (16)

1536 MHz

20% to 80% output rise RL = 100 Ω, emitter resistors = 240 Ω

80% to 20% output fall time

Output high voltage

Output low voltage

Output voltage

Figure 5

Output high voltage

Output low voltage

Output voltage

Figure 5

Output high voltage

Output low voltage

Output voltage

Figure 5

to GND CLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp)

T = 25 °C, DC measurement Termination = 50 Ω to VCC- 1.4 V

T = 25 °C, DC measurement Termination = 50 Ω to VCC– 1.7 V

T = 25 °C, DC Measurement Termination = 50 Ω to VCC– 2 V

305 380 440 |mV| 610 760 880 mVpp

545 625 705 |mV|

1090 1250 1410 mVpp

660 870 965 |mV|

1320 1740 1930 mVpp

150 ps

VCC–

1.03

VCC–

1.41

VCC–

1.07

VCC–

1.69

VCC–

1.10

VCC–

1.97

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Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5

Output high voltage

Output low voltage

Output voltage

Figure 5

T = 25 °C, DC Measurement Termination = 50 Ω to VCC– 2.3 V

LVCMOS CLOCK OUTPUTS (CLKoutX)

CLKout

DUTY

CLK

Maximum frequency

(3) (16)

5-pF Load 250 MHz

Output high voltage 1-mA Load Output low voltage 1-mA Load 0.1 V

Output high current (source) VCC= 3.3 V, VO= 1.65 V 28 mA Output low current (sink) VCC= 3.3 V, VO= 1.65 V 28 mA Output duty cycle

(3)

Output rise time

Output fall time

VCC/2 to VCC/2, F 25 °C

20% to 80%, RL = 50 Ω, CL = 5 pF

80% to 20%, RL = 50 Ω, CL = 5 pF

DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC)

High-level output voltage IOH= -500 µA Low-level output voltage IOL= 500 µA 0.4 V

DIGITAL INPUTS (Status_CLKinX, SYNC)

High-level input voltage 1.6 V Low-level input voltage 0.4 V

Status_CLKinX_TYPE = 0 (High Impedance)

High-level input current VIH= V

Status_CLKinX_TYPE = 1 (Pull-up)

Status_CLKinX_TYPE = 2 (Pull-down)

Status_CLKinX_TYPE = 0 (High Impedance)

Low-level input current VIL= 0 V

Status_CLKinX_TYPE = 1 (Pull-up)

Status_CLKinX_TYPE = 2 (Pulldown)

DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)

High-level input voltage 1.6 V Low-level input voltage 0.4 V High-level input current VIH= V

Low-level input current VIL= 0 –5 5 µA

= 100 MHz, T =

CLK

1600 2140 2400 mVpp

VCC–

45% 50% 55%

VCC–

1.13

VCC–

2.20

800 1070 1200 |mV|

0.1

400 ps

0.4

–5 5

µA

10 80

–5 5

–40 –5

µA

–5 5

5 25 µA

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6.6 Timing Requirements

T T T T T T T T

ECS DCS CDH CWH CWL CES EWH CR

LE to Clock Set Up Time See Figure 6 25 ns Data to Clock Set Up Time See Figure 6 25 ns Clock to Data Hold Time See Figure 6 8 ns Clock Pulse Width High See Figure 6 25 ns Clock Pulse Width Low See Figure 6 25 ns Clock to LE Set Up Time See Figure 6 25 ns LE Pulse Width See Figure 6 25 ns Falling Clock to Readback Time See Figure 9 25 ns

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MIN NOM MAX UNIT

Product Folder Links: LMK04906

0 500 1000 1500 2000 2500 3000

200

400

600

800

1000

1200

(mV)

FREQUENCY (MHz)

2000 mVpp

1600 mVpp

0 500 1000 1500 2000 2500 3000

100

150

200

250

300

350

400

450

500

(mV)

FREQUENCY (MHz)

0 500 1000 1500 2000 2500 3000

200

400

600

800

1000

1200

(mV)

FREQUENCY (MHz)

2000 mVpp 1600 mVpp 1200 mVpp 700 mVpp

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6.7 Typical Characteristics

Figure 1. LVDS VODvs Frequency Figure 2. LVPECL With 240-Ω Emitter Resistors VODvs

LMK04906

SNAS589F –JUNE 2012–REVISED AUGUST 2017

Frequency

Figure 3. LVPECL With 120-Ω Emitter Resistors VODvs Frequency

Product Folder Links: LMK04906

CPout CPout

I2 I5

= ´

CPout CPout

I1 I3

= ´

I4 I6

100%

I4 I6

= ´

LMK04906

SNAS589F –JUNE 2012–REVISED AUGUST 2017

7 Parameter Measurement Information

7.1 Charge Pump Current Specification Definitions

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I1 = Charge Pump Sink Current at V I2 = Charge Pump Sink Current at V I3 = Charge Pump Sink Current at V I4 = Charge Pump Source Current at V I5 = Charge Pump Source Current at V I6 = Charge Pump Source Current at V ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage

7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch

CPout CPout CPout

= VCC- ΔV = VCC/2 = ΔV

Product Folder Links: LMK04906

GND

VID = | VA - VB |

VSS = 2·V

VID Definition VSS Definition for Input

Non-Inverting Clock

Inverting Clock

2·V

2 T 2

T 25 C

CPout A

2 T 25 C

I I

= °

= ´

5 T 5

T 25 C

5 T 25 C

I I

100%

= °

= ´

LMK04906

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SNAS589F –JUNE 2012–REVISED AUGUST 2017

Charge Pump Current Specification Definitions (continued)

7.1.3 Charge Pump Output Current Magnitude Variation vs Temperature

7.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measurement is typically VIDor VODdepending on if an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second measurement is VSSand is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSScan be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VODas described in the first description.

Figure 4 illustrates the two different definitions side-by-side for inputs and Figure 5 illustrates the two different

definitions side-by-side for outputs. The VIDand VODdefinitions show VAand VBDC levels that the non-inverting and inverting signals toggle between with respect to ground. VSSinput and output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.

VIDand VODare often defined as volts (V) and VSSis often defined as volts peak-to-peak (VPP).

Figure 4. Two Different Definitions for Differential Input Signals

Product Folder Links: LMK04906

GND

VOD = | VA - VB |

VSS = 2·V

VOD Definition VSS Definition for Output

Non-Inverting Clock

Inverting Clock

2·V

LMK04906

SNAS589F –JUNE 2012–REVISED AUGUST 2017

Differential Voltage Measurement Terminology (continued)

See the AN-912 Common Data Transmission Parameters and Their Definitions (SNLA036) application note for more information.

Figure 5. Two Different Definitions for Differential Output Signals

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8 Detailed Description

8.1 Overview

In default mode of operation, dual PLL mode with internal VCO, the Phase Frequency Detector in PLL1 compares the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external VCXO or crystal attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1 should be narrow to provide an ultra clean reference clock from the external VCXO or crystal to the OSCin/OSCin* pins for PLL2.

The Phase Frequency Detector in PLL2 compares the external VCXO or crystal attached to the OCSin port divided by the PLL2 R divider with the output of the internal VCO divided by the PLL2 N divider and N2 prescaler and optionally the VCO divider. The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is also placed on the distribution path for the clock distribution section. The clock distribution consists of 6 dividers and delays which drive 6 outputs. Each clock output allows the user to select a divide value, a digital delay value, and an analog delay. The 6 dividers drive programmable output buffers. Two outputs allow their input signal to be from the OSCin port directly.

When a 0-delay mode is used, a clock output will be passed through the feedback mux to the PLL1 N Divider for synchronization and 0-delay.

When an external VCO mode is used, the Fin port will be used to input an external VCO signal. PLL2 Phase comparison will now be with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may not be used. One less clock input is available when using an external VCO mode.

When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.

8.1.1 System Architecture

The dual loop PLL architecture of the LMK04906 provides the lowest jitter performance over the widest range of output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. This “cleaned” reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or tunable crystal.

Ultra low jitter is achieved by allowing the external VCXO or Crystal’s phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

The LMK04906 allows subsets of the device to be used to increase the flexibility of device. These different modes are selected using MODE: Device Mode. For instance:

• Dual Loop Mode - Typical use case of LMK04906. CLKinX used as reference input to PLL1, OSCin port is

connected to VCXO or tunable crystal.

• Single Loop Mode - Powers down PLL1. OSCin port is used as reference input.

• Clock Distribution Mode - Allows input of CLKin1 to be distributed to output with division, digital delay, and

analog delay.

See Device Functional Modes for more information on these modes.

8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0, CLKin1/CLKin1, and CLKin2/CLKin2*)

The LMK04906 has three reference clock inputs for PLL1, CLKin0, CLKin1, and CLKin2. Ref Mux selects CLKin0, CLKin1, or CLKin2. Automatic or manual switching occurs between the inputs.

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Overview (continued)

CLKin0, CLKin1, and CLKin2 each have input dividers. The input divider allows different clock input frequencies to be normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching. By programming these dividers such that the frequency presented to the input of the PLL1_R divider is the same prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another CLKin port with a different frequency.

CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin). Fast manual switching between reference clocks is possible with a external pins Status_CLKin0, Status_CLKin1,

Status_CLKin2. If Status_CLKinx pins are used to select the reference clock, a minimum pulse width of 500ns must be met.

8.1.3 PLL1 Tunable Crystal Support

The LMK04906 integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to perform jitter cleaning.

The LMK04906 must be programmed to enable Crystal mode.

8.1.4 VCXO/Crystal Buffered Outputs

The LMK04906 provides a dedicated output which is a buffered copy of the PLL2 reference input. This reference input is typically a low noise VCXO or Crystal. When using a VCXO, this output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, etc. before the LMK04906 is programmed.

The OSCout0 buffer output type is programmable to LVDS, LVPECL, or LVCMOS. The dedicated output buffer OSCout0 can output frequency lower than the VCXO or Crystal frequency by

programming the OSC Divider. The OSC Divider value range is 1 to 8. Each OSCoutX can individually choose to use the OSC Divider output or to bypass the OSC Divider.

Two clock outputs can also be programmed to be driven by OSCin. This allows a total of 2 additional differential outputs to be buffered outputs of OSCin. When programmed in this way, a total of 3 differential outputs can be driven by a buffered copy of OSCin.

VCXO/Crystal buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion of SYNC will still cause these outputs to become low. Since these outputs will turn off and on asynchronously with respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur on the buffered clock outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX bits are set these outputs will not be affected by the SYNC event except that the phase relationship will change with the other synchronized clocks unless a buffered clock output is used as a qualification clock during SYNC.

8.1.5 Frequency Holdover

The LMK04906 supports holdover operation to keep the clock outputs on frequency with minimum drift when the reference is lost until a valid reference clock signal is re-established.

8.1.6 Integrated Loop Filter Poles

The LMK04906 features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter response. The integrated programmable resistors and capacitors compliment external components mounted near the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors to their minimum values.

8.1.7 Internal VCO

The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or a divided version of the VCO for the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and N-divider.

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Overview (continued)

The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd divide values.

The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.

8.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04906. Using an external VCO reduces the number of available clock inputs by one.

8.1.9 Clock Distribution

The LMK04906 features a total of 6 outputs driven from the internal or external VCO. All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or

LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 24 outputs are available.

If the buffered OSCin output OSCout0 is included in the total number of clock outputs the LMK04906 is able to distribute, then up to 6 differential clocks or up to 12 single ended clocks may be generated with the LMK04906.

The following sections discuss specific features of the clock distribution channels that allow the user to control various aspects of the output clocks.

8.1.9.1 CLKout DIVIDER

Each clock output has a single clock output divider. The divider supports a divide range of 1 to 1045 (even and odd) with 50% output duty cycle. When divides of 26 or greater are used, the divider/delay block uses extended mode.

The VCO Divider may be used to reduce the divide needed by the clock output divider so that it may operate in normal mode instead of extended mode. This can result in a small current saving if enabling the VCO Divider allows 3 or more clock output divides to change from extended to normal mode.

8.1.9.2 CLKout Delay

The clock distribution section includes both a fine (analog) and coarse (digital) delay for phase adjustment of the clock outputs.

The fine (analog) delay allows a nominal 25 ps step size and range from 0 to 475 ps of total delay. Enabling the analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay, glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the minimum-specified maximum output frequency of 1536 MHz.

The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the period of the clock distribution path by using the CLKoutX_HS bit provided the output divide value is greater than

1. For example 2 GHz VCO frequency without using the VCO divider results in 250 ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

There are 3 different ways to use the digital (coarse) delay.

1. Fixed Digital Delay

2. Absolute Dynamic Digital Delay

3. Relative Dynamic Digital Delay

8.1.9.3 Programmable Output Type

For increased flexibility all LMK04906 clock outputs (CLKoutX) and OSCout0 can be programmed to an LVDS, LVPECL, or LVCMOS output type.

Any LVPECL output type can be programmed to 700, 1200, 1600, or 2000 mVpp amplitude levels. The 2000 mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000 mVpp differential swing for compatibility with many data converters and is also known as 2VPECL.

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Overview (continued)

8.1.9.4 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge. See Clock Output Synchronization

(SYNC) for more information.

The SYNC event also causes the digital delay values to take effect.

8.1.10 0-Delay

The 0-delay mode synchronizes the input clock phase to the output clock phase. The 0-delay feedback may performed with an internal feedback loop from some of the clock outputs or with an external feedback loop into the FBCLKin port as selected by the FEEDBACK_MUX.

Without using 0-delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

8.1.11 Default Start-Up Clocks

Before the LMK04906 is programmed, CLKout4 is enabled and operating at a nominal frequency and CLKout3 and OSCout0 are enabled and operating at the OSCin frequency. These clocks can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, etc. before the LMK04906 is programmed.

For CLKout3 and OSCout0 to work before the LMK04906 is programmed the device must not be using Crystal mode.

8.1.12 Status Pins

The LMK04906 provides status pins which can be monitored for feedback or in some cases used for input depending upon device programming. For example:

• The Status_Holdover pin may indicate if the device is in hold-over mode.

• The Status_CLKin0 pin may indicate the LOS (loss-of-signal) for CLKin0.

• The Status_CLKin0 pin may be an input for selecting the active clock input.

• The Status_LD pin may indicate if the device is locked. The status pins can be programmed to a variety of other outputs including analog lock detect, PLL divider

outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, and so forth. See Status PINS of this data sheet for more information. Default pin programming is captured in Table 17.

8.1.13 Register Readback

Programmed registers may be read back using the MICROWIRE interface. For readback one of the status pins must be programmed for readback mode.

At no time may registers be programed to values other than the valid states defined in the data sheet.

Product Folder Links: LMK04906

CLKuWire

DATAuWire

LEuWire

R1 Divider

(1 to 16,383)

CPout1

Internal VCO

Partially

Integrated

Loop Filter

Mux

R Delay

N Delay

OSCin*

OSCin

Mux

Control

Registers

PWire

Port

SYNC/

Status_CLKin2

Status_LD Status_Holdover Status_CLKin0

Device Control

Status_CLKin1

Holdover

CLKin0*

CLKin0

Divider

(1 to 1045)

Digital

Delay

CLKout1 CLKout3 CLKout4 CLKout5

VCO Divider

(2 to 8)

Osc

Mux1

Osc

Mux2

CPout2

CLKin0 Divider

(1, 2, 4, or 8)

N1 Divider

(1 to 16,383)

R2 Divider

(1 to 4,095)

Phase

Detector

PLL1

Phase

Detector

PLL2

N2 Divider

(1 to 262,143)

Delay

Clock Buffer 2

Clock Buffer 1

Clock Buffer 3

Clock Distribution PathN2 Prescaler

(2 to 8)

VCO Mux

Fin/Fin*

CLKin1 Divider

(1, 2, 4, or 8)

OSCout0

OSCout0*

OSCout0

_MUX

OSC Divider

(2 to 8)

CLKin1*/Fin* FBCLKin* CLKin1/ Fin/FBCLKin

Mode Mux2

Mode Mux1

OSCout0

_MUX

Mode Mux3

FBMux

CLKin2*

CLKin2

CLKin2 Divider

(1, 2, 4, or 8)

Ref

Mux

CLKout0

CLKout0*

Mux

Divider

(1 to 1045)

Digital

Delay

CLKout1

CLKout1*

Mux

Divider

(1 to 1045)

Digital

Delay

CLKout2

CLKout2*

Mux

Divider

(1 to 1045)

Digital Delay

Delay

CLKout4

CLKout4*

Mux

Divider

(1 to 1045)

Digital Delay

Delay

CLKout5

CLKout5*

Mux

Divider

(1 to 1045)

Digital Delay

Delay

CLKout3

CLKout3*

Mux

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8.2 Functional Block Diagram

LMK04906

SNAS589F –JUNE 2012–REVISED AUGUST 2017

8.3 Feature Description

8.3.1 Serial MICROWIRE Timing Diagram

Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming. See Figure 6 for timing diagram.

Product Folder Links: LMK04906

D26 A0

MSB LSB

CLKuWire

LEuWire

CES

ECS

D26 A0

MSB LSB

CLKuWire

LEuWire

ECS

EWH

CWH

CWL

CES

DCS

D26 D25 D24 D23

CDH

CWH

CWL

D22 D0 A4 A1 A0

MSB LSB

CLKuWire

LEuWire

CES

EWH

ECS

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SNAS589F –JUNE 2012–REVISED AUGUST 2017

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Feature Description (continued)

Figure 6. MICROWIRE Timing Diagram

8.3.2 Advanced MICROWIRE Timing Diagrams

8.3.2.1 Three Extra Clocks or Double Program

Figure 7 shows the timing for the programming sequence for loading CLKoutX_DIV > 25 or CLKoutX_DDLY > 12

as described in Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY.

Figure 7. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5

8.3.2.2 Three Extra Clocks With LEuWire High

Figure 8 shows the timing for the programming sequence which allows SYNC_EN_AUTO = 1 when loading

CLKoutX_DIV > 25 or CLKoutX_DDLY > 12. When SYNC_EN_AUTO = 1, a SYNC event is automatically generated on the falling edge of LEuWire. See Special Programming Case for R0 to R5 for CLKoutX_DIV and

CLKoutX_DDLY.

Figure 8. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5 With LEuWire Asserted

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D26 A0

MSB LSB

DATAuWire

CLKuWire

LEuWire

ECS

EWH

Readback Pin RD0RD24RD26

LEuWire

CWH

CWL

RD25

RD23

ECS

CES

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Feature Description (continued)

8.3.2.3 Readback

For timing specifications, see Timing Requirements. See Readback for more information on performing a readback operation. Figure 9 shows timing for LEuWire for both READBACK_LE = 1 and 0.

The rising edges of CLKuWire during MICROWIRE readback continue to clock data on DATAuWire into the device during readback. If after the readback, LEuWire transitions from low to high, this data will be latched to the decoded register. The decoded register address consists of the last 5 bits clocked on DATAuWire as shown in the MICROWIRE Timing Diagrams.

Figure 9. MICROWIRE Readback Timing Diagram

8.3.3 Inputs / Outputs

8.3.3.1 PLL1 Reference Inputs (CLKin0, CLKin1, and CLKin2)

The reference clock inputs for PLL1 may be selected from either CLKin0, CLKin1, or CLKin2. The user has the capability to manually select one of the inputs or to configure an automatic switching mode of operation. See

Input Clock Switching for more info.

CLKin0, CLKin1, and CLKin2 have dividers which allow the device to switch between reference inputs of different frequencies automatically without needing to reprogram the PLL1 R divider. The CLKin pre-divider values are 1, 2, 4, and 8.

CLKin1 input can alternatively be used for external feedback in 0-delay mode (FBCLKin) or for an external VCO input port (Fin).

8.3.3.2 PLL2 OSCin / OSCin* Port

The feedback from the external oscillator being locked with PLL1 drives the OSCin/OSCin* pins. Internally this signal is routed to the PLL1 N Divider and to the reference input for PLL2.

This input may be driven with either a single-ended or differential signal and must be AC coupled. If operated in single ended mode, the unused input must be connected to GND with a 0.1-µF capacitor.

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Feature Description (continued)

8.3.3.3 Crystal Oscillator

The internal circuitry of the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, a varactor diode, and a small number of other external components may be used to implement the oscillator. The internal oscillator circuit is enabled by setting the EN_PLL2_XTAL bit. See EN_PLL2_XTAL.

8.3.4 Input Clock Switching

Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the CLKin_SELECT_MODE register.

Below is information about how the active input clock is selected and what causes a switching event in the various clock input selection modes.

8.3.4.1 Input Clock Switching - Manual Mode

When CLKin_SELECT_MODE is 0, 1, or 2 then CLKin0, CLKin1, or CLKin2 respectively is always selected as the active input clock. Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is is disabled with EN_CLKinX = 0.

Entering Holdover

If holdover mode is enabled then holdover mode is entered if:

Digital lock detect of PLL1 goes low and DISABLE_DLD1_DET = 0.

Exiting Holdover

The active clock for automatic exit of holdover mode is the manually selected clock input.

8.3.4.2 Input Clock Switching - Pin Select Mode

When CLKin_SELECT_MODE is 3, the pins Status_CLKin0 and Status_CLKin1 select which clock input is active.

Clock Switch Event: Pins

Changing the state of Status_CLKin0 or Status_CLKin1 pins causes an input clock switch event.

Clock Switch Event: PLL1 DLD

To prevent PLL1 DLD high to low transition from causing a input clock switch event and causing the device to enter holdover mode, disable the PLL1 DLD detect by setting DISABLE_DLD1_DET = 1. This is the preferred behavior for Pin Select Mode.

Configuring Pin Select Mode

The Status_CLKin0_TYPE must be programmed to an input value for the Status_CLKin0 pin to function as an input for pin select mode.

The Status_CLKin1_TYPE must be programmed to an input value for the Status_CLKin1 pin to function as an input for pin select mode.

If the Status_CLKinX_TYPE is set as output, the input value is considered "0."

Table 1 defines which input clock is active depending on Status_CLKin0 and Status_CLKin1 state.

Table 1. Active Clock Input – Pin Select Mode

Status_CLKin1 Status_CLKin0 ACTIVE CLOCK

0 0 CLKin0 0 1 CLKin1 1 0 CLKin2 1 1 Holdover

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The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is is disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX = 1) that could be switched to.

8.3.4.2.1 Pin Select Mode and Host

When in the pin select mode, the host can monitor conditions of the clocking system which could cause the host to switch the active clock input. The LMK04906 device can also provide indicators on the Status_LD and Status_HOLDOVER like "DAC Rail," "PLL1 DLD", "PLL1 & PLL2 DLD" which the host can use in determining which clock input to use as active clock input.

8.3.4.2.2 Switch Event Without Holdover

When an input clock switch event is triggered and holdover mode is disabled, the active clock input immediately switches to the selected clock. When PLL1 is designed with a narrow loop bandwidth, the switching transient is minimized.

8.3.4.2.3 Switch Event With Holdover

When an input clock switch event is triggered and holdover mode is enabled, the device will enter holdover mode and remain in holdover until a holdover exit condition is met as described in Holdover Mode. Then the device will complete the reference switch to the pin selected clock input.

8.3.4.3 Input Clock Switching – Automatic Mode

When CLKin_SELECT_MODE is 4, the active clock is selected in priority order of enabled clock inputs starting upon an input clock switch event. The priority order of the clocks is CLKin0 → CLKin1 → CLKin2, etc.

For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX.

8.3.4.3.1 Starting Active Clock

Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SELECT_MODE to the manual mode which selects the desired clock input (CLKin0, 1, or 2). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SELECT_MODE = 4.

8.3.4.3.2 Clock Switch Event: PLL1 DLD

A loss of lock as indicated by PLL1’s DLD signal (PLL1_DLD = 0) will cause an input clock switch event if DISABLE_DLD1_DET = 0. PLL1 DLD must go high (PLL1_DLD = 1) in between input clock switching events.

8.3.4.3.3 Clock Switch Event: PLL1 V

tune

Rail

If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses the DAC high or low threshold, holdover mode will be entered. Since PLL1_DLD = 0 in holdover a clock input switching event will occur.

8.3.4.3.4 Clock Switch Event With Holdover

Holdover mode is entered and the active clock is set to the next enabled clock input in priority order. When the new active clock meets the holdover exit conditions, holdover is exited and the active clock will continue to be used as a reference until another PLL1 loss of lock event. PLL1 DLD must go high in between input clock switching events.

8.3.4.3.5 Clock Switch Event Without Holdover

If holdover is not enabled and an input clock switch event occurs, the active clock is set to the next enabled clock in priority order. The LMK04906 will keep this new input clock as the active clock until another input clock switching event. PLL1 DLD must go high in between input clock switching events.

8.3.4.4 Input Clock Switching - Automatic Mode With Pin Select

When CLKin_SELECT_MODE is 6, the active clock is selected using the Status_CLKinX pins upon an input clock switch event according to Table 2.

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8.3.4.4.1 Starting Active Clock

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Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SELECT_MODE to the manual mode which selects the desired clock input (CLKin0 or 1). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SELECT_MODE = 6.

8.3.4.4.2 Clock Switch Event: PLL1 DLD

An input clock switch event is generated by a loss of lock as indicated by PLL1's DLD signal (PLL1 DLD = 0).

8.3.4.4.3 Clock Switch Event: PLL1 V

tune

Rail

If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses the DAC threshold, holdover mode will be entered. Since PLL1_DLD = 0 in holdover, a clock input switching event will occur.

8.3.4.4.4 Clock Switch Event With Holdover

Clock switch event with holdover enabled is recommended in this input clock switching mode. When an input clock switch event occurs, holdover mode is entered and the active clock is set to the clock input defined by the Status_CLKinX pins. When the new active clock meets the holdover exit conditions, holdover is exited and the active clock will continue to be used as a reference until another input clock switch event. PLL1 DLD must go high in between input clock switching events.

Table 2. Active Clock Input - Auto Pin Mode

Status_CLKin1 Status_CLKin0 ACTIVE CLOCK

X 1 CLKin0 1 0 CLKin1 0 0 CLKin2

The polarity of Status_CLKin1 and Status_CLKin0 input pins can be inverted with the CLKin_SEL_INV bit.

8.3.5 Holdover Mode

Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed tuning voltage is set on CPout1 to operate PLL1 in open loop.

8.3.5.1 Enable Holdover

Program HOLDOVER_MODE to enable holdover mode. Holdover mode can be manually enabled by programming the FORCE_HOLDOVER bit.

The holdover mode can be set to operate in 2 different sub-modes.

• Fixed CPout1 (EN_TRACK = 0 or 1, EN_MAN_DAC = 1).

• Tracked CPout1 (EN_TRACK = 1, EN_MAN_DAC = 0).

– Not valid when EN_VTUNE_RAIL_DET = 1.

Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector frequency divided by DAC_CLK_DIV. These updates occur any time EN_TRACK = 1.

The DAC update rate should be programmed for <= 100 kHz to ensure DAC holdover accuracy. When tracking is enabled the current voltage of DAC can be readback, see DAC_CNT.

8.3.5.2 Entering Holdover

The holdover mode is entered as described in Input Clock Switching. Typically this is because:

• FORCE_HOLDOVER bit is set.

• PLL1 loses lock according to PLL1_DLD, and

– HOLDOVER_MODE = 2 – DISABLE_DLD1_DET = 0

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VCXO Frequency

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• CPout1 voltage crosses DAC high or low threshold, and

– HOLDOVER_MODE = 2 – EN_VTUNE_RAIL_DET = 1 – EN_TRACK = 1 – DAC_HIGH_TRIP = User Value – DAC_LOW_TRIP = User Value – EN_MAN_DAC = 1 – MAN_DAC = User Value

8.3.5.3 During Holdover

PLL1 is run in open loop mode.

• PLL1 charge pump is set to TRI-STATE.

• PLL1 DLD will be unasserted.

• The HOLDOVER status is asserted

• During holdover If PLL2 was locked prior to entry of holdover mode, PLL2 DLD will continue to be asserted.

• CPout1 voltage will be set to:

– a voltage set in the MAN_DAC register (fixed CPout1). – a voltage determined to be the last valid CPout1 voltage (tracked CPout1).

• PLL1 DLD will attempt to lock with the active clock input. The HOLDOVER status signal can be monitored on the Status_HOLDOVER or Status_LD pin by programming

the HOLDOVER_MUX or LD_MUX register to "Holdover Status."

8.3.5.4 Exiting Holdover

Holdover mode can be exited in one of two ways.

• Manually, by programming the device from the host.

• Automatically, By a clock operating within a specified ppm of the current PLL1 frequency on the active clock

input. See Input Clock Switching for more detail on which clock input is active.

To exit holdover by programming, set HOLDOVER_MODE = Disabled. HOLDOVER_MODE can then be reenabled by programming HOLDOVER_MODE = Enabled. Care should be taken to ensure that the active clock upon exiting holdover is as expected, otherwise the CLKin_SELECT_MODE register may need to be reprogrammed.

8.3.5.5 Holdover Frequency Accuracy and DAC Performance

When in holdover mode PLL1 will run in open loop and the DAC will set the CPout1 voltage. If Fixed CPout1 mode is used, then the output of the DAC will be a voltage dependant upon the MAN_DAC register. If Tracked CPout1 mode is used, then the output of the DAC will be the voltage at the CPout1 pin before holdover mode was entered. When using Tracked mode and EN_MAN_DAC = 1, during holdover the DAC value is loaded with the programmed value in MAN_DAC, not the tracked value.

When in Tracked CPout1 mode the DAC has a worst case tracking error of ±2 LSBs once PLL1 tuning voltage is acquired. The step size is approximately 3.2 mV; therefore, the VCXO frequency error during holdover mode caused by the DAC tracking accuracy is ±6.4 mV × Kv. Where Kv is the tuning sensitivity of the VCXO in use. Therefore the accuracy of the system when in holdover mode in ppm is:

(1)

Example: consider a system with a 19.2 MHz clock input, a 153.6 MHz VCXO with a Kv of 17 kHz/V. The accuracy of the system in holdover in ppm is:

±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz It is important to account for this frequency error when determining the allowable frequency error window to

cause holdover mode to exit.

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8.3.5.6 Holdover Mode - Automatic Exit of Holdover

The LMK04906 device can be programmed to automatically exit holdover mode when the accuracy of the frequency on the active clock input achieves a specified accuracy. The programmable variables include PLL1_WND_SIZE and DLD_HOLD_CNT.

See Digital Lock Detect Frequency Accuracy to calculate the register values to cause holdover to automatically exit upon reference signal recovery to within a user specified ppm error of the holdover frequency.

It is possible for the time to exit holdover to vary because the condition for automatic holdover exit is for the reference and feedback signals to have a time/phase error less than a programmable value. Because it is possible for two clock signals to be very close in frequency but not close in phase, it may take a long time for the phases of the clocks to align themselves within the allowable time/phase error before holdover exits.

8.3.6 PLLs

8.3.6.1 PLL1

PLL1's maximum phase detector frequency (f

) is 40 MHz. Since a narrow loop bandwidth should be used for

PD1

PLL1, the need to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary. The maximum values for the PLL1 R and N dividers is 16,383. Charge pump current ranges from 100 to 1600 µA. PLL1 N divider may be driven by OSCin port at the OSCout0_MUX output (default) or by internal or external feedback as selected by Feedback Mux in 0-delay mode.

Low charge pump currents and phase detector frequencies aid design of low loop bandwidth loop filters with reasonably sized components to allow the VCXO or PLL2 to dominate phase noise inside of PLL2 loop bandwidth. High charge pump currents may be used by PLL1 when using VCXOs with leaky tuning voltage inputs to improve system performance.

8.3.6.2 PLL2

PLL2's maximum phase detector frequency (f

) is 155 MHz. Operating at highest possible phase detector rate

PD2

will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter. The in-band phase noise from the reference input and PLL is proportional to N2. The maximum value for the PLL2 R divider is 4,095. The maximum value for the PLL2 N divider is 262,143. The N2 Prescaler in the total N feedback path can be programmed for values 2 to 8 (all divides even and odd). Charge pump current ranges from 100 to 3200 µA.

High charge pump currents help to widen the PLL2 loop bandwidth to optimize PLL2 performance.

8.3.6.2.1 PLL2 Frequency Doubler

The PLL2 reference input at the OSCin port may be routed through a frequency doubler before the PLL2 R Divider. The frequency doubler feature allows the phase comparison frequency to be increased when a relatively low frequency oscillator is driving the OSCin port. By doubling the PLL2 phase detector frequency, the in-band PLL2 noise is reduced by about 3 dB.

For applications in which the OSCin frequency and PLL2 phase detector frequency are equal, the best PLL2 inband noise can be achieved when the doubler is enabled (EN_PLL2_REF_2X = 1) and the PLL2 R divide value is 2. Do not use doubler disabled (EN_PLL2_REF_2X = 0) and PLL2 R divide value of 1.

When using the doubler take care to use the PLL2 R Divider to reduce the phase detector frequency to the limit of the PLL2 maximum phase detector frequency.

8.3.6.3 Digital Lock Detect

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count reaches a user specified value lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be asserted false. This is illustrated in

Figure 10.

The incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock.

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YES

Phase Error < â

PLLX

Lock Detected = False

Lock Count = 0

PLLX Lock Count =

PLLX_DLD_CNT

Phase Error > â

NO YES

START

Increment

PLLX Lock Count

PLLX

Lock Detected = True

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The digital lock detect signal can be monitored on the Status_LD or Status_Holdover pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.

The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Holdover

Mode for more info.

8.3.7 Status PINS

The Status_LD, Status_HOLDOVER, Status_CLKin0, Status_CLKin1, and SYNC/Status_CLKin2 pins can be programmed to output a variety of signals for indicating various statuses like digital lock detect, holdover, several DAC indicators, and several PLL divider outputs.

8.3.7.1 Logic Low

This is a vary simple output. In combination with the output _MUX register, this output can be toggled between high and low. Useful to confirm MICROWIRE programming or as a general purpose IO.

8.3.7.2 Digital Lock Detect

PLL1 DLD, PLL2 DLD, and PLL1 + PLL2 are selectable on certain output pins. See Digital Lock Detect for more information.

Figure 10. Digital Lock Detect Flowchart

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8.3.7.3 Holdover Status

Indicates if the device is in Holdover mode. See Holdover Mode for more information.

8.3.7.4 DAC

Various flags for the DAC can be monitored including DAC Locked, DAC Rail, DAC Low, and DAC High. When the PLL1 tuning voltage crosses the low threshold, DAC Low is asserted. When PLL1 tuning voltage

crosses the high threshold, DAC High is asserted. When either DAC Low or DAC High is asserted, DAC Rail will also be asserted.

DAC Locked is asserted when EN_Track = 1 and DAC is closely tracking the PLL1 tuning voltage.

8.3.7.5 PLL Divider Outputs

The PLL divider outputs are useful for debugging failure to lock issues. It allows the user to measure the frequency the PLL inputs are receiving. The settings of PLL1_R, PLL1_N, PLL2_R, and PLL2_N output pulses at the phase detector rate. The settings of PLL1_R / 2, PLL1_N / 2, PLL2_R / 2, and PLL2_N / 2 output a 50% duty cycle waveform at half the phase detector rate.

8.3.7.6 CLKinX_LOS

The clock input loss of signal indicator is asserted when LOS is enabled (EN_LOS) and the clock no longer detects an input as defined by the time-out threshold, LOS_TIMEOUT. The loss of signal indicator detects a loss of signal on CLKinX only when CLKinX_BUF_TYPE is configured as Bipolar.

8.3.7.7 CLKinX Selected

If this clock is the currently selected/active clock, this pin will be asserted.

8.3.7.8 MICROWIRE Readback

The readback data can be output on any pin programmable to readback mode. For more information on readback see Readback.

8.3.8 VCO

The integrated VCO uses a frequency calibration routine when register R30 is programmed to lock VCO to target frequency. Register R30 contains the PLL2_N register.

During the frequency calibration the PLL2_N_CAL value is used instead of PLL2_N, this allows 0-delay modes to have a separate PLL2 N value for VCO frequency calibration and regular operation.

8.3.9 Clock Distribution

8.3.9.1 Fixed Digital Delay

This section discussing Fixed Digital delay and associated registers is fundamental to understanding digital delay and dynamic digital delay.

Clock outputs may be delayed or advanced from one another by up to 517.5 clock distribution path periods. By programming a digital delay value from 4.5 to 522 clock distribution path periods, a relative clock output delay from 0 to 517.5 periods is achieved. The CLKoutX_DDLY (5 to 522) and CLKoutX_HS (–0.5 or 0) registers set the digital delay as shown in Table 3.

Table 3. Possible Digital Delay Values

CLKoutX_DDLY CLKoutX_HS Digital Delay

5 1 4.5 5 0 5 6 1 5.5 6 0 6 7 1 6.5

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+ 96 hidden pages

Texas Instruments LMK04906 Datasheet

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Timing Requirements

6.7 Typical Characteristics

7 Parameter Measurement Information

7.1 Charge Pump Current Specification Definitions

7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage

7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch

7.1.3 Charge Pump Output Current Magnitude Variation vs Temperature

7.2 Differential Voltage Measurement Terminology

8 Detailed Description

8.1 Overview

8.1.1 System Architecture

8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)

8.1.3 PLL1 Tunable Crystal Support

8.1.4 VCXO/Crystal Buffered Outputs

8.1.5 Frequency Holdover

8.1.6 Integrated Loop Filter Poles

8.1.7 Internal VCO

8.1.8 External VCO Mode

8.1.9 Clock Distribution

8.1.9.1 CLKout DIVIDER

8.1.9.2 CLKout Delay

8.1.9.3 Programmable Output Type

8.1.9.4 Clock Output Synchronization

8.1.10 0-Delay

8.1.11 Default Start-Up Clocks

8.1.12 Status Pins

8.1.13 Register Readback

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Serial MICROWIRE Timing Diagram

8.3.2 Advanced MICROWIRE Timing Diagrams

8.3.2.1 Three Extra Clocks or Double Program

8.3.2.2 Three Extra Clocks With LEuWire High

8.3.2.3 Readback

8.3.3 Inputs / Outputs

8.3.3.1 PLL1 Reference Inputs (CLKin0, CLKin1, and CLKin2)

8.3.3.2 PLL2 OSCin / OSCin* Port

8.3.3.3 Crystal Oscillator

8.3.4 Input Clock Switching

8.3.4.1 Input Clock Switching - Manual Mode

8.3.4.2 Input Clock Switching - Pin Select Mode

8.3.4.3 Input Clock Switching – Automatic Mode

8.3.4.4 Input Clock Switching - Automatic Mode With Pin Select

8.3.5 Holdover Mode

8.3.5.1 Enable Holdover

8.3.5.2 Entering Holdover

8.3.5.3 During Holdover

8.3.5.4 Exiting Holdover

8.3.5.5 Holdover Frequency Accuracy and DAC Performance

8.3.5.6 Holdover Mode - Automatic Exit of Holdover

8.3.6 PLLs

8.3.6.1 PLL1

8.3.6.2 PLL2

8.3.6.3 Digital Lock Detect

8.3.7 Status PINS

8.3.7.1 Logic Low

8.3.7.2 Digital Lock Detect

8.3.7.3 Holdover Status

8.3.7.4 DAC

8.3.7.5 PLL Divider Outputs

8.3.7.6 CLKinX_LOS

8.3.7.7 CLKinX Selected

8.3.7.8 MICROWIRE Readback

8.3.8 VCO

8.3.9 Clock Distribution

8.3.9.1 Fixed Digital Delay

8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0, CLKin1/CLKin1, and CLKin2/CLKin2*)