Texas Instruments LM86CIM Schematic [ru]

LM86

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SNIS114E –DECEMBER 2001–REVISED MARCH 2013

±0.75°C Accurate, Remote Diode and Local Digital Temperature Sensor With Two-Wire

Interface

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FEATURES

• Accurately Senses Die Temperature of Remote ICs or Diode Junctions

• Offset Register Allows Sensing a Variety of Thermal Diodes Accurately

• On-Board Local Temperature Sensing

• 10-Bit Plus Sign Remote Diode Temperature Data Format, 0.125°C Resolution

• T_CRIT_A Output Useful for System Shutdown

• ALERT Output Supports SMBus 2.0 Protocol

• SMBus 2.0 Compatible Interface, Supports TIMEOUT

• 8-Pin VSSOP and SOIC Packages

APPLICATIONS

• Computer System Thermal Management (For Example, Laptop, Desktop, Workstations, Server)

• Electronic Test Equipment

• Office Electronics

KEY SPECIFICATIONS

• Supply Voltage 3.0V to 3.6V

• Supply Current 0.8mA (typ)

• Local Temp Accuracy (includes quantization error)

– TA=25°C to 125°C, ±3.0°C (max)

• Remote Diode Temp Accuracy (includes quantization error)

– TA=30°C, TD=80°C, ±0.75°C (max) – TA=30°C to 50°C, TD=60°C to 100°C, ±1.0°C

(max)

– TA=0°C to 85°C, TD=25°C to 125°C, ±3.0°C

(max)

DESCRIPTION

The LM86 is an 11-bit digital temperature sensor with a 2-wire System Management Bus (SMBus) serial interface. The LM86 accurately measures its own temperature as well as the temperature of an external device, such as processor thermal diode or diode connected transistor such as the 2N3904. The temperature of any ASIC can be accurately determined using the LM86 as long as a dedicated diode (semiconductor junction) is available on the target die. The LM86 remote sensor accuracy of ±0.75°C is factory trimmed for the 1.008 typical nonideality factor of the mobile Pentium™ III thermal diode. The LM86 has an Offset register to allow measuring other diodes without requiring continuous software management. Contact hardware.monitor.team@nsc.com to obtain the latest data for new processors.

Activation of the ALERT output occurs when any temperature goes outside a preprogrammed window set by the HIGH and LOW temperature limit registers or exceeds the T_CRIT temperature limit. Activation of the T_CRIT_A occurs when any temperature exceeds the T_CRIT programmed limit. The LM86 is pin and register compatible with the the Analog Devices ADM1032 and Maxim MAX6657/8.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Pentium is a trademark of Intel Corporation.. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Control Logic

One Shot

Remote Offset

Registers

Local/Remote

Temperature

Registers

HIGH Limit

Registers

LOW Limit

Registers

T_CRIT Limit & Hysteresis

Registers

Configuration

and Status

Registers

Conversion

Rate

Registers

Two-Wire Serial

Interface

Local/Remote

Diode Selector

Temperature

Sensor

Circuitry

10-Bit Plus Sign

'-6

Converter

Programable

Level Filter

Fault

Queue

Fault

Queue

Fault

Queue

3.0V-3.6V

D+

D-

T_Crit_A

ALERT

SMBData SMBClock

LM86

SNIS114E –DECEMBER 2001–REVISED MARCH 2013

Simplified Block Diagram

Connection Diagram

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VSSOP-8 or SOIC-8

(TOP VIEW)

Pin Description

Label Pin No. Function Typical Connection

D+ 2 transistor junction or to the diode connected transistor junction on a

D− 3 Diode Return Current Sink To Diode Cathode.

T_CRIT_A 4

GND 5 Power Supply Ground Ground

ALERT 6

SMBData 7 SMBCLK 8 SMBus Input From Controller, Pull-Up Resistor

1 Positive Supply Voltage Input DC Voltage from 3.0 V to 3.6 V

Diode Current Source To Diode Anode. Connected to remote discrete diode connected

remote IC whose die temperature is being sensed.

T_CRIT Alarm Output, Open-Drain, Pull-Up Resistor, Controller Interrupt or Power Supply Shutdown Control Active-Low

Interrupt Output, Open-Drain, Pull-Up Resistor, Controller Interrupt or Alert Line Active-Low

SMBus Bi-Directional Data Line, From and to Controller, Pull-Up Resistor Open-Drain Output

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LM86

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Typical Application

SNIS114E –DECEMBER 2001–REVISED MARCH 2013

Product Folder Links: LM86

SNP

V+

GND

ESD

Clamp

I/O

LM86

SNIS114E –DECEMBER 2001–REVISED MARCH 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)

Supply Voltage −0.3 V to 6.0 V Voltage at SMBData, SMBCLK, ALERT, T_CRIT_A −0.5V to 6.0V Voltage at Other Pins −0.3 V to (VDD+ 0.3 V) D− Input Current ±1 mA Input Current at All Other Pins Package Input Current

(2)

±5 mA

30 mA SMBData, ALERT, T_CRIT_A Output Sink Current 10 mA Storage Temperature −65°C to +150°C Soldering Information, Lead Temperature, Vapor Phase (60 seconds) 215°C

SOIC-8 or VSSOP-8 Packages ESD Susceptibility

(4)

(3)

Infrared (15 seconds) 220°C Human Body Model 2000 V Machine Model 200 V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not

apply when operating the device beyond its rated operating conditions.

(2) When the input voltage (VI) at any pin exceeds the power supplies (VI< GND or VI> VDD), the current at that pin should be limited to 5

mA. Parasitic components and or ESD protection circuitry are shown in Table 1 and Figure 1 for the LM86's pins. The nominal breakdown voltage of D3 is 6.5 V. Care should be taken not to forward bias the parasitic diode, D1, present on pins: D+, D−. Doing so

by more than 50 mV may corrupt a temperature measurements. (3) See the URL ”http://www.national.com/packaging/“ for other recommendations and methods of soldering surface mount devices. (4) Human body model, 100pF discharged through a 1.5kΩ resistor. Machine model, 200pF discharged directly into each pin.

Table 1. ESD Protection

Pin Name PIN D1 D2 D3 D4 D5 D6 R1 SNP ESD

VDD(V+) 1 x x D+ 2 x

(1)

x x x x x D− 3 x x x x x x T_CRIT_A 4 x x x ALERT 6 x x x SMBData 7 x x x SMBCLK 8 x

(1) An “x” indicates that the diode exists.

CLAM

Figure 1. ESD Protection Input Structure

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LM86

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SNIS114E –DECEMBER 2001–REVISED MARCH 2013

Operating Ratings

Operating Temperature Range 0°C to +125°C Electrical Characteristics Temperature Range T

MIN≤TA≤TMAX

LM86 0°C≤TA≤+85°C Supply Voltage Range (VDD) +3.0V to +3.6V

Temperature-to-Digital Converter Characteristics

Unless otherwise noted, these specifications apply for VDD=+3.0Vdc to 3.6Vdc. Boldface limits apply for TA= TJ= T

MIN≤TA≤TMAX

Temperature Accuracy Using Local Diode TA= +25°C to +125°C, Temperature Accuracy Using Remote Diode of TA= +30°C TD= +80°C ±0.75 °C (max)

mobile Pentium III with typical nonideality of 1.008. For other processors email hardware.monitor.team@nsc.com to obtain the latest data. (TDis the Remote Diode Junction Temperature)

Remote Diode Measurement Resolution 11 Bits

Local Diode Measurement Resolution 8 Bits

Conversion Time of All Temperatures at the Fastest Setting

Quiescent Current

D− Source Voltage 0.7 V Diode Source Current (D+ − D−)=+ 0.65V; high level 160 315 µA (max)

ALERT and T_CRIT_A Output Saturation Voltage I Power-On Reset Threshold Measure on VDDinput, falling edge 2.4 V (max)

Local and Remote HIGH Default Temperature settings

Local and Remote LOW Default Temperature settings

Local and Remote T_CRIT Default Temperature Setting

; all other limits TA= TJ=+25°C, unless otherwise noted.

Parameter Test Conditions Typical Limits Unit

(1) (2)

(3)

TA= +30°C to +50°C TD= +60°C to ±1

+100°C

TA= +0°C to +85°C TD= +25°C to ±3 °C (max)

+125°C

(4)

(5)

SMBus Inactive, 16Hz conversion rate 0.8 1.7 mA (max) Shutdown 315 µA

Low level 13 20 µA (max)

= 6.0 mA 0.4 V (max)

OUT

(6)

±1 ±3 °C (max)

0.125 °C

1 °C

31.25 34.4 ms (max)

110 µA (min)

7 µA (min)

1.8 V (min)

+70 °C

0 °C

+85 °C

(Limit)

°C (max)

(1) Typical values are at TA= 25°C and represent most likely parametric norm. (2) Limits are guaranteed to National's AOQL (Average Outgoing Quality Level). (3) Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the

internal power dissipation of the LM86 and the thermal resistance. See()for the thermal resistance to be used in the self-heating calculation.

(4) This specification is provided only to indicate how often temperature data is updated. The LM86 can be read at any time without regard

to conversion state (and will yield last conversion result). (5) Quiescent current will not increase substantially with an SMBus. (6) Default values set at power up.

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LM86

SNIS114E –DECEMBER 2001–REVISED MARCH 2013

Logic Electrical Characteristics DIGITAL DC CHARACTERISTICS

Unless otherwise noted, these specifications apply for VDD=+3.0 to 3.6 Vdc. Boldface limits apply for TA= TJ= T T

; all other limits TA= TJ=+25°C, unless otherwise noted.

MAX

Symbol Parameter Test Conditions

SMBData, SMBCLK INPUTS

V V

I I C

IN(1) IN(0)

IN(HYST)

Logical “1” Input Voltage 2.1 V (min) Logical “0”Input Voltage 0.8 V (max) SMBData and SMBCLK Digital Input 400 mV

Hysteresis Logical “1” Input Current VIN= V

Logical “0” Input Current VIN= 0 V −0.005 ±10 µA (max) Input Capacitance 5 pF

ALL DIGITAL OUTPUTS

High Level Output Current VOH= V

SMBus Low Level Output Voltage IOL= 4mA 0.4 V (max)

IOL= 6mA 0.6

(1) Typical values are at TA= 25°C and represent most likely parametric norm. (2) Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Typical

(1)

Limits

(2)

0.005 ±10 µA (max)

10 µA (max)

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MIN

Unit

(Limit)

SMBus DIGITAL SWITCHING CHARACTERISTICS

Unless otherwise noted, these specifications apply for VDD=+3.0 Vdc to +3.6 Vdc, CL(load capacitance) on output lines = 80 pF. Boldface limits apply for TA= TJ= T The switching characteristics of the LM86 fully meet or exceed the published specifications of the SMBus version 2.0. The following parameters are the timing relationships between SMBCLK and SMBData signals related to the LM86. They adhere to but are not necessarily the SMBus bus specifications.

Symbol Parameter Test Conditions

SMB

LOW

HIGH

R,SMB

F,SMB

TIMEOUT

SU;DAT

HD;DAT

HD;STA

SU;STO

SMBus Clock Frequency 100 kHz (max)

SMBus Clock Low Time from V

SMBus Clock High Time from V SMBus Rise Time SMBus Fall Time Output Fall Time CL= 400pF, 250 ns (max)

SMBData and SMBCLK Time Low for Reset of 25 ms (min) Serial Interface

(5)

Data In Setup Time to SMBCLK High 250 ns (min) Data Out Stable after SMBCLK Low 300 ns (min)

Start Condition SMBData Low to SMBCLK Low 100 ns (min) (Start condition hold before the first clock falling edge)

Stop Condition SMBCLK High to SMBData 100 ns (min) Low (Stop Condition Setup)

MIN

to T

; all other limits TA= TJ= +25°C, unless otherwise noted.

MAX

(1)

Limits

1 µs (max)

0.3 µs (max)

IN(0)

IN(1)

(3) (4)

IO= 3mA

max to V

min to V

(4)

Typical

max 4.7 µs (min)

IN(0)

min 4.0 µs (min)

IN(1)

(2)

Unit

(Limit)

10 kHz (min)

25 ms (max)

35 ms (max)

900 ns (max)

(1) Typical values are at TA= 25°C and represent most likely parametric norm. (2) Limits are guaranteed to National's AOQL (Average Outgoing Quality Level). (3) The output rise time is measured from (V (4) The output fall time is measured from (V (5) Holding the SMBData and/or SMBCLK lines Low for a time interval greater than t

therefore setting SMBData and SMBCLK pins to a high impedance state.

max + 0.15V) to (V

IN(0)

min - 0.15V) to (V

IN(1)

min − 0.15V).

IN(1)

min + 0.15V).

IN(1)

will reset the LM86's SMBus state machine,

TIMEOUT

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SMBCLK

SMBDAT

BUF

HD;STA

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

SU;STO

LM86

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SNIS114E –DECEMBER 2001–REVISED MARCH 2013

SMBus DIGITAL SWITCHING CHARACTERISTICS (continued)

Symbol Parameter Test Conditions

SU;STA

BUF

SMBus Repeated Start-Condition Setup Time, 0.6 µs (min) SMBCLK High to SMBData Low

SMBus Free Time Between Stop and Start 1.3 µs (min) Conditions

MIN

to T

; all other limits TA= TJ= +25°C, unless otherwise noted.

MAX

Figure 2. SMBus Communication

Typical

(1)

Limits

(2)

Unit

(Limit)

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0.01 0.1 1.0 10 100

CONVERSION RATE (Hz)

400

600

800

1000

1200

140

1600

1800

2000

SUPPLY CURRENT (PA

LM86

SNIS114E –DECEMBER 2001–REVISED MARCH 2013

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FUNCTIONAL DESCRIPTION

The LM86 temperature sensor incorporates a delta VBEbased temperature sensor using a Local or Remote diode and a 10-bit plus sign ADC (Delta-Sigma Analog-to-Digital Converter). The LM86 is compatible with the serial SMBus version 2.0 two-wire interface. Digital comparators compare the measured Local Temperature (LT) to the Local High (LHS), Local Low (LLS) and Local T_CRIT (LCS) user-programmable temperature limit registers. The measured Remote Temperature (RT) is digitally compared to the Remote High (RHS), Remote Low (RLS) and Remote T_CRIT (RCS) user-programmable temperature limit registers. Activation of the ALERT output indicates that a comparison is greater than the limit preset in a T_CRIT or HIGH limit register or less than the limit preset in a LOW limit register. The T_CRIT_A output responds as a true comparator with built in hysteresis. The hysteresis is set by the value placed in the Hysteresis register (TH). Activation of T_CRIT_A occurs when the temperature is above the T_CRIT setpoint. T_CRIT_A remains activated until the temperature goes below the setpoint calculated by T_CRIT − TH. The hysteresis register impacts both the remote temperature and local temperature readings.

The LM86 may be placed in a low power consumption (Shutdown) mode by setting the RUN/STOP bit found in the Configuration register. In the Shutdown mode, the LM86's SMBus interface remains while all circuitry not required is turned off.

The Local temperature reading and setpoint data registers are 8-bits wide. The format of the 11-bit remote temperature data is a 16-bit left justified word. Two 8-bit registers, high and low bytes, are provided for each setpoint as well as the temperature reading. Two offset registers (RTOLB and RTOHB) can be used to compensate for nonideality error. The remote temperature reading reported is adjusted by subtracting from or adding to the actual temperature reading the value placed in the offset registers.

CONVERSION SEQUENCE

The LM86 takes approximately 31.25 ms to convert the Local Temperature (LT), Remote Temperature (RT), and to update all of its registers. Only during the conversion process the busy bit (D7) in the Status register (02h) is high. These conversions are addressed in a round robin sequence. The conversion rate may be modified by the Conversion Rate Register (04h). When the conversion rate is modified a delay is inserted between conversions, the actual conversion time remains at 31.25ms. Different conversion rates will cause the LM86 to draw different amounts of supply current as shown in Figure 3.

THE ALERT OUTPUT

The LM86's ALERT pin is an active-low open-drain output that is triggered by a temperature conversion that is outside the limits defined by the temperature setpoint registers. Reset of the ALERT output is dependent upon the selected method of use. The LM86's ALERT pin is versatile and will accommodate three different methods of use to best serve the system designer: as a temperature comparator, as a temperature based interrupt flag, and as part of an SMBus ALERT system. The three methods of use are further described below. The ALERT and interrupt methods are different only in how the user interacts with the LM86.

Figure 3. Conversion Rate Effect on Power Supply Current

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Remote High Limit

RDTS Measurement

LM86 ALERT Pin

Status Register: RTDS High

TIME

TEMPERATURE

LM86

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SNIS114E –DECEMBER 2001–REVISED MARCH 2013

Each temperature reading (LT and RT) is associated with a T_CRIT setpoint register (LCS, RCS), a HIGH setpoint register (LHS and RHS) and a LOW setpoint register (LLS and RLS). At the end of every temperature reading, a digital comparison determines whether that reading is above its HIGH or T_CRIT setpoint or below its LOW setpoint. If so, the corresponding bit in the STATUS REGISTER is set. If the ALERT mask bit is not high, any bit set in the STATUS REGISTER, with the exception of Busy (D7) and OPEN (D2), will cause the ALERT output to be pulled low. Any temperature conversion that is out of the limits defined by the temperature setpoint registers will trigger an ALERT. Additionally, the ALERT mask bit in the Configuration register must be cleared to trigger an ALERT in all modes.

ALERT Output as a Temperature Comparator

When the LM86 is implemented in a system in which it is not serviced by an interrupt routine, the ALERT output could be used as a temperature comparator. Under this method of use, once the condition that triggered the ALERT to go low is no longer present, the ALERT is de-asserted (Figure 4). For example, if the ALERT output was activated by the comparison of LT > LHS, when this condition is no longer true the ALERT will return HIGH. This mode allows operation without software intervention, once all registers are configured during set-up. In order for the ALERT to be used as a temperature comparator, bit D0 (the ALERT configure bit) in the FILTER and ALERT CONFIGURE REGISTER (xBF) must be set high. This is not the power on default state.

Figure 4. ALERT Comparator Temperature Response Diagram

ALERT Output as an Interrupt

The LM86's ALERT output can be implemented as a simple interrupt signal when it is used to trigger an interrupt service routine. In such systems it is undesirable for the interrupt flag to repeatedly trigger during or before the interrupt service routine has been completed. Under this method of operation, during a read of the STATUS REGISTER the LM86 will set the ALERT mask bit (D7 of the Configuration register) if any bit in the STATUS REGISTER is set, with the exception of Busy (D7) and OPEN (D2). This prevents further ALERT triggering until the master has reset the ALERT mask bit, at the end of the interrupt service routine. The STATUS REGISTER bits are cleared only upon a read command from the master (see Figure 5) and will be re-asserted at the end of the next conversion if the triggering condition(s) persist(s). In order for the ALERT to be used as a dedicated interrupt signal, bit D0 (the ALERT configure bit) in the FILTER and ALERT CONFIGURE REGISTER (xBF) must be set low. This is the power on default state.

The following sequence describes the response of a system that uses the ALERT output pin as a interrupt flag:

1. Master Senses ALERT low

2. Master reads the LM86 STATUS REGISTER to determine what caused the ALERT

3. LM86 clears STATUS REGISTER, resets the ALERT HIGH and sets the ALERT mask bit (D7 in the Configuration register).

4. Master attends to conditions that caused the ALERT to be triggered. The fan is started, setpoint limits are adjusted, etc.

5. Master resets the ALERT mask (D7 in the Configuration register).

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Remote High Limit

RDTS Measurement

TIME

TEMPERATURE

LM86 ALERT pin

Status Register: RTDS High

End of Temperature conversion

ALERT mask set in response to reading of status register by master

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Figure 5. ALERT Output as an Interrupt Temperature Response Diagram

ALERT Output as an SMBus ALERT

When the ALERT output is connected to one or more ALERT outputs of other SMBus compatible devices and to a master, an SMBus alert line is created. Under this implementation, the LM86's ALERT should be operated using the ARA (Alert Response Address) protocol. The SMBus 2.0 ARA protocol, defined in the SMBus specification 2.0, is a procedure designed to assist the master in resolving which part generated an interrupt and service that interrupt while impeding system operation as little as possible.

The SMBus alert line is connected to the open-drain ports of all devices on the bus thereby AND'ing them together. The ARA is a method by which with one command the SMBus master may identify which part is pulling the SMBus alert line LOW and prevent it from pulling it LOW again for the same triggering condition. When an ARA command is received by all devices on the bus, the devices pulling the SMBus alert line LOW, first, send their address to the master and second, release the SMBus alert line after recognizing a successful transmission of their address.

The SMBus 1.1 and 2.0 specification state that in response to an ARA (Alert Response Address) “after acknowledging the slave address the device must disengage its SMBALERT pulldown”. Furthermore, “if the host still sees SMBALERT low when the message transfer is complete, it knows to read the ARA again”. This SMBus “disengaging of SMBALERT” requirement prevents locking up the SMBus alert line. Competitive parts may address this “disengaging of SMBALERT” requirement differently than the LM86 or not at all. SMBus systems that implement the ARA protocol as suggested for the LM86 will be fully compatible with all competitive parts.

The LM86 fulfills “disengaging of SMBALERT” by setting the ALERT mask bit (bit D7 in the Configuration register, at address 09h) after successfully sending out its address in response to an ARA and releasing the ALERT output pin. Once the ALERT mask bit is activated, the ALERT output pin will be disabled until enabled by software. In order to enable the ALERT the master must read the STATUS REGISTER, at address 02h, during the interrupt service routine and then reset the ALERT mask bit in the Configuration register to 0 at the end of the interrupt service routine.

The following sequence describes the ARA response protocol.

1. Master Senses SMBus alert line low

2. Master sends a START followed by the Alert Response Address (ARA) with a Read Command.

3. Alerting Device(s) send ACK.

4. Alerting Device(s) send their Address. While transmitting their address, alerting devices sense whether their address has been transmitted correctly. (The LM86 will reset its ALERT output and set the ALERT mask bit once its complete address has been transmitted successfully.)

5. Master/slave NoACK

6. Master sends STOP

7. Master attends to conditions that caused the ALERT to be triggered. The STATUS REGISTER is read and fan started, setpoint limits adjusted, etc.

8. Master resets the ALERT mask (D7 in the Configuration register).

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Remote High Limit

RDTS Measurement

TIME

TEMPERATURE

ALERT mask set in response to ARA from master

LM86 ALERT pin

Status Register: RTDS High

LM86

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SNIS114E –DECEMBER 2001–REVISED MARCH 2013

The ARA, 000 1100, is a general call address. No device should ever be assigned this address. Bit D0 (the ALERT configure bit) in the FILTER and ALERT CONFIGURE REGISTER (xBF) must be set low in

order for the LM86 to respond to the ARA command. The ALERT output can be disabled by setting the ALERT mask bit, D7, of the Configuration register. The power

on default is to have the ALERT mask bit and the ALERT configure bit low.

Figure 6. ALERT Output as an SMBus ALERT Temperature Response Diagram

T_CRIT_A OUTPUT and T_CRIT LIMIT

T_CRIT_A is activated when any temperature reading is greater than the limit preset in the critical temperature setpoint register (T_CRIT), as shown in Figure 7. The Status Register can be read to determine which event caused the alarm. A bit in the Status Register is set high to indicate which temperature reading exceeded the T_CRIT setpoint temperature and caused the alarm, see STATUS REGISTER (SR).

Local and remote temperature diodes are sampled in sequence by the A/D converter. The T_CRIT_A output and the Status Register flags are updated after every Local and Remote temperature conversion. T_CRT_A follows the state of the comparison, it is reset when the temperature falls below the setpoint RCS-TH. The Status Register flags are reset only after the Status Register is read and if a temperature conversion(s) is/are below the T_CRIT setpoint, as shown in . Figure 7

Figure 7. T_CRIT_A Temperature Response Diagram

POWER ON RESET DEFAULT STATES

LM86 always powers up to these known default states. The LM86 remains in these states until after the first conversion.

1. Command Register set to 00h

2. Local Temperature set to 0°C

3. Remote Diode Temperature set to 0°C until the end of the first conversion.

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