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LM5170-Q1 EVM
User Manual
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Texas Instruments LM5170-Q1 EVM User Manual

User's Guide
SNVU543A–November 2016–Revised December 2016

LM5170-Q1 EVM User Guide

The EVM can be configured to achieve a bidirectional power converter in the form of either the current source or voltage source. The direction of power flow can be controlled either by an external command signal or by the on-board jumper. Through the onboard interface headers, the EVM can be operated by a DSP, an FPGA, an MCU, or other digital controllers. Two EVMs can be paralleled to make a 3 or 4 phases interleaved converter for higher power. More EVMs can be paralleled for greater number of phases. Many convenient jumper headers are also included for versatile configurations of the EVM.
Refer to the LM5170-Q1 Multiphase Bidirectional Current Controller Datasheet (SNVSAQ6) for detailed technical information of the LM5170-Q1 device.
Contents
1 Features and Electrical Performance ..................................................................................... 3
2 Setup .......................................................................................................................... 4
3 Test Procedure ............................................................................................................. 12
4 Test Data .................................................................................................................... 14
5 Design Files................................................................................................................. 19
List of Figures
1 Simplified EVM Schematic ................................................................................................. 5
2 EVM Board Top View and Layout Partitions............................................................................. 6
3 Bidirectional Converter Bench Setup .................................................................................... 11
4 Buck Mode Efficiency vs Input Voltage and Load Current: V 5 Boost Mode Efficiency vs Input Voltage and Load Current: V
6 Channel DC Current Regulation vs ISETA: Buck Mode .............................................................. 14
7 Channel DC Current Regulation vs ISETA: Boost Mode ............................................................. 14
8 ISETD to ISETA Conversion.............................................................................................. 14
9 Current Sharing Between Two Channels ............................................................................... 14
10 EVM Enable Power-Up Sequence....................................................................................... 15
11 EVM Shutdown by nFAULT............................................................................................... 15
12 Buck Mode Enable......................................................................................................... 15
13 Boost Mode Enable........................................................................................................ 15
14 Dual-Channel Interleaving Operation in Buck Mode: 20 A Per Channel ........................................... 15
15 Dual-Channel Interleaving Operation in Boost Mode: 20 A Per Channel........................................... 15
16 Inductor Current Tracking: Buck Mode.................................................................................. 16
17 Inductor Current Tracking: Boost Mode ................................................................................. 16
18 Diode Emulation During Start-Up ........................................................................................ 16
19 Diode Emulation During Shutdown ...................................................................................... 16
20 Diode Emulation in DCM.................................................................................................. 16
21 Response to Dynamic DIR Change ..................................................................................... 17
22 Step Load Response: Buck Mode; 20-A to 50-A Load Step 1A/μs.................................................. 17
23 Step Load Response: Boost Mode, 5-A to 10-A Load Step 1A/μs .................................................. 17
= 14.5 V.......................................... 14
OUT
= 50.5 V......................................... 14
OUT
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24 OVP in Buck Mode......................................................................................................... 17
25 OVP in Boost Mode........................................................................................................ 17
26 Output Short Circuit: Buck Mode......................................................................................... 18
27 EVM Schematic Part 1: Power Circuit................................................................................... 19
28 EVM Schematic Part 2: Control Circuit.................................................................................. 20
29 EVM Schematic Part 3: Bias Supplies .................................................................................. 21
30 EVM Schematic Part 4: Optional Outer Voltage Loop Control Circuit .............................................. 22
31 EVM Schematic Part 5: Interface Connectors and Configuration Headers......................................... 23
32 EVM Top Layer Silkscreen................................................................................................ 27
33 EVM Top Layer Copper ................................................................................................... 28
34 EVM Middle Layer 1 ....................................................................................................... 29
35 EVM Middle Layer 2 ....................................................................................................... 30
36 EVM Middle Layer 3 ....................................................................................................... 31
37 EVM Middle Layer 4 ....................................................................................................... 32
38 EVM Middle Layer 5 ....................................................................................................... 33
39 EVM Middle Layer 6 ....................................................................................................... 34
40 EVM Bottom Layer Copper ............................................................................................... 35
41 EVM Bottom Layer Silkscreen............................................................................................ 36
List of Tables
1 Electrical Performance...................................................................................................... 4
2 Three-Pin Header Settings................................................................................................. 7
3 Two-Pin Header Settings................................................................................................... 8
4 J17 60-Pin Header Description ............................................................................................ 9
5 J18 60-Pin Header Description........................................................................................... 10
6 Bill of Materials ............................................................................................................. 24
Trademarks
2
LM5170-Q1 EVM User Guide
Copyright © 2016, Texas Instruments Incorporated
SNVU543A–November 2016–Revised December 2016
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1 Features and Electrical Performance

The EVM supports the following features and performance capabilities:
• Input Operating Voltage Ranges – The 48VDC-Port 6 V to 75 V, in the Buck Mode – The 12VDC-Port 3 V to 48 V, in the Boost Mode
• Output Voltage Regulation (With the Onboard Outer Voltage Loop Control Activated) – 14.5-V Output Voltage at the 12VDC-Port, in the Buck Mode – 50.5-V Output Voltage at the 48VDC-Port, in the Boost Mode
• Operating Current – 60-Adc Maximum from or into the 12VDC-Port – Typical 1% Current Regulation Accuracy – Typical 1% Current Monitor Accuracy
• Switching Frequency: – Standalone Fsw = 100 kHz – Able to Synchronize to an External Clock from 80 kHz to 120 kHz.
• Maximum Efficiency: >97%
• OVP Threshold – 75 V at the 48VDC-Port – 22 V at the 12VDC-Port – Synchronous Rectifier Diode Emulation Function Preventing Negative Current
• Other Convenient Features – Optional Onboard Wide-VIN™ LM5118-Q1 Buck-Boost Converter as the +10-V Supply – Onboard Ultra Low IQ TPS709-Q1 LDOs for +3.3-V and +5.0-V Bias Voltages for Convenient EVM
Configurations and for Biasing the External MCU through Headers.
– Onboard LM26LV Temperature Sensors Monitoring Local Temperatures of Power MOSFETs, With
Optional Overtemperature Shutdown and LED Indicator. – LED indicators of Buck and Boost Operating Modes. – Optional Channel Current Shunt AC Filters for Accurate DVM Reading (Unpopulated).
The electrical performance of the EVM is show in Table 1. Figure 1 shows the simplified EVM schematic.
Features and Electrical Performance
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Setup
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Table 1. Electrical Performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
48VDC-Port Buck mode operation (DIR > 2 V) 6 48 70 V 12VDC-Port Boost mode operation (DIR < 1 V) 3 12 48 V
OUTPUT CHARACTERISTICS
Current delivery Current regulation accuracy 12VDC-Port current vs ISETA command voltage 1%
Channel current monitor accuracy
48VDC-Port
12VDC-Port
SYSTEM CHARACTERISTICS
Switching frequency 100 kHz External clock
synchronization Full load efficiency 97% Junction temperature, T
12VDC-Port input or output current (dual-channel enabled)
When onboard IOUT1 and IOUT2 termination filter activated
Boost mode operation (DIR < 1 V, onboard analog output voltage loop closed)
Buck mode operation (DIR > 2 V, onboard analog output voltage loop closed)
J
0 60 A
1%
50.5 V
14.5 V
80 120 kHz
–40 150 °C

2 Setup

2.1 EVM Configurations

Figure 2 shows the EVM board top view and circuit layout partitions. The EVM has the following ports:
• 48VDC-Port: Connected to 48-V battery rail
• 12VDC-Port: Connected to 12-V battery rail
• J17 (60-Pin Header): Interfacing the external control commands or MCU
• J18 (60-Pin Header): Interfacing the slave EVM’s J17 in a 4-phase system consisting of two EVMs
• Master Enable Using J17-pin 5: Providing a voltage of 2.5 V to 6 V to operate the EVM.
• Channel Current Setting: Analog programming at J17-pin 11, and digital programming at J17-pin 13.
Table 2 through Table 5 list the functions of the EVM jumpers and headers. They offer flexible
configurability and programmability of the EVM for various use cases including but not limited to the following:
• A unidirectional or bidirectional current source
• A unidirectional or bidirectional voltage source
• Dynamic phase adding and shedding in a 4-phase system consisting of two EVMs
• Dynamic MOSFETs dead time adjustment
• Individual channel current monitoring or total current monitoring
• Programmable undervoltage lockout (unpopulated)
• Synchronization to external clock
• External shutdown command through nFAULT pin (J17-pin45)
4
LM5170-Q1 EVM User Guide
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+
12VDC-Port
-
23
4.7 µH 1 m
20
22 36 35
470 µF
PGND
6
19
2.2 µF
PGND
34
33
VIN
HO1
HB1
LO1
CSA1
CSB1
BRKG
BRKSVCC
31 VCCA
24.9
1 µF
46 AGND
44
10
39
DIR
UVLO
EN1
43
EN2
40
AGND
42 ISETD
45
ISETA
SYNCIN
41
SYNCOUT
4
28
8
95.3 k
1 nF
VINX
RAMP1
RAMP2
14
0.22 µF
PGND
4.7 µH
1 m
17
15
1 2
PGND
HO2
HB2
LO2
CSA2
CSB2
9.09 k
ENABLE
DIR
ISETA
+
+10Vdc
-
1 nF
26COMP1
11COMP2
15 nF
634
VCC
VCC
1 nF
15 nF
634
1 nF
12
25
9
AGND
SS
OVPA
OVPB
48DT
10 nF
10 k
51.1 k
54.9 k
30IPK
40.2 k
29 OPT
37
IOUT1
38
IOUT2
9.09 k
10 k
47 OSC
40.2 k
10 nF
10 nF
AGND
24
SW1
13
SW2
0.22 µF
IOUT1
IOUT2
27
nFAULT
PGND
+
48VDC-Port
-
VCC
100 µF
100 µF
PGND
470 µF
LM5170-Q1
CMMD AND
MONITOR
C2
C1
C
HB1
Q
H1
Q
L2
C
VCC
C5
C
IOUT1
C
IOUT2
C8
C
HB2
C10
C
SS
C
HF1
C
COMP1
C
RAMP2
C
RAMP1
Q
H2
Q
L2
R
CS2
R
VCCA
R
OSC
R
SYNCO
R
IOUT1
R
IOUT2
R
IPK
R
OVPB
R
OVPA
R
DT
R
COMP1
R
RAMP2
R
RAMP1
R
BRK
D
HB1
D
HB2
18
PGND
PGND
PGND
AGND
C
COMP2
R
COMP2
C
HF2
1 M
L
m1
R
CS1
L
m2
PGND
95.3 k
95.3 NŸ
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Setup
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Figure 1. Simplified EVM Schematic
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Setup
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LM5170-Q1 EVM User Guide
Figure 2. EVM Board Top View and Layout Partitions
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Table 2. Three-Pin Header Settings
HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
(1)
J1 —
J5 OPT
J7 OTEMP
J13 SYNC
J21 BIAS
J28 DIR
J29 EN1
J30 EN2
J31 UVLO
(1)
– = All jumper pins open.
(2)
(1,2) = Pins 1 and 2 closed.
(3)
(2,3) = Pins 2 and 3 closed.
--
(2)
(1,2)
(3)
(2,3)
-- External interleaving control through J17 (1,2) CH-2 240 degree delay from CH-1 (2,3) CH-2 180 degree delay from CH-1 Y
-- Onboard Overtemperature protection disabled Y (1,2) Overtemperature protection in hiccup mode (2,3) Overtemperature protection in latched shutdown
-- Slave EVM not sync to master EVM Y (1,2) Slave EVM sync to master via J18 (2,3) Slave EVM sync to external Clock
-- Use external 10V supply (1,2) Onboard +10V produced from the 12VDC-Port (2,3) Onboard +10V produced from the 48VDC-Port Y
-- External DIR control through J17 (1,2) Onboard DIR command for buck operation Y (2,3) Onboard DIR command for boost operation
-- External CH-1 enable control through J17 (1,2) Onboard CH-1 enable Y (2,3) Onboard CH-1 disable
-­(1,2) Onboard CH-2 enable
(2,3) Onboard CH-2 disable
-- External EVM enable through J17 Y (1,2) (2,3) EVM disable
No UVLO Programming Y 48VDC-Port UVLO Control 12VDC-Port UVLO Control
External CH-1 enable control through J17, overridden by J25.
Onboard EVM enable, if external 3.3V is supplied to J17­pin23.
Setup
Y
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Setup
Table 3. Two-Pin Header Settings
HEADER SIGNAL PINS FUNCTION DESCRIPTION DEFAULT
J2 IOUT1
J3 SYNCOUT
J4 VCC
J6 ISETD
J8 IOUT2
J14 3.3 V
J15 5 V
J16 IOUT_All
J19 10 V
J20 nFAULT
J22 EN
J23 CH1S
J24 IOUT1-2
J25 EN1-2
J26 DTS
J27 DT
J32 OPT/ EN2_slave
J33 ILIM
J34 48VDC Sense
J35 12VDC Sense
J36 ISETA
J37 5 V
(1)
Jumper pins open.
(2)
Jumper pins closed.
(1)
O
(2)
C
O Enable the fault detection Y
C Disable the fault detection disabled
O An external 10-V supply as VCC supply Y
C The onboard 10-V regulator as VCC supply
O ISETD input disabled
C ISETD input is enabled Y
O External IOUT2 signal termination
C Onboard IOUT2 signal termination Y
O Onboard 3.3-V bias voltage disconnected from the slave EVM Y
C Onboard 3.3-V bias voltage feeding the slave EVM
O Onboard 5-V bias voltage disconnected from the slave EVM Y
C Onboard 5-V bias voltage feeding the slave EVM
O Independent channel monitor Y
C
O 10-V bias voltage disconnected from the slave EVM Y
C 10-V bias voltage feeding the slave EVM
O Independent master/slave nFAULT signal Y
C Combined master/slave nFAULT signal
O Independent enable control of the master and slave EVMs Y
C Combined enable control of the master and slave EVMs
O Independent slave EVM CH-1 enable Y
C Combined master/slave channel enable
O Independent channel current monitors Y
C Combined dual-channel current monitor
O Independent channel enable Y
C Combined dual-channel enable
O Independent DT adjustment input for the slave EVM Y
C Combined DT adjustment for both the master and slave EVMs
O External programmable DT adjustment input Y
C Onboard DT setting
O 3- and 4-phase transition disabled Y
C 3- and 4-phases transition enabled O External current limit control input Y — Do not close O Boost analog outer voltage loop control disabled Y
C Boost analog outer voltage loop control enabled O Buck analog outer voltage loop control disabled Y
C Buck analog outer voltage loop control enabled O Analog outer voltage loop control disabled Y
C Analog outer voltage loop control enabled O Analog outer voltage loop control disabled Y
C Analog outer voltage loop control enabled
External IOUT1 termination Onboard IOUT1 termination Y
Combined total monitor in master/slave configuration. Requiring J25 to be closed too.
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Table 4. J17 60-Pin Header Description
(1)
PIN SIGNAL I/O DESCRIPTION
1 V48SN O
(2)
48V-port voltage sense during operation
3 V12SN O 12V-port voltage sense during operation 5
EN (MASTER
ENABLE)
(3)
I
Master EVM enable (connect to the UVLO pin of the IC)
7 CH1 I CH-1 control (connect to the EN1 pin of the IC)
9 DIR I Direction command 11 ISETA I Channel current setting (analog voltage) 13 ISETD I Channel current setting (PWM signal) 15 SYNCIN I Input of the external clock to be synchronized to 17 SYNCOUT O Clock output signal 19 OPT I Interleave angle setting 21 CH2 I CH-2 control (connect to the EN2 pin of the IC) 23 +3.3 V O Output of onboard +3.3-V voltage 25 +5 V O Output of onboard +5-V voltage 27 IOUT1 O CH-1 monitor 29 IOUT2 O CH-2 current monitor 31 IOUT1_S O Slave EVM CH-1 monitor in 3 or 4 phases 33 IOUT2_S O Slave EVM CH-2 current monitor in 3 or 4 phases 35 AGND I/O Reference GND for control signals 37 PGND O Power ground of the DC-DC converter 39 DT I Dead time adjustment pin 41 DT_S I Slave dead time adjustment pin 43 +10 V I/O Input of +10-V bias supply, or output of onboard +10-V bias supply 45 nFAULT I/O Fault report flag, or external shutdown command pin 47 ENABLE_S I Slave EVM enable (connect to the UVLO pin of the slave IC) 49 CH1_S I Slave EVM CH-1 control (connect to the EN1 pin of the slave IC) 51 CH2_S I Slave EVM CH-2 control (connect to the EN2 pin of the slave IC) 53 SYNCIN_S I Input of the external clock for the slave to be synchronized to 55 SYNCOUT_S O Slave EVM clock output signal 57 nFAULT_S I/O Slave EVM fault report flag, or external shut down command input pin 59 KEY — No Connect
All even
number pins
(1)
J17 is the interface connector to MCU, or external digital controller, or to the master EVM’s J18 if the host EVM serves as a slave in the multiphase configuration.
(2)
I = input pin
(3)
O = output pin
AGND I/O All signals’ return
Setup
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Setup
Table 5. J18 60-Pin Header Description
PIN SIGNAL I/O DESCRIPTION
1 V48_X — No Connect
3 V12_X — No Connect
5 ENABLE_S I
7 CH1_S I Slave EVM CH-1 control (connect to the EN1 pin of the IC)
9 DIR I Direction command 11 ISETA I Channel current setting (analog voltage) 13 ISETD I Channel current setting (PWM signal) 15 SYNCIN_S I The external clock input for the slave 17 SYNCOUT_S O 19 OPT I Interleave angle setting 21 CH2_S I Slave EVM CH-2 control (connect to the EN1 pin of the IC) 23 +3.3 V I Output of onboard +3.3-V voltage 25 +5 V I Output of onboard +5-V voltage 27 IOUT1_S O Slave EVM CH-1 monitor in 3 or 4 phases 29 IOUT2_S O Slave EVM CH-2 current monitor in 3 or 4 phases 31 IOUT1_X — Not used 33 IOUT2_X — Not used 35 AGND I/O Reference GND for control signals 37 PGND O Power ground of the DC-DC converter 39 DT_S I Slave EVM dead time adjustment pin 41 DT_X — No Connect 43 +10 V I Input of +10-V bias supply, or output of onboard +10-V bias supply 45 nFAULT_X I/O Slave EVM fault report flag, or external shutdown command pin 47 UVLO_X — No Connect 49 CH1_X — No Connect 51 CH2_X — No Connect 53 SYNCIN_X — No Connect 55 SYNCOUT_X — No Connect 57 nFAULT_X — No Connect 59 KEY — No Connect
All even
number pins
(1)
J18 is the interface connector to the slave EVM in the multiphase configuration if the host EVM serves as the master. All control commands and control signals are sent through J18 to the slave EVM’s J17.
(2)
I = input pin
(3)
O = output pin
AGND I/O All signals’ return
(2)
(3)
Slave EVM enable (connect to the UVLO pin of the slave IC)
Slave EVM clock output signal
(1)
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LM5170-Q1 EVM
+
-
+10 V UVLO EN1/2 DIR
ISETA or
ISETD
+
-
48 VDC
12 VDC
RTN
RTN
HV-PS
LV-PSHV-E-Load
LV-E-Load
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2.2 Bench Setup

Figure 3 shows the typical bench setup to operate the EVM in the bidirectional power system environment.
The combination of the Electronic Load (E-Load) and bench Power Supply (PS) emulates a battery capable of both sourcing and sinking current. A relatively Higher Voltage Power Supply (HV-PS) and E­Load (HV-E-Load) should be used for the 48VDC-port, and a Lower Voltage Power Supply (LV-PS) and E-Load (LV-E-Load) for the 12VDC-port. The external control signals shown as dashed lines can also be created with the onboard headers.
Setup
To operate the EVM to full power, the initial setup should follow the guidelines below:
• Set the LV-E-Load to Constant Current (CC) of 62 A
• Set the LV-PS voltage at 12 V, and the current limit at 63 A
• Set the HV-E-Load to CC of 14 A
• Set the HV-PS voltage at 48 V, and the current limit at 15 A Note that in Buck Mode operation, the HV-E-load can be turned off, and in Boost Mode operation, the LV-
E-load can be turned off. If the output voltage loop is closed, the LV-PS can be disconnected in Buck Mode operation. In Boost Mode operation, the HV-PS is required for Boost start-up, which is limited by the onboard circuit breaker function. If the circuit breaker MOSFETS are shorted and J3 is closed, the HV-PS is not needed for Boost Mode operation.

2.3 Test Equipment

Power Supplies: HV-PS should be capable of 80V/20A, and LV-PS 40V/80A. To operate 2 EVMs in 4 phase configuration, the HV-PS and LV-PS capabilities should be doubled. Bench power supplies to generate UVLO, ISETA, DIR, and EN1 and EN2 signals should be capable of 5V/0.1A.
Electronic Loads: The HV-E-Load should be capable of 80V/20A, and LV-E-Load 40V/80A. To operate 2 EVMs in 4 phase configuration, the E-Loads’ capabilities should be doubled.
Meters: Because most current meters are rated only to 10 A, shunts are recommended to measure the current using a DVM.
Oscilloscope: An oscilloscope and 10x probes with at least 20-MHz bandwidth is required. Current probe capable of 50 A is required to monitor the inductor current via a wire loop inserted to the non-switching side of the inductor.
Figure 3. Bidirectional Converter Bench Setup
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Test Procedure

3 Test Procedure

Please read the LM5170-Q1 datasheet (SNVSAQ6) and this user guide before using the EVM. A typical EVM test bench setup is shown in Figure 2. The power supplies and loads should be capable of handling the input and output voltage and current rating of the board.
The EVM operation requires the four external control signals, which are UVLO, DIR, EN1/2, and ISETA or ISETD (refer to Figure 3).
• UVLO: The master enable command. Apply a voltage > 2.5 V and < 6 V between J17-pins 5 and 6 to enable the EVM. Pulling the voltage at J17-pin 5 low will keep the EVM in shutdown mode.
• DIR: the current direction command. Apply a voltage > 2 V at J17-pin 9 or J18-pin 9 to operate the EVM in Buck Mode. Apply a voltage < 1 V at the same pin to operate the EVM in Boost Mode. DIR command can also be programmed using J28. Note that DIR must be either active high or low to operate the EVM. If the DIR signal is floating, the EVM will not run.
• EN1 and EN2: The channel switching enable commands. Apply a voltage > 2 V at J17-pin 7 will turn on CH-1 converter, and at J17-pin 21 will turn on CH-2 converter. Removing the voltage at the EN1 and EN2 pins to disable each channel. The channel enable can also be controlled by J29, J30 and J25.
• ISETA or ISETD: The Channel current regulation setting. Applying an analog voltage across J17-pins 11 and 12, or J18-pins 11 and 12, or a PWM signal across J17-pins 13 and 14, or J18-pins 13 and 14, the EVM will regulate the channel DC current, which is also the power inductor dc current, to a level proportional the ISETA voltage or ISETD PWM duty ratio. ISETA is controlled by the onboard analog outer voltage control loop when it is closed. Note that, ISETA=1.5 V, or ISETD PWM duty ratio of 48%, will command the EVM to produce 60 A into or out of the 12VDC-port, depending on the operation mode.
For initial test, TI recommends using the onboard 10-V bias supply by closing the J4 and J21-pins 2 and
3. The user can also apply an external 10-V bias supply between J17-Pins 43 and 44, but remember to
open J4 and J21 in order to disable the onboard 10-V bias supply.
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3.1 Buck Mode Power-Up and Power-Down Sequence

1. Refer to Table 2 through Table 5 for proper jumper settings
2. Turn on the HV-PS power supply.
3. Turn on the LV-PS power supply and LV-E-Load.
4. Apply a voltage > 2.5 V and < 6 V at J17-pin 5 (Master Enable).
5. Apply an analog voltage gradually rising from 0V to 1.5V at J17-pin 11 or J18-pin 11 (ISETA), or a PWM signal of duty ratio of 0 to 48% at J17-pin 13 or J18-pin 13.
6. Perform the test.
7. After the tests are done, turn off the ISETA or ISETD signal, remove the voltage at J17-pin 5, and turn off the E-Load, LV-PS and HV-PS.
12
LM5170-Q1 EVM User Guide
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